[RISCV][docs] Describe status of zicsr and zifencei

[reames]

Summary

This has been a repeated point of recent confusion. There are a couple attempts in flight to change the way we handle the extensions, but for the moment, let's just document what's going on.

[asb]

LGTM, thanks!

[jrtc27]

llvm/docs/RISCVUsage.rst

133

Minor tweak to make it more obvious

[reames]

commit 0c412fed360f491e2c33373ffae12e10574a2f0e
Author: Philip Reames <[e-mail]>
Date: Mon Feb 13 09:07:28 2023 -0800

[RISCV][docs] Describe status of zicsr and zifencei

This has been a repeated point of recent confusion. There are a couple attempts in flight to change the way we handle the extensions, but for the moment, let's just document what's going on.

Differential Revision: https://reviews.llvm.org/D14392

(Typo in the differential revision line prevented the auto-close)

llvm/docs/RISCVUsage.rst

.. table:: Ratified Extensions by Status
      ``Zfh``          Supported
      ``Zfhmin``       Supported
      ``Zfinx``        Assembly Support
      ``Zhinx``        Assembly Support
      ``Zhinxmin``     Assembly Support
      ``Zicbom``       Assembly Support
      ``Zicbop``       Assembly Support
      ``Zicboz``       Assembly Support
+     ``Zicsr``        (`See Note <#riscv-i2p1_note>`__)
+     ``Zifencei``     (`See Note <#riscv-i2p1_note>`__)
      ``Zihintpause``  Assembly Support
      ``Zkn``          Supported
      ``Zknd``         Supported (`See note <#riscv-scalar-crypto-note2>`__)
      ``Zkne``         Supported (`See note <#riscv-scalar-crypto-note2>`__)
      ``Zknh``         Supported (`See note <#riscv-scalar-crypto-note2>`__)
      ``Zksed``        Supported (`See note <#riscv-scalar-crypto-note2>`__)
      ``Zksh``         Supported (`See note <#riscv-scalar-crypto-note2>`__)
      ``Zk``           Supported

 ``Zknd``, ``Zkne``, ``Zknh``, ``Zksed``, ``Zksh``
   No pattern matching exists.  As a result, these instructions can only be used from assembler or via intrinsic calls.
 
 .. _riscv-vlen-32-note:
 
 ``Zve32x``, ``Zve32f``, ``Zvl32b``
   LLVM currently assumes a minimum VLEN (vector register width) of 64 bits during compilation, and as a result ``Zve32x`` and ``Zve32f`` are supported only for VLEN>=64.  Assembly support doesn't have this restriction.
 
+.. _riscv-i2p1_note:
+
+``zicsr``, ``zifencei``
+  Between versions 2.0 and 2.1 of the base I specification, a backwards incompatible change was made to remove selected instructions and CSRs from the base ISA.  These instructions were grouped into a set of extensions, but were no longer required by the base ISA.  This change is described in "Preface to Document Version 20190608-Base-Ratified" from the specification.  LLVM currently implements version 2.0 of the base specification.  Thus, instructions from these extensions are accepted as part of the base ISA, but attempts to explicitly enable the extensions will error.
+
 Experimental Extensions
 =======================
 
 LLVM supports (to various degrees) a number of experimental extensions.  All experimental extensions have ``experimental-`` as a prefix.  There is explicitly no compatibility promised between versions of the toolchain, and regular users are strongly advised *not* to make use of experimental extensions before they reach ratification.
 
 The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases.  Experimental extensions are expected to either transition to ratified status, or be eventually removed.  The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised.
 
 ``experimental-zawrs``