[RISCV] Omit SRA in case of setlt or setge with zero constant

[eklepilkina]

Summary

As far as arithmetic right shift always saves the sign, shift can be omitted to check if number is positive or negative.

[eklepilkina]

During fixing this case I had a question why RISCV doesn't use SimplifySetCC from common TargetLowering. It seems that there are some cases of combinations that should work for RISCV. I tried to call it, but found cases that crashes compilations on RISCV. Are there any plans to rework this part and reuse some part of foldings from common lowering? It seems that some optimizations can be lost, doesn't it?

[craig.topper]

In D140206#4001027, @eklepilkina wrote:

During fixing this case I had a question why RISCV doesn't use SimplifySetCC from common TargetLowering. It seems that there are some cases of combinations that should work for RISCV. I tried to call it, but found cases that crashes compilations on RISCV. Are there any plans to rework this part and reuse some part of foldings from common lowering? It seems that some optimizations can be lost, doesn't it?

It should be called from DAGCombiner both before and after type legalization. I think the issue here is that the setcc is merged into RISCVISD::BR_CC before the sign_extend_inreg is converted to shl+sra.

[craig.topper]

llvm/test/CodeGen/RISCV/branch_zero.ll

11

Can you construct a test for GE too?

[eklepilkina]

Test on bge

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

static SDValue tryDemorganOfBooleanCondition(SDValue Cond, SelectionDAG &DAG) {
   unsigned Opc = IsAnd ? ISD::OR : ISD::AND;
   return DAG.getNode(Opc, SDLoc(Cond), VT, Setcc, Xor.getOperand(0));
 }
 
 // Perform common combines for BR_CC and SELECT_CC condtions.
 static bool combine_CC(SDValue &LHS, SDValue &RHS, SDValue &CC, const SDLoc &DL,
                        SelectionDAG &DAG, const RISCVSubtarget &Subtarget) {
   ISD::CondCode CCVal = cast<CondCodeSDNode>(CC)->get();
+
+  // As far as arithmetic right shift always saves the sign,
+  // shift can be omitted.
+  // Fold setlt (sra X, N), 0 -> setlt X, 0 and
+  // setge (sra X, N), 0 -> setge X, 0
+  if (auto *RHSConst = dyn_cast<ConstantSDNode>(RHS.getNode())) {
+    if ((CCVal == ISD::SETGE || CCVal == ISD::SETLT) &&
+        LHS.getOpcode() == ISD::SRA && RHSConst->isZero()) {
+      LHS = LHS.getOperand(0);
+      return true;
+    }
+  }
+
   if (!ISD::isIntEqualitySetCC(CCVal))
     return false;
 
   // Fold ((setlt X, Y), 0, ne) -> (X, Y, lt)
   // Sometimes the setcc is introduced after br_cc/select_cc has been formed.
   if (LHS.getOpcode() == ISD::SETCC && isNullConstant(RHS) &&
       LHS.getOperand(0).getValueType() == Subtarget.getXLenVT()) {
     // If we're looking for eq 0 instead of ne 0, we need to invert the

llvm/test/CodeGen/RISCV/branch_zero.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s
 
 define void @foo(i16 %finder_idx) {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:  .LBB0_1: # %for.body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    bltz a0, .LBB0_4
 ; CHECK-NEXT:  # %bb.2: # %while.cond.preheader.i
 ; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
 ; CHECK-NEXT:    li a0, 0
 ; CHECK-NEXT:    bnez zero, .LBB0_1
 ; CHECK-NEXT:  # %bb.3: # %while.body
 ; CHECK-NEXT:  .LBB0_4: # %while.cond1.preheader.i
 entry:

 }
 
 define void @bar(i16 %finder_idx) {
 ; CHECK-LABEL: bar:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:  .LBB1_1: # %for.body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    bgez a0, .LBB1_4
 ; CHECK-NEXT:  # %bb.2: # %while.cond.preheader.i
 ; CHECK-NEXT:    # in Loop: Header=BB1_1 Depth=1
 ; CHECK-NEXT:    li a0, 0
 ; CHECK-NEXT:    bnez zero, .LBB1_1
 ; CHECK-NEXT:  # %bb.3: # %while.body
 ; CHECK-NEXT:  .LBB1_4: # %while.cond1.preheader.i
 entry: