[RISCV] Allow conversion of fp divisions to fp multiplications by the reciprocal

[asi-sc]

Summary

If the divisor is repeated at least twice, we will convert the FDIVs to the
calculation of the reciprocal and FMULs.

We perform the transformation only under fast-math mode. FDIVs must have
'arcp' flag.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.h

private:
 
   /// Disable normalizing
   /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
   /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y))
   /// RISCV doesn't have flags so it's better to perform the and/or in a GPR.
   bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override {
     return false;
   };
+
+  /// For available scheduling models FDIV + two independent FMULs are much
+  /// faster than two FDIVs.
+  unsigned combineRepeatedFPDivisors() const override;
 };
 namespace RISCVVIntrinsicsTable {
 
 struct RISCVVIntrinsicInfo {
   unsigned IntrinsicID;
   uint8_t ScalarOperand;
   uint8_t VLOperand;
   bool hasScalarOperand() const {

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

static cl::opt<unsigned> ExtensionMaxWebSize(
     cl::init(18));
 
 static cl::opt<bool>
     AllowSplatInVW_W(DEBUG_TYPE "-form-vw-w-with-splat", cl::Hidden,
                      cl::desc("Allow the formation of VW_W operations (e.g., "
                               "VWADD_W) with splat constants"),
                      cl::init(false));
 
+static cl::opt<unsigned> NumRepeatedDivisors(
+    DEBUG_TYPE "-fp-repeated-divisors", cl::Hidden,
+    cl::desc("Set the minimum number of repetitions of a divisor to allow "
+             "transformation to multiplications by the reciprocal"),
+    cl::init(2));
+
 RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
                                          const RISCVSubtarget &STI)
     : TargetLowering(TM), Subtarget(STI) {
 
   if (Subtarget.isRV32E())
     report_fatal_error("Codegen not yet implemented for RV32E");
 
   RISCVABI::ABI ABI = Subtarget.getTargetABI();
bool RISCVTargetLowering::isLegalElementTypeForRVV(Type *ScalarTy) const {
   if (ScalarTy->isFloatTy())
     return Subtarget.hasVInstructionsF32();
   if (ScalarTy->isDoubleTy())
     return Subtarget.hasVInstructionsF64();
 
   return false;
 }
 
+unsigned RISCVTargetLowering::combineRepeatedFPDivisors() const {
+  return NumRepeatedDivisors;
+}
+
 static SDValue getVLOperand(SDValue Op) {
   assert((Op.getOpcode() == ISD::INTRINSIC_WO_CHAIN ||
           Op.getOpcode() == ISD::INTRINSIC_W_CHAIN) &&
          "Unexpected opcode");
   bool HasChain = Op.getOpcode() == ISD::INTRINSIC_W_CHAIN;
   unsigned IntNo = Op.getConstantOperandVal(HasChain ? 1 : 0);
   const RISCVVIntrinsicsTable::RISCVVIntrinsicInfo *II =
       RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntNo);

llvm/test/CodeGen/RISCV/repeated-fp-divisors.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s | FileCheck %s
 
+; Negative test
 define void @single_fdiv(double %a0, double %a1, ptr %res) {
 ; CHECK-LABEL: single_fdiv:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fdiv.d ft0, fa1, fa0
 ; CHECK-NEXT:    fsd ft0, 0(a0)
 ; CHECK-NEXT:    ret
 entry:
   %div = fdiv arcp double %a1, %a0
   store double %div, ptr %res
   ret void
 }
 
 define void @two_fdivs(double %a0, double %a1, double %a2, ptr %res) {
 ; CHECK-LABEL: two_fdivs:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    fdiv.d ft0, fa1, fa0
-; CHECK-NEXT:    fdiv.d ft1, fa2, fa0
-; CHECK-NEXT:    fsd ft0, 0(a0)
-; CHECK-NEXT:    fsd ft1, 8(a0)
+; CHECK-NEXT:    lui a1, %hi(.LCPI1_0)
+; CHECK-NEXT:    fld ft0, %lo(.LCPI1_0)(a1)
+; CHECK-NEXT:    fdiv.d ft0, ft0, fa0
+; CHECK-NEXT:    fmul.d ft1, fa1, ft0
+; CHECK-NEXT:    fmul.d ft0, fa2, ft0
+; CHECK-NEXT:    fsd ft1, 0(a0)
+; CHECK-NEXT:    fsd ft0, 8(a0)
 ; CHECK-NEXT:    ret
 entry:
   %div = fdiv arcp double %a1, %a0
   %div1 = fdiv arcp double %a2, %a0
   store double %div, ptr %res
   %arrayidx2 = getelementptr inbounds double, ptr %res, i64 1
   store double %div1, ptr %arrayidx2
   ret void
 }
 
+; Negative test
 define void @no_arcp(double %a0, double %a1, double %a2, ptr %res) {
 ; CHECK-LABEL: no_arcp:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fdiv.d ft0, fa1, fa0
 ; CHECK-NEXT:    fdiv.d ft1, fa2, fa0
 ; CHECK-NEXT:    fsd ft0, 0(a0)
 ; CHECK-NEXT:    fsd ft1, 8(a0)
 ; CHECK-NEXT:    ret
 entry:
   %div = fdiv arcp double %a1, %a0
   %div1 = fdiv double %a2, %a0
   store double %div, ptr %res
   %arrayidx2 = getelementptr inbounds double, ptr %res, i64 1
   store double %div1, ptr %arrayidx2
   ret void
 }