[RISCV] Add codegen support for RISCV XVentanaCondOps Extension

[kconsul]

Summary

This patch adds codegen support for part of XVentanaCondOps extension.
This extension is designed to reduce the number of branches in
the generated RISCV assembly by replacing branches with conditional
move instructions as defined by XVentanaCondOps specification.

The specification for XVentanaCondOps extension can be found at:
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf

Signed-off-by: Kautuk Consul <[e-mail]>
Signed-off-by: Mikhail Gudim <[e-mail]>

[jrtc27]

D137350

[jrtc27]

llvm/test/CodeGen/RISCV/xventanacondops.ll

2

... why MIR, just do asm like a normal CodeGen test

[reames]

As @jrtc27 mentions, we already have in tree support for XVentanCondOps. This was added in D137350.

Your change does include a number of things which are not currently in tree. Please rebase this patch, and adjust the description to reflect the changes that remain please.

[kconsul]

[RISCV] Add support for RISCV XVentanaCondops Extension

This patch adds support for part of XVentanaCondops extension.
This extension is designed to reduce the number of branches in
the generated RISCV assembly by replacing branches with conditional
move instructions as defined by XVentanaCondops specification.

The specification for XVentanaCondops extension can be found at:
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf

Signed-off-by: Kautuk Consul <[e-mail]>
Signed-off-by: Mikhail Gudim <[e-mail]>

Changes since v1:

• Rebased on the main branch.
• Ported my MASKC/MASKCN changes to VT_MASKC/VT_MASKCN as per Philip Reames' patch which added assembler support for the vt.maskc/vt.maskcn instructions.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4427

This doesn't belong here. It should be done on setOperationAction call that made ISD::SELECT Custom.

I think it's also incorrect here because it disabled SELECT_CC formation for FP selects.

llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td

58

Missing space before (VT_MASKCN

llvm/test/CodeGen/RISCV/xventanacondops.ll

3

Why stop-after finalize-isel?

llvm/test/MC/RISCV/rv64xventanacondops-valid.s

1 ↗

(On Diff #480849)

don't we already have a test called XVentanaCondOps-valid.s?

[asb]

Leaving a comment here for completeness, as I reported back in the other RISC-V extension patches that were put on the agenda for the RISC-V sync call yesterday. We already support these condops at the MC level, so the discussion was mostly focused around the practicalities of getting this patch in a form that can be merged and determining what plans people have for any related follow-up optimisations.

[kconsul]

[RISCV] Add support for RISCV XVentanaCondops Extension

This patch adds support for part of XVentanaCondops extension.
This extension is designed to reduce the number of branches in
the generated RISCV assembly by replacing branches with conditional
move instructions as defined by XVentanaCondops specification.

The specification for XVentanaCondops extension can be found at:
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf

Signed-off-by: Kautuk Consul <[e-mail]>
Signed-off-by: Mikhail Gudim <[e-mail]>

Changes since v2:

• Inserted a space before "(VT_MASKCN"
• Removed the xventanacondops-valid.s and xventanacondops-invalid.s
• Modified the code in RISCVTargetLowering::RISCVTargetLowering() so that the setOperationAction for ISD::SELECT is called only when xvenatancondops attribute is not set.
• Modified the xventanacondops.ll test-case to check till full asm.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

303–304

Use !Subtarget.hasVendorXVentanaCondOps()

llvm/test/CodeGen/RISCV/xventanacondops.ll

3

Drop --check-prefix and use the default CHECK

[kconsul]

[RISCV] Add support for RISCV XVentanaCondops Extension

This patch adds support for part of XVentanaCondops extension.
This extension is designed to reduce the number of branches in
the generated RISCV assembly by replacing branches with conditional
move instructions as defined by XVentanaCondops specification.

The specification for XVentanaCondops extension can be found at:
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf

Signed-off-by: Kautuk Consul <[e-mail]>
Signed-off-by: Mikhail Gudim <[e-mail]>

Changes since v3:

• use Subtarget.hasVendorXVentanaCondOps() in the check in llvm/lib/Target/RISCV/RISCVISelLowering.cpp.
• Drop the -check-prefix=RV64 argument to FileCheck

[kconsul]

This patch adds support for part of XVentanaCondops extension.
This extension is designed to reduce the number of branches in
the generated RISCV assembly by replacing branches with conditional
move instructions as defined by XVentanaCondops specification.

The specification for XVentanaCondops extension can be found at:
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf

Changes since v4:

• Modified the CodeGen/RISCV/select.ll test-case for the implementation of xventanacondops feature in RISCV backend.

[craig.topper]

LGTM with the extra RV64 lines removed from the test.

llvm/test/CodeGen/RISCV/xventanacondops.ll

5

Please remove the stale RV64 lines.

[kconsul]

[RISCV] Add support for RISCV XVentanaCondops Extension patterns

This patch adds support for XVentanaCondops extension patterns.
This extension is designed to reduce the number of branches in
the generated RISCV assembly by replacing branches with conditional
move instructions as defined by XVentanaCondops specification.

The specification for XVentanaCondops extension can be found at:
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf

Signed-off-by: Kautuk Consul <[e-mail]>
Signed-off-by: Mikhail Gudim <[e-mail]>

Changes since v5:

• Removed the RV64 lines from the xventanacondops.ll test-case.

[craig.topper]

LGTM

[jrtc27]

Subject and first line of the description should be clear it's about code generation. As it stands it still sounds like you're adding MC support.

[kconsul]

In D139394#3995937, @jrtc27 wrote:

Subject and first line of the description should be clear it's about code generation. As it stands it still sounds like you're adding MC support.

I have changed the description to state that I am adding support for xventanacondops patterns.

llvm/test/CodeGen/RISCV/xventanacondops.ll

2

I have implemented changes in RISCV backend so that llc generates these instructions for the select pattern. So to test those patterns we would need MIR right ?

[jrtc27]

llvm/test/CodeGen/RISCV/xventanacondops.ll

2

Normally you just test the asm output like you’re doing now

[craig.topper]

"Ops" in "XVentanaCondops" is capitalized in the specification and the code, but not in your patch title or patch description

[kconsul]

In D139394#3997124, @craig.topper wrote:

"Ops" in "XVentanaCondops" is capitalized in the specification and the code, but not in your patch title or patch description

Done.

[reames]

It's not really clear to me that the lowering here is what we want in general. This is certainly more general than the branchless lowerings previously implemented, but at least in several cases, it looks like the branchless lowerings would be better. I've also tagged a bunch of non-optimal lowering cases which the current branchless lowerings don't catch.

llvm/test/CodeGen/RISCV/select.ll

25

Using condops in this case appears to be a regression.

287

We should be able to do better here since 0 is the identity constant for the add.

We should be able to lower this as (add (select cond, a, 0), b). There should only need a single vt.maskc here.

423

Same here with the identity constant observation.

549

We should be able to:
li t1, 43
vt.maskc t1, t1, t0 0 or 43
sub t1, t1, 1 -1 or 42
and a0, a1, t1 // result

796

ashr a, (select cond, %b, 0) would likely be a better expansion.

[craig.topper]

llvm/test/CodeGen/RISCV/select.ll

287

InstCombine already does that transform before we get to SelectionDAG so it might not be an issue in practice.

[craig.topper]

llvm/test/CodeGen/RISCV/select.ll

287

Note there are two operations built into the addw. An add and a sign extension.

Doing a peephole on this in isel would require knowing that the promoted version of %b has 33 sign bits so that addw %b, 0 was equivalent to %b. It doesn't have 33 sign bits because it doesn't have the signext attribute.

It would also be valid if we knew the upper bits of the result didn't matter. But we have lost that information by the time we reach isel.

Alternatively, we could rewrite it before type legalization if we thought it was important.

423

Same issue as the addw above

[reames]

llvm/test/CodeGen/RISCV/select.ll

287

When making the original comment I had not realized this was specific to i32, and that the i64 case looks better below.

Hm, this points out a testing issue here. All of the existing tests are i32, and the added ones are i64. We should probably merge the test files so that the native width codegen is visible with and without.

To be clear, this is not meant to be a blocking comment. More making observations on potential improvements.

[craig.topper]

I modified the description and title to use "codegen support" instead of "patterns" that better matches the recent extension patches like Zca.

[craig.topper]

I think we can commit this and work on improvements in separate patches.

[kconsul]

In D139394#4004113, @craig.topper wrote:

I think we can commit this and work on improvements in separate patches.

Do I do a "git push" for this or will one of you do this for me ?
Sorry but I am new to LLVM reviews.llvm.org procedures for committing a change.

[craig.topper]

In D139394#4004118, @kconsul wrote:

In D139394#4004113, @craig.topper wrote:

I think we can commit this and work on improvements in separate patches.

Do I do a "git push" for this or will one of you do this for me ?
Sorry but I am new to LLVM reviews.llvm.org procedures for committing a change.

If you don't have commit access. I can push it. Should I use "Kautuk Consul <[e-mail]>" for the commit author?

[kconsul]

In D139394#4004119, @craig.topper wrote:

In D139394#4004118, @kconsul wrote:

In D139394#4004113, @craig.topper wrote:

I think we can commit this and work on improvements in separate patches.

Do I do a "git push" for this or will one of you do this for me ?
Sorry but I am new to LLVM reviews.llvm.org procedures for committing a change.

If you don't have commit access. I can push it. Should I use "Kautuk Consul <[e-mail]>" for the commit author?

That and "Mikhail Gudim <[e-mail]>" because I had help from him on this. Thanks!

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td

52

I think the VT_MASKC and VT_MASKCN are swapped in these patterns?

llvm/test/CodeGen/RISCV/xventanacondops.ll

198

I believe this corresponds to "Conditional bitwise-and, if non-zero" in the spec which should have this assembly

and rd, rs1, rs2
vt.maskcn rtmp, rs1, rc
or rd, rd, rtmp

[kconsul]

[RISCV] Add codegen support for RISCV XVentanaCondOps Extension

This patch adds codegen support for part of XVentanaCondops extension.
This extension is designed to reduce the number of branches in
the generated RISCV assembly by replacing branches with conditional
move instructions as defined by XVentanaCondops specification.

The specification for XVentanaCondops extension can be found at:
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf

Signed-off-by: Kautuk Consul <[e-mail]>
Signed-off-by: Mikhail Gudim <[e-mail]>

Changes since v6:

• Swapped the VT_MASKC and VT_MASKCN in the conditional AND patterns.
• Modified the xventanacondops.ll test-case with respect to the conditional AND pattern change.
• Modified the select.ll test-case with respect to the conditional AND pattern change.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Subtarget.is64Bit())
           MVT::i32, Custom);
   } else {
     setOperationAction({ISD::CTTZ, ISD::CTLZ, ISD::CTPOP}, XLenVT, Expand);
   }
 
   if (Subtarget.is64Bit())
     setOperationAction(ISD::ABS, MVT::i32, Custom);
 
+  if (!Subtarget.hasVendorXVentanaCondOps())
     setOperationAction(ISD::SELECT, XLenVT, Custom);
 
   static const unsigned FPLegalNodeTypes[] = {
       ISD::FMINNUM,        ISD::FMAXNUM,       ISD::LRINT,
       ISD::LLRINT,         ISD::LROUND,        ISD::LLROUND,
       ISD::STRICT_LRINT,   ISD::STRICT_LLRINT, ISD::STRICT_LROUND,
       ISD::STRICT_LLROUND, ISD::STRICT_FMA,    ISD::STRICT_FADD,
       ISD::STRICT_FSUB,    ISD::STRICT_FMUL,   ISD::STRICT_FDIV,
       ISD::STRICT_FSQRT,   ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS};
SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
 
   // Lower vector SELECTs to VSELECTs by splatting the condition.
   if (VT.isVector()) {
     MVT SplatCondVT = VT.changeVectorElementType(MVT::i1);
     SDValue CondSplat = DAG.getSplat(SplatCondVT, DL, CondV);
     return DAG.getNode(ISD::VSELECT, DL, VT, CondSplat, TrueV, FalseV);
   }
 
   if (!Subtarget.hasShortForwardBranchOpt()) {
     // (select c, -1, y) -> -c | y
     if (isAllOnesConstant(TrueV)) {
       SDValue Neg = DAG.getNegative(CondV, DL, VT);
       return DAG.getNode(ISD::OR, DL, VT, Neg, FalseV);
     }
     // (select c, y, -1) -> (c-1) | y
     if (isAllOnesConstant(FalseV)) {
       SDValue Neg = DAG.getNode(ISD::ADD, DL, VT, CondV,

llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td

: RVInstR<0b0000000, funct3, OPC_CUSTOM_3, (outs GPR:$rd),
               "$rd, $rs1, $rs2"> {
 }
 
 def VT_MASKC : VTMaskedMove<0b110, "vt.maskc">,
            Sched<[WriteIALU, ReadIALU, ReadIALU]>;
 
 def VT_MASKCN : VTMaskedMove<0b111, "vt.maskcn">,
            Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+
+multiclass XVentanaCondops_pats<SDPatternOperator Op, RVInst MI> {
+  def: Pat<(select i64:$rc, (Op i64:$rs1, i64:$rs2), i64:$rs1),
+           (MI $rs1, (VT_MASKC $rs2, $rc))>;
+  def: Pat<(select i64:$rc, i64:$rs1, (Op i64:$rs1, i64:$rs2)),
+           (MI $rs1, (VT_MASKCN $rs2, $rc))>;
+}
+
+// Directly use MASKC/MASKCN in case of any of the operands being 0.
+def: Pat<(select i64:$rc, i64:$rs1, (i64 0)),
+         (VT_MASKC $rs1, $rc)>;
+def: Pat<(select i64:$rc, (i64 0), i64:$rs1),
+         (VT_MASKCN $rs1, $rc)>;
+
+// Conditional operations patterns.
+defm: XVentanaCondops_pats<add, ADD>;
+defm: XVentanaCondops_pats<sub, SUB>;
+defm: XVentanaCondops_pats<or, OR>;
+defm: XVentanaCondops_pats<xor, XOR>;
+
+// Conditional AND operation patterns.
+def: Pat<(select i64:$rc, (and i64:$rs1, i64:$rs2), i64:$rs1),
+         (OR (AND $rs1, $rs2), (VT_MASKC $rs1, $rc))>;
+def: Pat<(select i64:$rc, i64:$rs1, (and i64:$rs1, i64:$rs2)),
+         (OR (AND $rs1, $rs2), (VT_MASKCN $rs1, $rc))>;
+
+// Basic select pattern that selects between 2 registers.
+def: Pat<(select i64:$rc, i64:$rs1, i64:$rs2),
+         (OR (VT_MASKC $rs1, $rc), (VT_MASKCN $rs2, $rc))>;

llvm/test/CodeGen/RISCV/select.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV32 %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64,NOCONDOPS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+xventanacondops -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64,CONDOPS %s
 
 define i16 @select_xor_1(i16 %A, i8 %cond) {
 ; RV32-LABEL: select_xor_1:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    andi a1, a1, 1
 ; RV32-NEXT:    neg a1, a1
 ; RV32-NEXT:    andi a1, a1, 43
 ; RV32-NEXT:    xor a0, a1, a0
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: select_xor_1:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    andi a1, a1, 1
-; RV64-NEXT:    negw a1, a1
-; RV64-NEXT:    andi a1, a1, 43
-; RV64-NEXT:    xor a0, a1, a0
-; RV64-NEXT:    ret
+; NOCONDOPS-LABEL: select_xor_1:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    andi a1, a1, 1
+; NOCONDOPS-NEXT:    negw a1, a1
+; NOCONDOPS-NEXT:    andi a1, a1, 43
+; NOCONDOPS-NEXT:    xor a0, a1, a0
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_xor_1:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    andi a1, a1, 1
+; CONDOPS-NEXT:    seqz a1, a1
+; CONDOPS-NEXT:    li a2, 43
+; CONDOPS-NEXT:    vt.maskcn a1, a2, a1
+; CONDOPS-NEXT:    xor a0, a0, a1
+; CONDOPS-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp eq i8 %and, 0
  %0 = xor i16 %A, 43
  %1 = select i1 %cmp10, i16 %A, i16 %0
  ret i16 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i16 @select_xor_1b(i16 %A, i8 %cond) {
 ; RV32-LABEL: select_xor_1b:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    andi a1, a1, 1
 ; RV32-NEXT:    neg a1, a1
 ; RV32-NEXT:    andi a1, a1, 43
 ; RV32-NEXT:    xor a0, a1, a0
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: select_xor_1b:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    andi a1, a1, 1
-; RV64-NEXT:    negw a1, a1
-; RV64-NEXT:    andi a1, a1, 43
-; RV64-NEXT:    xor a0, a1, a0
-; RV64-NEXT:    ret
+; NOCONDOPS-LABEL: select_xor_1b:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    andi a1, a1, 1
+; NOCONDOPS-NEXT:    negw a1, a1
+; NOCONDOPS-NEXT:    andi a1, a1, 43
+; NOCONDOPS-NEXT:    xor a0, a1, a0
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_xor_1b:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    andi a1, a1, 1
+; CONDOPS-NEXT:    li a2, 43
+; CONDOPS-NEXT:    vt.maskc a1, a2, a1
+; CONDOPS-NEXT:    xor a0, a0, a1
+; CONDOPS-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp ne i8 %and, 1
  %0 = xor i16 %A, 43
  %1 = select i1 %cmp10, i16 %A, i16 %0
  ret i16 %1
 }
 
 define i32 @select_xor_2(i32 %A, i32 %B, i8 %cond) {
-; CHECK-LABEL: select_xor_2:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    andi a2, a2, 1
-; CHECK-NEXT:    neg a2, a2
-; CHECK-NEXT:    and a1, a2, a1
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: select_xor_2:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    andi a2, a2, 1
+; RV32-NEXT:    neg a2, a2
+; RV32-NEXT:    and a1, a2, a1
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    ret
+;
+; NOCONDOPS-LABEL: select_xor_2:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    andi a2, a2, 1
+; NOCONDOPS-NEXT:    neg a2, a2
+; NOCONDOPS-NEXT:    and a1, a2, a1
+; NOCONDOPS-NEXT:    xor a0, a1, a0
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_xor_2:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    andi a2, a2, 1
+; CONDOPS-NEXT:    seqz a2, a2
+; CONDOPS-NEXT:    vt.maskcn a1, a1, a2
+; CONDOPS-NEXT:    xor a0, a0, a1
+; CONDOPS-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp eq i8 %and, 0
  %0 = xor i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i32 @select_xor_2b(i32 %A, i32 %B, i8 %cond) {
-; CHECK-LABEL: select_xor_2b:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    andi a2, a2, 1
-; CHECK-NEXT:    neg a2, a2
-; CHECK-NEXT:    and a1, a2, a1
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: select_xor_2b:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    andi a2, a2, 1
+; RV32-NEXT:    neg a2, a2
+; RV32-NEXT:    and a1, a2, a1
+; RV32-NEXT:    xor a0, a1, a0
+; RV32-NEXT:    ret
+;
+; NOCONDOPS-LABEL: select_xor_2b:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    andi a2, a2, 1
+; NOCONDOPS-NEXT:    neg a2, a2
+; NOCONDOPS-NEXT:    and a1, a2, a1
+; NOCONDOPS-NEXT:    xor a0, a1, a0
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_xor_2b:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    andi a2, a2, 1
+; CONDOPS-NEXT:    vt.maskc a1, a1, a2
+; CONDOPS-NEXT:    xor a0, a0, a1
+; CONDOPS-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp ne i8 %and, 1
  %0 = xor i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
 define i32 @select_or(i32 %A, i32 %B, i8 %cond) {
-; CHECK-LABEL: select_or:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    andi a2, a2, 1
-; CHECK-NEXT:    neg a2, a2
-; CHECK-NEXT:    and a1, a2, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: select_or:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    andi a2, a2, 1
+; RV32-NEXT:    neg a2, a2
+; RV32-NEXT:    and a1, a2, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    ret
+;
+; NOCONDOPS-LABEL: select_or:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    andi a2, a2, 1
+; NOCONDOPS-NEXT:    neg a2, a2
+; NOCONDOPS-NEXT:    and a1, a2, a1
+; NOCONDOPS-NEXT:    or a0, a1, a0
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_or:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    andi a2, a2, 1
+; CONDOPS-NEXT:    seqz a2, a2
+; CONDOPS-NEXT:    vt.maskcn a1, a1, a2
+; CONDOPS-NEXT:    or a0, a0, a1
+; CONDOPS-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp eq i8 %and, 0
  %0 = or i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i32 @select_or_b(i32 %A, i32 %B, i8 %cond) {
-; CHECK-LABEL: select_or_b:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    andi a2, a2, 1
-; CHECK-NEXT:    neg a2, a2
-; CHECK-NEXT:    and a1, a2, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: select_or_b:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    andi a2, a2, 1
+; RV32-NEXT:    neg a2, a2
+; RV32-NEXT:    and a1, a2, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    ret
+;
+; NOCONDOPS-LABEL: select_or_b:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    andi a2, a2, 1
+; NOCONDOPS-NEXT:    neg a2, a2
+; NOCONDOPS-NEXT:    and a1, a2, a1
+; NOCONDOPS-NEXT:    or a0, a1, a0
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_or_b:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    andi a2, a2, 1
+; CONDOPS-NEXT:    vt.maskc a1, a1, a2
+; CONDOPS-NEXT:    or a0, a0, a1
+; CONDOPS-NEXT:    ret
 entry:
  %and = and i8 %cond, 1
  %cmp10 = icmp ne i8 %and, 1
  %0 = or i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
 define i32 @select_or_1(i32 %A, i32 %B, i32 %cond) {
-; CHECK-LABEL: select_or_1:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    andi a2, a2, 1
-; CHECK-NEXT:    neg a2, a2
-; CHECK-NEXT:    and a1, a2, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: select_or_1:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    andi a2, a2, 1
+; RV32-NEXT:    neg a2, a2
+; RV32-NEXT:    and a1, a2, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    ret
+;
+; NOCONDOPS-LABEL: select_or_1:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    andi a2, a2, 1
+; NOCONDOPS-NEXT:    neg a2, a2
+; NOCONDOPS-NEXT:    and a1, a2, a1
+; NOCONDOPS-NEXT:    or a0, a1, a0
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_or_1:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    andi a2, a2, 1
+; CONDOPS-NEXT:    seqz a2, a2
+; CONDOPS-NEXT:    vt.maskcn a1, a1, a2
+; CONDOPS-NEXT:    or a0, a0, a1
+; CONDOPS-NEXT:    ret
 entry:
  %and = and i32 %cond, 1
  %cmp10 = icmp eq i32 %and, 0
  %0 = or i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
 ; Equivalent to above, but with icmp ne (and %cond, 1), 1 instead of
 ; icmp eq (and %cond, 1), 0
 define i32 @select_or_1b(i32 %A, i32 %B, i32 %cond) {
-; CHECK-LABEL: select_or_1b:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    andi a2, a2, 1
-; CHECK-NEXT:    neg a2, a2
-; CHECK-NEXT:    and a1, a2, a1
-; CHECK-NEXT:    or a0, a1, a0
-; CHECK-NEXT:    ret
+; RV32-LABEL: select_or_1b:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    andi a2, a2, 1
+; RV32-NEXT:    neg a2, a2
+; RV32-NEXT:    and a1, a2, a1
+; RV32-NEXT:    or a0, a1, a0
+; RV32-NEXT:    ret
+;
+; NOCONDOPS-LABEL: select_or_1b:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    andi a2, a2, 1
+; NOCONDOPS-NEXT:    neg a2, a2
+; NOCONDOPS-NEXT:    and a1, a2, a1
+; NOCONDOPS-NEXT:    or a0, a1, a0
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_or_1b:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    andi a2, a2, 1
+; CONDOPS-NEXT:    vt.maskc a1, a1, a2
+; CONDOPS-NEXT:    or a0, a0, a1
+; CONDOPS-NEXT:    ret
 entry:
  %and = and i32 %cond, 1
  %cmp10 = icmp ne i32 %and, 1
  %0 = or i32 %B, %A
  %1 = select i1 %cmp10, i32 %A, i32 %0
  ret i32 %1
 }
 
 define i32 @select_add_1(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_add_1:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    beqz a0, .LBB8_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    add a2, a1, a2
 ; RV32-NEXT:  .LBB8_2: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: select_add_1:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    beqz a0, .LBB8_2
-; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    addw a2, a1, a2
-; RV64-NEXT:  .LBB8_2: # %entry
-; RV64-NEXT:    mv a0, a2
-; RV64-NEXT:    ret
+; NOCONDOPS-LABEL: select_add_1:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    beqz a0, .LBB8_2
+; NOCONDOPS-NEXT:  # %bb.1:
+; NOCONDOPS-NEXT:    addw a2, a1, a2
+; NOCONDOPS-NEXT:  .LBB8_2: # %entry
+; NOCONDOPS-NEXT:    mv a0, a2
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_add_1:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    addw a1, a1, a2
+; CONDOPS-NEXT:    vt.maskcn a2, a2, a0
+; CONDOPS-NEXT:    vt.maskc a0, a1, a0
+; CONDOPS-NEXT:    or a0, a0, a2
+; CONDOPS-NEXT:    ret
 entry:
   %c = add i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_add_2(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_add_2:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    bnez a0, .LBB9_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    add a1, a1, a2
 ; RV32-NEXT:  .LBB9_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: select_add_2:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    bnez a0, .LBB9_2
-; RV64-NEXT:  # %bb.1: # %entry
-; RV64-NEXT:    addw a1, a1, a2
-; RV64-NEXT:  .LBB9_2: # %entry
-; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:    ret
+; NOCONDOPS-LABEL: select_add_2:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    bnez a0, .LBB9_2
+; NOCONDOPS-NEXT:  # %bb.1: # %entry
+; NOCONDOPS-NEXT:    addw a1, a1, a2
+; NOCONDOPS-NEXT:  .LBB9_2: # %entry
+; NOCONDOPS-NEXT:    mv a0, a1
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_add_2:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    addw a2, a1, a2
+; CONDOPS-NEXT:    vt.maskc a1, a1, a0
+; CONDOPS-NEXT:    vt.maskcn a0, a2, a0
+; CONDOPS-NEXT:    or a0, a1, a0
+; CONDOPS-NEXT:    ret
 entry:
   %c = add i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_add_3(i1 zeroext %cond, i32 %a) {
 ; RV32-LABEL: select_add_3:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    bnez a0, .LBB10_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    addi a1, a1, 42
 ; RV32-NEXT:  .LBB10_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: select_add_3:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    bnez a0, .LBB10_2
-; RV64-NEXT:  # %bb.1: # %entry
-; RV64-NEXT:    addiw a1, a1, 42
-; RV64-NEXT:  .LBB10_2: # %entry
-; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:    ret
+; NOCONDOPS-LABEL: select_add_3:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    bnez a0, .LBB10_2
+; NOCONDOPS-NEXT:  # %bb.1: # %entry
+; NOCONDOPS-NEXT:    addiw a1, a1, 42
+; NOCONDOPS-NEXT:  .LBB10_2: # %entry
+; NOCONDOPS-NEXT:    mv a0, a1
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_add_3:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    addiw a2, a1, 42
+; CONDOPS-NEXT:    vt.maskc a1, a1, a0
+; CONDOPS-NEXT:    vt.maskcn a0, a2, a0
+; CONDOPS-NEXT:    or a0, a1, a0
+; CONDOPS-NEXT:    ret
 entry:
   %c = add i32 %a, 42
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_sub_1(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_sub_1:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    beqz a0, .LBB11_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    sub a2, a1, a2
 ; RV32-NEXT:  .LBB11_2: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: select_sub_1:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    beqz a0, .LBB11_2
-; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    subw a2, a1, a2
-; RV64-NEXT:  .LBB11_2: # %entry
-; RV64-NEXT:    mv a0, a2
-; RV64-NEXT:    ret
+; NOCONDOPS-LABEL: select_sub_1:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    beqz a0, .LBB11_2
+; NOCONDOPS-NEXT:  # %bb.1:
+; NOCONDOPS-NEXT:    subw a2, a1, a2
+; NOCONDOPS-NEXT:  .LBB11_2: # %entry
+; NOCONDOPS-NEXT:    mv a0, a2
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_sub_1:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    subw a1, a1, a2
+; CONDOPS-NEXT:    vt.maskcn a2, a2, a0
+; CONDOPS-NEXT:    vt.maskc a0, a1, a0
+; CONDOPS-NEXT:    or a0, a0, a2
+; CONDOPS-NEXT:    ret
 entry:
   %c = sub i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_sub_2(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_sub_2:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    bnez a0, .LBB12_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sub a1, a1, a2
 ; RV32-NEXT:  .LBB12_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: select_sub_2:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    bnez a0, .LBB12_2
-; RV64-NEXT:  # %bb.1: # %entry
-; RV64-NEXT:    subw a1, a1, a2
-; RV64-NEXT:  .LBB12_2: # %entry
-; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:    ret
+; NOCONDOPS-LABEL: select_sub_2:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    bnez a0, .LBB12_2
+; NOCONDOPS-NEXT:  # %bb.1: # %entry
+; NOCONDOPS-NEXT:    subw a1, a1, a2
+; NOCONDOPS-NEXT:  .LBB12_2: # %entry
+; NOCONDOPS-NEXT:    mv a0, a1
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_sub_2:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    subw a2, a1, a2
+; CONDOPS-NEXT:    vt.maskc a1, a1, a0
+; CONDOPS-NEXT:    vt.maskcn a0, a2, a0
+; CONDOPS-NEXT:    or a0, a1, a0
+; CONDOPS-NEXT:    ret
 entry:
   %c = sub i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_sub_3(i1 zeroext %cond, i32 %a) {
 ; RV32-LABEL: select_sub_3:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    bnez a0, .LBB13_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    addi a1, a1, -42
 ; RV32-NEXT:  .LBB13_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: select_sub_3:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    bnez a0, .LBB13_2
-; RV64-NEXT:  # %bb.1: # %entry
-; RV64-NEXT:    addiw a1, a1, -42
-; RV64-NEXT:  .LBB13_2: # %entry
-; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:    ret
+; NOCONDOPS-LABEL: select_sub_3:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    bnez a0, .LBB13_2
+; NOCONDOPS-NEXT:  # %bb.1: # %entry
+; NOCONDOPS-NEXT:    addiw a1, a1, -42
+; NOCONDOPS-NEXT:  .LBB13_2: # %entry
+; NOCONDOPS-NEXT:    mv a0, a1
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_sub_3:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    addiw a2, a1, -42
+; CONDOPS-NEXT:    vt.maskc a1, a1, a0
+; CONDOPS-NEXT:    vt.maskcn a0, a2, a0
+; CONDOPS-NEXT:    or a0, a1, a0
+; CONDOPS-NEXT:    ret
 entry:
   %c = sub i32 %a, 42
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_and_1(i1 zeroext %cond, i32 %a, i32 %b) {
-; CHECK-LABEL: select_and_1:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    beqz a0, .LBB14_2
-; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    and a2, a1, a2
-; CHECK-NEXT:  .LBB14_2: # %entry
-; CHECK-NEXT:    mv a0, a2
-; CHECK-NEXT:    ret
+; RV32-LABEL: select_and_1:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    beqz a0, .LBB14_2
+; RV32-NEXT:  # %bb.1:
+; RV32-NEXT:    and a2, a1, a2
+; RV32-NEXT:  .LBB14_2: # %entry
+; RV32-NEXT:    mv a0, a2
+; RV32-NEXT:    ret
+;
+; NOCONDOPS-LABEL: select_and_1:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    beqz a0, .LBB14_2
+; NOCONDOPS-NEXT:  # %bb.1:
+; NOCONDOPS-NEXT:    and a2, a1, a2
+; NOCONDOPS-NEXT:  .LBB14_2: # %entry
+; NOCONDOPS-NEXT:    mv a0, a2
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_and_1:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    vt.maskc a0, a2, a0
+; CONDOPS-NEXT:    and a1, a2, a1
+; CONDOPS-NEXT:    or a0, a1, a0
+; CONDOPS-NEXT:    ret
 entry:
   %c = and i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_and_2(i1 zeroext %cond, i32 %a, i32 %b) {
-; CHECK-LABEL: select_and_2:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    bnez a0, .LBB15_2
-; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    and a1, a1, a2
-; CHECK-NEXT:  .LBB15_2: # %entry
-; CHECK-NEXT:    mv a0, a1
-; CHECK-NEXT:    ret
+; RV32-LABEL: select_and_2:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    bnez a0, .LBB15_2
+; RV32-NEXT:  # %bb.1: # %entry
+; RV32-NEXT:    and a1, a1, a2
+; RV32-NEXT:  .LBB15_2: # %entry
+; RV32-NEXT:    mv a0, a1
+; RV32-NEXT:    ret
+;
+; NOCONDOPS-LABEL: select_and_2:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    bnez a0, .LBB15_2
+; NOCONDOPS-NEXT:  # %bb.1: # %entry
+; NOCONDOPS-NEXT:    and a1, a1, a2
+; NOCONDOPS-NEXT:  .LBB15_2: # %entry
+; NOCONDOPS-NEXT:    mv a0, a1
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_and_2:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    vt.maskcn a0, a1, a0
+; CONDOPS-NEXT:    and a1, a1, a2
+; CONDOPS-NEXT:    or a0, a1, a0
+; CONDOPS-NEXT:    ret
 entry:
   %c = and i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_and_3(i1 zeroext %cond, i32 %a) {
-; CHECK-LABEL: select_and_3:
-; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    bnez a0, .LBB16_2
-; CHECK-NEXT:  # %bb.1: # %entry
-; CHECK-NEXT:    andi a1, a1, 42
-; CHECK-NEXT:  .LBB16_2: # %entry
-; CHECK-NEXT:    mv a0, a1
-; CHECK-NEXT:    ret
+; RV32-LABEL: select_and_3:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    bnez a0, .LBB16_2
+; RV32-NEXT:  # %bb.1: # %entry
+; RV32-NEXT:    andi a1, a1, 42
+; RV32-NEXT:  .LBB16_2: # %entry
+; RV32-NEXT:    mv a0, a1
+; RV32-NEXT:    ret
+;
+; NOCONDOPS-LABEL: select_and_3:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    bnez a0, .LBB16_2
+; NOCONDOPS-NEXT:  # %bb.1: # %entry
+; NOCONDOPS-NEXT:    andi a1, a1, 42
+; NOCONDOPS-NEXT:  .LBB16_2: # %entry
+; NOCONDOPS-NEXT:    mv a0, a1
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_and_3:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    vt.maskcn a0, a1, a0
+; CONDOPS-NEXT:    li a2, 42
+; CONDOPS-NEXT:    and a1, a1, a2
+; CONDOPS-NEXT:    or a0, a1, a0
+; CONDOPS-NEXT:    ret
 entry:
   %c = and i32 %a, 42
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_udiv_1(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_udiv_1:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    beqz a0, .LBB17_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    divu a2, a1, a2
 ; RV32-NEXT:  .LBB17_2: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: select_udiv_1:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    beqz a0, .LBB17_2
-; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    divuw a2, a1, a2
-; RV64-NEXT:  .LBB17_2: # %entry
-; RV64-NEXT:    mv a0, a2
-; RV64-NEXT:    ret
+; NOCONDOPS-LABEL: select_udiv_1:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    beqz a0, .LBB17_2
+; NOCONDOPS-NEXT:  # %bb.1:
+; NOCONDOPS-NEXT:    divuw a2, a1, a2
+; NOCONDOPS-NEXT:  .LBB17_2: # %entry
+; NOCONDOPS-NEXT:    mv a0, a2
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_udiv_1:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    divuw a1, a1, a2
+; CONDOPS-NEXT:    vt.maskcn a2, a2, a0
+; CONDOPS-NEXT:    vt.maskc a0, a1, a0
+; CONDOPS-NEXT:    or a0, a0, a2
+; CONDOPS-NEXT:    ret
 entry:
   %c = udiv i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_udiv_2(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_udiv_2:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    bnez a0, .LBB18_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    divu a1, a1, a2
 ; RV32-NEXT:  .LBB18_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: select_udiv_2:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    bnez a0, .LBB18_2
-; RV64-NEXT:  # %bb.1: # %entry
-; RV64-NEXT:    divuw a1, a1, a2
-; RV64-NEXT:  .LBB18_2: # %entry
-; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:    ret
+; NOCONDOPS-LABEL: select_udiv_2:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    bnez a0, .LBB18_2
+; NOCONDOPS-NEXT:  # %bb.1: # %entry
+; NOCONDOPS-NEXT:    divuw a1, a1, a2
+; NOCONDOPS-NEXT:  .LBB18_2: # %entry
+; NOCONDOPS-NEXT:    mv a0, a1
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_udiv_2:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    divuw a2, a1, a2
+; CONDOPS-NEXT:    vt.maskc a1, a1, a0
+; CONDOPS-NEXT:    vt.maskcn a0, a2, a0
+; CONDOPS-NEXT:    or a0, a1, a0
+; CONDOPS-NEXT:    ret
 entry:
   %c = udiv i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_udiv_3(i1 zeroext %cond, i32 %a) {
 ; RV32-LABEL: select_udiv_3:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    bnez a0, .LBB19_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    srli a1, a1, 1
 ; RV32-NEXT:    lui a0, 199729
 ; RV32-NEXT:    addi a0, a0, -975
 ; RV32-NEXT:    mulhu a1, a1, a0
 ; RV32-NEXT:    srli a1, a1, 2
 ; RV32-NEXT:  .LBB19_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: select_udiv_3:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    bnez a0, .LBB19_2
-; RV64-NEXT:  # %bb.1: # %entry
-; RV64-NEXT:    srliw a0, a1, 1
-; RV64-NEXT:    lui a1, 199729
-; RV64-NEXT:    addiw a1, a1, -975
-; RV64-NEXT:    mul a1, a0, a1
-; RV64-NEXT:    srli a1, a1, 34
-; RV64-NEXT:  .LBB19_2: # %entry
-; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:    ret
+; NOCONDOPS-LABEL: select_udiv_3:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    bnez a0, .LBB19_2
+; NOCONDOPS-NEXT:  # %bb.1: # %entry
+; NOCONDOPS-NEXT:    srliw a0, a1, 1
+; NOCONDOPS-NEXT:    lui a1, 199729
+; NOCONDOPS-NEXT:    addiw a1, a1, -975
+; NOCONDOPS-NEXT:    mul a1, a0, a1
+; NOCONDOPS-NEXT:    srli a1, a1, 34
+; NOCONDOPS-NEXT:  .LBB19_2: # %entry
+; NOCONDOPS-NEXT:    mv a0, a1
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_udiv_3:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    srliw a2, a1, 1
+; CONDOPS-NEXT:    lui a3, 199729
+; CONDOPS-NEXT:    addiw a3, a3, -975
+; CONDOPS-NEXT:    mul a2, a2, a3
+; CONDOPS-NEXT:    srli a2, a2, 34
+; CONDOPS-NEXT:    vt.maskc a1, a1, a0
+; CONDOPS-NEXT:    vt.maskcn a0, a2, a0
+; CONDOPS-NEXT:    or a0, a1, a0
+; CONDOPS-NEXT:    ret
 entry:
   %c = udiv i32 %a, 42
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_shl_1(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_shl_1:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    beqz a0, .LBB20_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    sll a2, a1, a2
 ; RV32-NEXT:  .LBB20_2: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: select_shl_1:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    beqz a0, .LBB20_2
-; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    sllw a2, a1, a2
-; RV64-NEXT:  .LBB20_2: # %entry
-; RV64-NEXT:    mv a0, a2
-; RV64-NEXT:    ret
+; NOCONDOPS-LABEL: select_shl_1:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    beqz a0, .LBB20_2
+; NOCONDOPS-NEXT:  # %bb.1:
+; NOCONDOPS-NEXT:    sllw a2, a1, a2
+; NOCONDOPS-NEXT:  .LBB20_2: # %entry
+; NOCONDOPS-NEXT:    mv a0, a2
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_shl_1:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    sllw a1, a1, a2
+; CONDOPS-NEXT:    vt.maskcn a2, a2, a0
+; CONDOPS-NEXT:    vt.maskc a0, a1, a0
+; CONDOPS-NEXT:    or a0, a0, a2
+; CONDOPS-NEXT:    ret
 entry:
   %c = shl i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_shl_2(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_shl_2:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    bnez a0, .LBB21_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sll a1, a1, a2
 ; RV32-NEXT:  .LBB21_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: select_shl_2:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    bnez a0, .LBB21_2
-; RV64-NEXT:  # %bb.1: # %entry
-; RV64-NEXT:    sllw a1, a1, a2
-; RV64-NEXT:  .LBB21_2: # %entry
-; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:    ret
+; NOCONDOPS-LABEL: select_shl_2:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    bnez a0, .LBB21_2
+; NOCONDOPS-NEXT:  # %bb.1: # %entry
+; NOCONDOPS-NEXT:    sllw a1, a1, a2
+; NOCONDOPS-NEXT:  .LBB21_2: # %entry
+; NOCONDOPS-NEXT:    mv a0, a1
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_shl_2:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    sllw a2, a1, a2
+; CONDOPS-NEXT:    vt.maskc a1, a1, a0
+; CONDOPS-NEXT:    vt.maskcn a0, a2, a0
+; CONDOPS-NEXT:    or a0, a1, a0
+; CONDOPS-NEXT:    ret
 entry:
   %c = shl i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_shl_3(i1 zeroext %cond, i32 %a) {
 ; CHECK-LABEL: select_shl_3:

 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    beqz a0, .LBB23_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    sra a2, a1, a2
 ; RV32-NEXT:  .LBB23_2: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: select_ashr_1:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    beqz a0, .LBB23_2
-; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    sraw a2, a1, a2
-; RV64-NEXT:  .LBB23_2: # %entry
-; RV64-NEXT:    mv a0, a2
-; RV64-NEXT:    ret
+; NOCONDOPS-LABEL: select_ashr_1:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    beqz a0, .LBB23_2
+; NOCONDOPS-NEXT:  # %bb.1:
+; NOCONDOPS-NEXT:    sraw a2, a1, a2
+; NOCONDOPS-NEXT:  .LBB23_2: # %entry
+; NOCONDOPS-NEXT:    mv a0, a2
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_ashr_1:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    sraw a1, a1, a2
+; CONDOPS-NEXT:    vt.maskcn a2, a2, a0
+; CONDOPS-NEXT:    vt.maskc a0, a1, a0
+; CONDOPS-NEXT:    or a0, a0, a2
+; CONDOPS-NEXT:    ret
 entry:
   %c = ashr i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_ashr_2(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_ashr_2:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    bnez a0, .LBB24_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    sra a1, a1, a2
 ; RV32-NEXT:  .LBB24_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: select_ashr_2:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    bnez a0, .LBB24_2
-; RV64-NEXT:  # %bb.1: # %entry
-; RV64-NEXT:    sraw a1, a1, a2
-; RV64-NEXT:  .LBB24_2: # %entry
-; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:    ret
+; NOCONDOPS-LABEL: select_ashr_2:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    bnez a0, .LBB24_2
+; NOCONDOPS-NEXT:  # %bb.1: # %entry
+; NOCONDOPS-NEXT:    sraw a1, a1, a2
+; NOCONDOPS-NEXT:  .LBB24_2: # %entry
+; NOCONDOPS-NEXT:    mv a0, a1
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_ashr_2:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    sraw a2, a1, a2
+; CONDOPS-NEXT:    vt.maskc a1, a1, a0
+; CONDOPS-NEXT:    vt.maskcn a0, a2, a0
+; CONDOPS-NEXT:    or a0, a1, a0
+; CONDOPS-NEXT:    ret
 entry:
   %c = ashr i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_ashr_3(i1 zeroext %cond, i32 %a) {
 ; CHECK-LABEL: select_ashr_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mv a0, a1

 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    beqz a0, .LBB26_2
 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    srl a2, a1, a2
 ; RV32-NEXT:  .LBB26_2: # %entry
 ; RV32-NEXT:    mv a0, a2
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: select_lshr_1:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    beqz a0, .LBB26_2
-; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    srlw a2, a1, a2
-; RV64-NEXT:  .LBB26_2: # %entry
-; RV64-NEXT:    mv a0, a2
-; RV64-NEXT:    ret
+; NOCONDOPS-LABEL: select_lshr_1:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    beqz a0, .LBB26_2
+; NOCONDOPS-NEXT:  # %bb.1:
+; NOCONDOPS-NEXT:    srlw a2, a1, a2
+; NOCONDOPS-NEXT:  .LBB26_2: # %entry
+; NOCONDOPS-NEXT:    mv a0, a2
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_lshr_1:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    srlw a1, a1, a2
+; CONDOPS-NEXT:    vt.maskcn a2, a2, a0
+; CONDOPS-NEXT:    vt.maskc a0, a1, a0
+; CONDOPS-NEXT:    or a0, a0, a2
+; CONDOPS-NEXT:    ret
 entry:
   %c = lshr i32 %a, %b
   %res = select i1 %cond, i32 %c, i32 %b
   ret i32 %res
 }
 
 define i32 @select_lshr_2(i1 zeroext %cond, i32 %a, i32 %b) {
 ; RV32-LABEL: select_lshr_2:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    bnez a0, .LBB27_2
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    srl a1, a1, a2
 ; RV32-NEXT:  .LBB27_2: # %entry
 ; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
-; RV64-LABEL: select_lshr_2:
-; RV64:       # %bb.0: # %entry
-; RV64-NEXT:    bnez a0, .LBB27_2
-; RV64-NEXT:  # %bb.1: # %entry
-; RV64-NEXT:    srlw a1, a1, a2
-; RV64-NEXT:  .LBB27_2: # %entry
-; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:    ret
+; NOCONDOPS-LABEL: select_lshr_2:
+; NOCONDOPS:       # %bb.0: # %entry
+; NOCONDOPS-NEXT:    bnez a0, .LBB27_2
+; NOCONDOPS-NEXT:  # %bb.1: # %entry
+; NOCONDOPS-NEXT:    srlw a1, a1, a2
+; NOCONDOPS-NEXT:  .LBB27_2: # %entry
+; NOCONDOPS-NEXT:    mv a0, a1
+; NOCONDOPS-NEXT:    ret
+;
+; CONDOPS-LABEL: select_lshr_2:
+; CONDOPS:       # %bb.0: # %entry
+; CONDOPS-NEXT:    srlw a2, a1, a2
+; CONDOPS-NEXT:    vt.maskc a1, a1, a0
+; CONDOPS-NEXT:    vt.maskcn a0, a2, a0
+; CONDOPS-NEXT:    or a0, a1, a0
+; CONDOPS-NEXT:    ret
 entry:
   %c = lshr i32 %a, %b
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 
 define i32 @select_lshr_3(i1 zeroext %cond, i32 %a) {
 ; CHECK-LABEL: select_lshr_3:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    mv a0, a1
 ; CHECK-NEXT:    ret
 entry:
   %c = lshr i32 %a, 42
   %res = select i1 %cond, i32 %a, i32 %c
   ret i32 %res
 }
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CONDOPS: {{.*}}
-; NOCONDOPS: {{.*}}
+; RV64: {{.*}}

llvm/test/CodeGen/RISCV/xventanacondops.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops < %s | FileCheck %s
+
+define i64 @zero1(i64 %rs1, i1 %rc) {
+; RV64-LABEL: zero1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a1, a1, 1
+; RV64-NEXT:    vt.maskc a0, a0, a1
+; RV64-NEXT:    ret
+; CHECK-LABEL: zero1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a1, a1, 1
+; CHECK-NEXT:    vt.maskc a0, a0, a1
+; CHECK-NEXT:    ret
+  %sel = select i1 %rc, i64 %rs1, i64 0
+  ret i64 %sel
+}
+
+define i64 @zero2(i64 %rs1, i1 %rc) {
+; RV64-LABEL: zero2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a1, a1, 1
+; RV64-NEXT:    vt.maskcn a0, a0, a1
+; RV64-NEXT:    ret
+; CHECK-LABEL: zero2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a1, a1, 1
+; CHECK-NEXT:    vt.maskcn a0, a0, a1
+; CHECK-NEXT:    ret
+  %sel = select i1 %rc, i64 0, i64 %rs1
+  ret i64 %sel
+}
+
+define i64 @add1(i1 %rc, i64 %rs1, i64 %rs2) {
+; RV64-LABEL: add1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a0, a0, 1
+; RV64-NEXT:    vt.maskc a0, a2, a0
+; RV64-NEXT:    add a0, a1, a0
+; RV64-NEXT:    ret
+; CHECK-LABEL: add1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    vt.maskc a0, a2, a0
+; CHECK-NEXT:    add a0, a1, a0
+; CHECK-NEXT:    ret
+  %add = add i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %add, i64 %rs1
+  ret i64 %sel
+}
+
+define i64 @add2(i1 %rc, i64 %rs1, i64 %rs2) {
+; RV64-LABEL: add2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a0, a0, 1
+; RV64-NEXT:    vt.maskc a0, a1, a0
+; RV64-NEXT:    add a0, a2, a0
+; RV64-NEXT:    ret
+; CHECK-LABEL: add2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    vt.maskc a0, a1, a0
+; CHECK-NEXT:    add a0, a2, a0
+; CHECK-NEXT:    ret
+  %add = add i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %add, i64 %rs2
+  ret i64 %sel
+}
+
+define i64 @add3(i1 %rc, i64 %rs1, i64 %rs2) {
+; RV64-LABEL: add3:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a0, a0, 1
+; RV64-NEXT:    vt.maskcn a0, a2, a0
+; RV64-NEXT:    add a0, a1, a0
+; RV64-NEXT:    ret
+; CHECK-LABEL: add3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    vt.maskcn a0, a2, a0
+; CHECK-NEXT:    add a0, a1, a0
+; CHECK-NEXT:    ret
+  %add = add i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %rs1, i64 %add
+  ret i64 %sel
+}
+
+define i64 @add4(i1 %rc, i64 %rs1, i64 %rs2) {
+; RV64-LABEL: add4:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a0, a0, 1
+; RV64-NEXT:    vt.maskcn a0, a1, a0
+; RV64-NEXT:    add a0, a2, a0
+; RV64-NEXT:    ret
+; CHECK-LABEL: add4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    vt.maskcn a0, a1, a0
+; CHECK-NEXT:    add a0, a2, a0
+; CHECK-NEXT:    ret
+  %add = add i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %rs2, i64 %add
+  ret i64 %sel
+}
+
+define i64 @sub1(i1 %rc, i64 %rs1, i64 %rs2) {
+; RV64-LABEL: sub1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a0, a0, 1
+; RV64-NEXT:    vt.maskc a0, a2, a0
+; RV64-NEXT:    sub a0, a1, a0
+; RV64-NEXT:    ret
+; CHECK-LABEL: sub1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    vt.maskc a0, a2, a0
+; CHECK-NEXT:    sub a0, a1, a0
+; CHECK-NEXT:    ret
+  %sub = sub i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %sub, i64 %rs1
+  ret i64 %sel
+}
+
+define i64 @sub2(i1 %rc, i64 %rs1, i64 %rs2) {
+; RV64-LABEL: sub2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a0, a0, 1
+; RV64-NEXT:    vt.maskcn a0, a2, a0
+; RV64-NEXT:    sub a0, a1, a0
+; RV64-NEXT:    ret
+; CHECK-LABEL: sub2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    vt.maskcn a0, a2, a0
+; CHECK-NEXT:    sub a0, a1, a0
+; CHECK-NEXT:    ret
+  %sub = sub i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %rs1, i64 %sub
+  ret i64 %sel
+}
+
+define i64 @or1(i1 %rc, i64 %rs1, i64 %rs2) {
+; RV64-LABEL: or1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a0, a0, 1
+; RV64-NEXT:    vt.maskc a0, a2, a0
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+; CHECK-LABEL: or1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    vt.maskc a0, a2, a0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    ret
+  %or = or i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %or, i64 %rs1
+  ret i64 %sel
+}
+
+define i64 @or2(i1 %rc, i64 %rs1, i64 %rs2) {
+; RV64-LABEL: or2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a0, a0, 1
+; RV64-NEXT:    vt.maskc a0, a1, a0
+; RV64-NEXT:    or a0, a2, a0
+; RV64-NEXT:    ret
+; CHECK-LABEL: or2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    vt.maskc a0, a1, a0
+; CHECK-NEXT:    or a0, a2, a0
+; CHECK-NEXT:    ret
+  %or = or i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %or, i64 %rs2
+  ret i64 %sel
+}
+
+define i64 @or3(i1 %rc, i64 %rs1, i64 %rs2) {
+; RV64-LABEL: or3:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a0, a0, 1
+; RV64-NEXT:    vt.maskcn a0, a2, a0
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+; CHECK-LABEL: or3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    vt.maskcn a0, a2, a0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    ret
+  %or = or i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %rs1, i64 %or
+  ret i64 %sel
+}
+
+define i64 @or4(i1 %rc, i64 %rs1, i64 %rs2) {
+; RV64-LABEL: or4:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a0, a0, 1
+; RV64-NEXT:    vt.maskcn a0, a1, a0
+; RV64-NEXT:    or a0, a2, a0
+; RV64-NEXT:    ret
+; CHECK-LABEL: or4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    vt.maskcn a0, a1, a0
+; CHECK-NEXT:    or a0, a2, a0
+; CHECK-NEXT:    ret
+  %or = or i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %rs2, i64 %or
+  ret i64 %sel
+}
+
+define i64 @xor1(i1 %rc, i64 %rs1, i64 %rs2) {
+; RV64-LABEL: xor1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a0, a0, 1
+; RV64-NEXT:    vt.maskc a0, a2, a0
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    ret
+; CHECK-LABEL: xor1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    vt.maskc a0, a2, a0
+; CHECK-NEXT:    xor a0, a1, a0
+; CHECK-NEXT:    ret
+  %xor = xor i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %xor, i64 %rs1
+  ret i64 %sel
+}
+
+define i64 @xor2(i1 %rc, i64 %rs1, i64 %rs2) {
+; RV64-LABEL: xor2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a0, a0, 1
+; RV64-NEXT:    vt.maskc a0, a1, a0
+; RV64-NEXT:    xor a0, a2, a0
+; RV64-NEXT:    ret
+; CHECK-LABEL: xor2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    vt.maskc a0, a1, a0
+; CHECK-NEXT:    xor a0, a2, a0
+; CHECK-NEXT:    ret
+  %xor = xor i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %xor, i64 %rs2
+  ret i64 %sel
+}
+
+define i64 @xor3(i1 %rc, i64 %rs1, i64 %rs2) {
+; RV64-LABEL: xor3:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a0, a0, 1
+; RV64-NEXT:    vt.maskcn a0, a2, a0
+; RV64-NEXT:    xor a0, a1, a0
+; RV64-NEXT:    ret
+; CHECK-LABEL: xor3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    vt.maskcn a0, a2, a0
+; CHECK-NEXT:    xor a0, a1, a0
+; CHECK-NEXT:    ret
+  %xor = xor i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %rs1, i64 %xor
+  ret i64 %sel
+}
+
+define i64 @xor4(i1 %rc, i64 %rs1, i64 %rs2) {
+; RV64-LABEL: xor4:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a0, a0, 1
+; RV64-NEXT:    vt.maskcn a0, a1, a0
+; RV64-NEXT:    xor a0, a2, a0
+; RV64-NEXT:    ret
+; CHECK-LABEL: xor4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    vt.maskcn a0, a1, a0
+; CHECK-NEXT:    xor a0, a2, a0
+; CHECK-NEXT:    ret
+  %xor = xor i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %rs2, i64 %xor
+  ret i64 %sel
+}
+
+define i64 @and1(i1 %rc, i64 %rs1, i64 %rs2) {
+; RV64-LABEL: and1:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a0, a0, 1
+; RV64-NEXT:    and a2, a1, a2
+; RV64-NEXT:    vt.maskc a0, a1, a0
+; RV64-NEXT:    or a0, a2, a0
+; RV64-NEXT:    ret
+; CHECK-LABEL: and1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    and a2, a1, a2
+; CHECK-NEXT:    vt.maskc a0, a1, a0
+; CHECK-NEXT:    or a0, a2, a0
+; CHECK-NEXT:    ret
+  %and = and i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %and, i64 %rs1
+  ret i64 %sel
+}
+
+define i64 @and2(i1 %rc, i64 %rs1, i64 %rs2) {
+; RV64-LABEL: and2:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a0, a0, 1
+; RV64-NEXT:    and a1, a2, a1
+; RV64-NEXT:    vt.maskc a0, a2, a0
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+; CHECK-LABEL: and2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    and a1, a2, a1
+; CHECK-NEXT:    vt.maskc a0, a2, a0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    ret
+  %and = and i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %and, i64 %rs2
+  ret i64 %sel
+}
+
+define i64 @and3(i1 %rc, i64 %rs1, i64 %rs2) {
+; RV64-LABEL: and3:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a0, a0, 1
+; RV64-NEXT:    and a2, a1, a2
+; RV64-NEXT:    vt.maskcn a0, a1, a0
+; RV64-NEXT:    or a0, a2, a0
+; RV64-NEXT:    ret
+; CHECK-LABEL: and3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    and a2, a1, a2
+; CHECK-NEXT:    vt.maskcn a0, a1, a0
+; CHECK-NEXT:    or a0, a2, a0
+; CHECK-NEXT:    ret
+  %and = and i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %rs1, i64 %and
+  ret i64 %sel
+}
+
+define i64 @and4(i1 %rc, i64 %rs1, i64 %rs2) {
+; RV64-LABEL: and4:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a0, a0, 1
+; RV64-NEXT:    and a1, a2, a1
+; RV64-NEXT:    vt.maskcn a0, a2, a0
+; RV64-NEXT:    or a0, a1, a0
+; RV64-NEXT:    ret
+; CHECK-LABEL: and4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    and a1, a2, a1
+; CHECK-NEXT:    vt.maskcn a0, a2, a0
+; CHECK-NEXT:    or a0, a1, a0
+; CHECK-NEXT:    ret
+  %and = and i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %rs2, i64 %and
+  ret i64 %sel
+}
+
+define i64 @basic(i1 %rc, i64 %rs1, i64 %rs2) {
+; RV64-LABEL: basic:
+; RV64:       # %bb.0:
+; RV64-NEXT:    andi a0, a0, 1
+; RV64-NEXT:    vt.maskcn a2, a2, a0
+; RV64-NEXT:    vt.maskc a0, a1, a0
+; RV64-NEXT:    or a0, a0, a2
+; RV64-NEXT:    ret
+; CHECK-LABEL: basic:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andi a0, a0, 1
+; CHECK-NEXT:    vt.maskcn a2, a2, a0
+; CHECK-NEXT:    vt.maskc a0, a1, a0
+; CHECK-NEXT:    or a0, a0, a2
+; CHECK-NEXT:    ret
+  %sel = select i1 %rc, i64 %rs1, i64 %rs2
+  ret i64 %sel
+}