[RISCV] Add codegen support for RISCV XVentanaCondOps Extension

[kconsul]

Summary

This patch adds codegen support for part of XVentanaCondOps extension.
This extension is designed to reduce the number of branches in
the generated RISCV assembly by replacing branches with conditional
move instructions as defined by XVentanaCondOps specification.

The specification for XVentanaCondOps extension can be found at:
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf

Signed-off-by: Kautuk Consul <[e-mail]>
Signed-off-by: Mikhail Gudim <[e-mail]>

[jrtc27]

D137350

[jrtc27]

llvm/test/CodeGen/RISCV/xventanacondops.ll

1

... why MIR, just do asm like a normal CodeGen test

[reames]

As @jrtc27 mentions, we already have in tree support for XVentanCondOps. This was added in D137350.

Your change does include a number of things which are not currently in tree. Please rebase this patch, and adjust the description to reflect the changes that remain please.

[kconsul]

[RISCV] Add support for RISCV XVentanaCondops Extension

This patch adds support for part of XVentanaCondops extension.
This extension is designed to reduce the number of branches in
the generated RISCV assembly by replacing branches with conditional
move instructions as defined by XVentanaCondops specification.

The specification for XVentanaCondops extension can be found at:
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf

Signed-off-by: Kautuk Consul <[e-mail]>
Signed-off-by: Mikhail Gudim <[e-mail]>

Changes since v1:

• Rebased on the main branch.
• Ported my MASKC/MASKCN changes to VT_MASKC/VT_MASKCN as per Philip Reames' patch which added assembler support for the vt.maskc/vt.maskcn instructions.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4225

This doesn't belong here. It should be done on setOperationAction call that made ISD::SELECT Custom.

I think it's also incorrect here because it disabled SELECT_CC formation for FP selects.

llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td

58 ↗

(On Diff #480849)

Missing space before (VT_MASKCN

llvm/test/CodeGen/RISCV/xventanacondops.ll

3

Why stop-after finalize-isel?

llvm/test/MC/RISCV/rv64xventanacondops-valid.s

2

don't we already have a test called XVentanaCondOps-valid.s?

[asb]

Leaving a comment here for completeness, as I reported back in the other RISC-V extension patches that were put on the agenda for the RISC-V sync call yesterday. We already support these condops at the MC level, so the discussion was mostly focused around the practicalities of getting this patch in a form that can be merged and determining what plans people have for any related follow-up optimisations.

[kconsul]

[RISCV] Add support for RISCV XVentanaCondops Extension

This patch adds support for part of XVentanaCondops extension.
This extension is designed to reduce the number of branches in
the generated RISCV assembly by replacing branches with conditional
move instructions as defined by XVentanaCondops specification.

The specification for XVentanaCondops extension can be found at:
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf

Signed-off-by: Kautuk Consul <[e-mail]>
Signed-off-by: Mikhail Gudim <[e-mail]>

Changes since v2:

• Inserted a space before "(VT_MASKCN"
• Removed the xventanacondops-valid.s and xventanacondops-invalid.s
• Modified the code in RISCVTargetLowering::RISCVTargetLowering() so that the setOperationAction for ISD::SELECT is called only when xvenatancondops attribute is not set.
• Modified the xventanacondops.ll test-case to check till full asm.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

302

Use !Subtarget.hasVendorXVentanaCondOps()

llvm/test/CodeGen/RISCV/xventanacondops.ll

3

Drop --check-prefix and use the default CHECK

[kconsul]

[RISCV] Add support for RISCV XVentanaCondops Extension

This patch adds support for part of XVentanaCondops extension.
This extension is designed to reduce the number of branches in
the generated RISCV assembly by replacing branches with conditional
move instructions as defined by XVentanaCondops specification.

The specification for XVentanaCondops extension can be found at:
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf

Signed-off-by: Kautuk Consul <[e-mail]>
Signed-off-by: Mikhail Gudim <[e-mail]>

Changes since v3:

• use Subtarget.hasVendorXVentanaCondOps() in the check in llvm/lib/Target/RISCV/RISCVISelLowering.cpp.
• Drop the -check-prefix=RV64 argument to FileCheck

[kconsul]

This patch adds support for part of XVentanaCondops extension.
This extension is designed to reduce the number of branches in
the generated RISCV assembly by replacing branches with conditional
move instructions as defined by XVentanaCondops specification.

The specification for XVentanaCondops extension can be found at:
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf

Changes since v4:

• Modified the CodeGen/RISCV/select.ll test-case for the implementation of xventanacondops feature in RISCV backend.

[craig.topper]

LGTM with the extra RV64 lines removed from the test.

llvm/test/CodeGen/RISCV/xventanacondops.ll

6

Please remove the stale RV64 lines.

[kconsul]

[RISCV] Add support for RISCV XVentanaCondops Extension patterns

This patch adds support for XVentanaCondops extension patterns.
This extension is designed to reduce the number of branches in
the generated RISCV assembly by replacing branches with conditional
move instructions as defined by XVentanaCondops specification.

The specification for XVentanaCondops extension can be found at:
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf

Signed-off-by: Kautuk Consul <[e-mail]>
Signed-off-by: Mikhail Gudim <[e-mail]>

Changes since v5:

• Removed the RV64 lines from the xventanacondops.ll test-case.

[craig.topper]

LGTM

[jrtc27]

Subject and first line of the description should be clear it's about code generation. As it stands it still sounds like you're adding MC support.

[kconsul]

In D139394#3995937, @jrtc27 wrote:

Subject and first line of the description should be clear it's about code generation. As it stands it still sounds like you're adding MC support.

I have changed the description to state that I am adding support for xventanacondops patterns.

llvm/test/CodeGen/RISCV/xventanacondops.ll

1

I have implemented changes in RISCV backend so that llc generates these instructions for the select pattern. So to test those patterns we would need MIR right ?

[jrtc27]

llvm/test/CodeGen/RISCV/xventanacondops.ll

1

Normally you just test the asm output like you’re doing now

[craig.topper]

"Ops" in "XVentanaCondops" is capitalized in the specification and the code, but not in your patch title or patch description

[kconsul]

In D139394#3997124, @craig.topper wrote:

"Ops" in "XVentanaCondops" is capitalized in the specification and the code, but not in your patch title or patch description

Done.

[reames]

It's not really clear to me that the lowering here is what we want in general. This is certainly more general than the branchless lowerings previously implemented, but at least in several cases, it looks like the branchless lowerings would be better. I've also tagged a bunch of non-optimal lowering cases which the current branchless lowerings don't catch.

llvm/test/CodeGen/RISCV/select.ll

25 ↗

(On Diff #482727)

Using condops in this case appears to be a regression.

287 ↗

(On Diff #482727)

We should be able to do better here since 0 is the identity constant for the add.

We should be able to lower this as (add (select cond, a, 0), b). There should only need a single vt.maskc here.

423 ↗

(On Diff #482727)

Same here with the identity constant observation.

549 ↗

(On Diff #482727)

We should be able to:
li t1, 43
vt.maskc t1, t1, t0 0 or 43
sub t1, t1, 1 -1 or 42
and a0, a1, t1 // result

796 ↗

(On Diff #482727)

ashr a, (select cond, %b, 0) would likely be a better expansion.

[craig.topper]

llvm/test/CodeGen/RISCV/select.ll

287 ↗

(On Diff #482727)

InstCombine already does that transform before we get to SelectionDAG so it might not be an issue in practice.

[craig.topper]

llvm/test/CodeGen/RISCV/select.ll

287 ↗

(On Diff #482727)

Note there are two operations built into the addw. An add and a sign extension.

Doing a peephole on this in isel would require knowing that the promoted version of %b has 33 sign bits so that addw %b, 0 was equivalent to %b. It doesn't have 33 sign bits because it doesn't have the signext attribute.

It would also be valid if we knew the upper bits of the result didn't matter. But we have lost that information by the time we reach isel.

Alternatively, we could rewrite it before type legalization if we thought it was important.

423 ↗

(On Diff #482727)

Same issue as the addw above

[reames]

llvm/test/CodeGen/RISCV/select.ll

287 ↗

(On Diff #482727)

When making the original comment I had not realized this was specific to i32, and that the i64 case looks better below.

Hm, this points out a testing issue here. All of the existing tests are i32, and the added ones are i64. We should probably merge the test files so that the native width codegen is visible with and without.

To be clear, this is not meant to be a blocking comment. More making observations on potential improvements.

[craig.topper]

I modified the description and title to use "codegen support" instead of "patterns" that better matches the recent extension patches like Zca.

[craig.topper]

I think we can commit this and work on improvements in separate patches.

[kconsul]

In D139394#4004113, @craig.topper wrote:

I think we can commit this and work on improvements in separate patches.

Do I do a "git push" for this or will one of you do this for me ?
Sorry but I am new to LLVM reviews.llvm.org procedures for committing a change.

[craig.topper]

In D139394#4004118, @kconsul wrote:

In D139394#4004113, @craig.topper wrote:

I think we can commit this and work on improvements in separate patches.

Do I do a "git push" for this or will one of you do this for me ?
Sorry but I am new to LLVM reviews.llvm.org procedures for committing a change.

If you don't have commit access. I can push it. Should I use "Kautuk Consul <[e-mail]>" for the commit author?

[kconsul]

In D139394#4004119, @craig.topper wrote:

In D139394#4004118, @kconsul wrote:

In D139394#4004113, @craig.topper wrote:

I think we can commit this and work on improvements in separate patches.

Do I do a "git push" for this or will one of you do this for me ?
Sorry but I am new to LLVM reviews.llvm.org procedures for committing a change.

If you don't have commit access. I can push it. Should I use "Kautuk Consul <[e-mail]>" for the commit author?

That and "Mikhail Gudim <[e-mail]>" because I had help from him on this. Thanks!

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td

52 ↗

(On Diff #482727)

I think the VT_MASKC and VT_MASKCN are swapped in these patterns?

llvm/test/CodeGen/RISCV/xventanacondops.ll

198

I believe this corresponds to "Conditional bitwise-and, if non-zero" in the spec which should have this assembly

and rd, rs1, rs2
vt.maskcn rtmp, rs1, rc
or rd, rd, rtmp

[kconsul]

[RISCV] Add codegen support for RISCV XVentanaCondOps Extension

This patch adds codegen support for part of XVentanaCondops extension.
This extension is designed to reduce the number of branches in
the generated RISCV assembly by replacing branches with conditional
move instructions as defined by XVentanaCondops specification.

The specification for XVentanaCondops extension can be found at:
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf

Signed-off-by: Kautuk Consul <[e-mail]>
Signed-off-by: Mikhail Gudim <[e-mail]>

Changes since v6:

• Swapped the VT_MASKC and VT_MASKCN in the conditional AND patterns.
• Modified the xventanacondops.ll test-case with respect to the conditional AND pattern change.
• Modified the select.ll test-case with respect to the conditional AND pattern change.

[craig.topper]

LGTM

llvm/lib/Support/RISCVISAInfo.cpp

static const RISCVSupportedExtension SupportedExtensions[] = {
     {"zve32f", RISCVExtensionVersion{1, 0}},
     {"zve64x", RISCVExtensionVersion{1, 0}},
     {"zve64f", RISCVExtensionVersion{1, 0}},
     {"zve64d", RISCVExtensionVersion{1, 0}},
 
     {"zicbom", RISCVExtensionVersion{1, 0}},
     {"zicboz", RISCVExtensionVersion{1, 0}},
     {"zicbop", RISCVExtensionVersion{1, 0}},
+    {"xventanacondops", RISCVExtensionVersion{1, 0}},
 };
 
 static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
     {"zihintntl", RISCVExtensionVersion{0, 2}},
 
     {"zca", RISCVExtensionVersion{0, 70}},
     {"zvfh", RISCVExtensionVersion{0, 1}},
     {"zawrs", RISCVExtensionVersion{1, 0}},

llvm/lib/Target/RISCV/RISCV.td

 // built with this feature is not ABI-compatible with code built without this
 // feature, if atomic variables are exposed across the ABI boundary.
 def FeatureForcedAtomics : SubtargetFeature<
     "forced-atomics", "HasForcedAtomics", "true",
     "Assume that lock-free native-width atomics are available">;
 def HasAtomicLdSt
     : Predicate<"Subtarget->hasStdExtA() || Subtarget->hasForcedAtomics()">;
 
+def FeatureXVentanaCondops
+    : SubtargetFeature<"xventanacondops", "HasXVentanaCondops", "true",
+                       "X Ventana Conditional Instructions">;
+def HasXVentanaCondops: Predicate<"Subtarget->hasXVentanaCondops()">,
+                           AssemblerPredicate<(all_of FeatureXVentanaCondops),
+                           "X Ventana Conditional Instructions">;
+
 //===----------------------------------------------------------------------===//
 // Named operands for CSR instructions.
 //===----------------------------------------------------------------------===//
 
 include "RISCVSystemOperands.td"
 
 //===----------------------------------------------------------------------===//
 // Registers, calling conventions, instruction descriptions.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Subtarget.is64Bit())
           MVT::i32, Custom);
   } else {
     setOperationAction({ISD::CTTZ, ISD::CTLZ, ISD::CTPOP}, XLenVT, Expand);
 
     if (Subtarget.is64Bit())
       setOperationAction(ISD::ABS, MVT::i32, Custom);
   }
 
   setOperationAction(ISD::SELECT, XLenVT, Custom);
 
   static const unsigned FPLegalNodeTypes[] = {
       ISD::FMINNUM,        ISD::FMAXNUM,       ISD::LRINT,
       ISD::LLRINT,         ISD::LROUND,        ISD::LLROUND,
       ISD::STRICT_LRINT,   ISD::STRICT_LLRINT, ISD::STRICT_LROUND,
       ISD::STRICT_LLROUND, ISD::STRICT_FMA,    ISD::STRICT_FADD,
       ISD::STRICT_FSUB,    ISD::STRICT_FMUL,   ISD::STRICT_FDIV,
       ISD::STRICT_FSQRT,   ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS};
SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
 
   // Lower vector SELECTs to VSELECTs by splatting the condition.
   if (VT.isVector()) {
     MVT SplatCondVT = VT.changeVectorElementType(MVT::i1);
     SDValue CondSplat = DAG.getSplat(SplatCondVT, DL, CondV);
     return DAG.getNode(ISD::VSELECT, DL, VT, CondSplat, TrueV, FalseV);
   }
 
+  // Lower the Op just as it is without any changes.
+  // This will resolve this to Ventana's MASKC/MASKCN instruction
+  // as per the pattern definitions in RISCVInstrInfoXVentanaCondops.td.
+  if (Subtarget.getFeatureBits()[RISCV::FeatureXVentanaCondops]) {
+    return Op;
+  }
+
   // If the CondV is the output of a SETCC node which operates on XLenVT inputs,
   // then merge the SETCC node into the lowered RISCVISD::SELECT_CC to take
   // advantage of the integer compare+branch instructions. i.e.:
   // (select (setcc lhs, rhs, cc), truev, falsev)
   // -> (riscvisd::select_cc lhs, rhs, cc, truev, falsev)
   if (CondV.getOpcode() == ISD::SETCC &&
       CondV.getOperand(0).getSimpleValueType() == XLenVT) {
     SDValue LHS = CondV.getOperand(0);

llvm/lib/Target/RISCV/RISCVInstrFormats.td

 def OPC_NMSUB     : RISCVOpcode<"NMSUB",     0b1001011>;
 def OPC_NMADD     : RISCVOpcode<"NMADD",     0b1001111>;
 def OPC_OP_FP     : RISCVOpcode<"OP_FP",     0b1010011>;
 def OPC_OP_V      : RISCVOpcode<"OP_V",      0b1010111>;
 def OPC_BRANCH    : RISCVOpcode<"BRANCH",    0b1100011>;
 def OPC_JALR      : RISCVOpcode<"JALR",      0b1100111>;
 def OPC_JAL       : RISCVOpcode<"JAL",       0b1101111>;
 def OPC_SYSTEM    : RISCVOpcode<"SYSTEM",    0b1110011>;
+def OPC_CMOV      : RISCVOpcode<"CMOV",      0b1111011>;
 
 class RVInst<dag outs, dag ins, string opcodestr, string argstr,
              list<dag> pattern, InstFormat format>
     : Instruction {
   field bits<32> Inst;
   // SoftFail is a field the disassembler can use to provide a way for
   // instructions to not match without killing the whole decode process. It is
   // mainly used for ARM, but Tablegen expects this field to exist or it fails

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 include "RISCVInstrInfoF.td"
 include "RISCVInstrInfoD.td"
 include "RISCVInstrInfoC.td"
 include "RISCVInstrInfoZb.td"
 include "RISCVInstrInfoZk.td"
 include "RISCVInstrInfoV.td"
 include "RISCVInstrInfoZfh.td"
 include "RISCVInstrInfoZicbo.td"
+include "RISCVInstrInfoXVentanaCondops.td"

llvm/lib/Target/RISCV/RISCVInstrInfoXVentanaCondops.td

+//===-- RISCVInstrInfoXVentanaCondops.td - RISC-V 'xventanacondops' instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V instructions from the custom 'xventanacondops',
+// Ventana's Conditional Move instruction set extension.
+//
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasXVentanaCondops] in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class CMOV_rr<bits<7> funct7, bits<3> funct3, string opcodestr,
+             bit Commutable = 0>
+    : RVInstR<funct7, funct3, OPC_CMOV, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+              opcodestr, "$rd, $rs1, $rs2"> {
+  let isCommutable = Commutable;
+}
+
+def MASKC : CMOV_rr<0b0000000, 0b110, "vt.maskc">,
+           Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+def MASKCN : CMOV_rr<0b0000000, 0b111, "vt.maskcn">,
+           Sched<[WriteIALU, ReadIALU, ReadIALU]>;
+
+multiclass XVentanaCondops_pats<SDPatternOperator Op, RVInst MI> {
+  def: Pat<(select i64:$rc, (Op i64:$rs1, i64:$rs2), i64:$rs1),
+           (MI $rs1, (MASKC $rs2, $rc))>;
+  def: Pat<(select i64:$rc, i64:$rs1, (Op i64:$rs1, i64:$rs2)),
+           (MI $rs1, (MASKCN $rs2, $rc))>;
+}
+
+// Directly use MASKC/MASKCN in case of any of the operands being 0.
+def: Pat<(select i64:$rc, i64:$rs1, (i64 0)),
+         (MASKC $rs1, $rc)>;
+def: Pat<(select i64:$rc, (i64 0), i64:$rs1),
+         (MASKCN $rs1, $rc)>;
+
+// Conditional operations patterns.
+defm: XVentanaCondops_pats<add, ADD>;
+defm: XVentanaCondops_pats<sub, SUB>;
+defm: XVentanaCondops_pats<or, OR>;
+defm: XVentanaCondops_pats<xor, XOR>;
+
+// Conditional AND operation patterns.
+def: Pat<(select i64:$rc, (and i64:$rs1, i64:$rs2), i64:$rs1),
+         (OR (AND $rs1, $rs2), (MASKC $rs1, $rc))>;
+def: Pat<(select i64:$rc, i64:$rs1, (and i64:$rs1, i64:$rs2)),
+         (OR (AND $rs1, $rs2), (MASKCN $rs1, $rc))>;
+
+// Basic select pattern that selects between 2 registers.
+def: Pat<(select i64:$rc, i64:$rs1, i64:$rs2),
+         (OR (MASKC $rs1, $rc),(MASKCN $rs2, $rc))>;
+}

llvm/lib/Target/RISCV/RISCVSubtarget.h

private:
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
   bool EnableRVCHintInstrs = true;
   bool EnableDefaultUnroll = true;
   bool EnableSaveRestore = false;
   bool EnableUnalignedScalarMem = false;
   bool HasLUIADDIFusion = false;
   bool HasForcedAtomics = false;
+  bool HasXVentanaCondops = false;
   unsigned XLen = 32;
   unsigned ZvlLen = 0;
   MVT XLenVT = MVT::i32;
   uint8_t MaxInterleaveFactor = 2;
   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
   std::bitset<RISCV::NUM_TARGET_REGS> UserReservedRegister;
   RISCVFrameLowering FrameLowering;
   RISCVInstrInfo InstrInfo;
public:
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
   bool enableDefaultUnroll() const { return EnableDefaultUnroll; }
   bool enableSaveRestore() const { return EnableSaveRestore; }
   bool enableUnalignedScalarMem() const { return EnableUnalignedScalarMem; }
   bool hasLUIADDIFusion() const { return HasLUIADDIFusion; }
   bool hasForcedAtomics() const { return HasForcedAtomics; }
+  bool hasXVentanaCondops() const { return HasXVentanaCondops; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
   unsigned getFLen() const {
     if (HasStdExtD)
       return 64;
 
     if (HasStdExtF)
       return 32;

llvm/test/CodeGen/RISCV/xventanacondops.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops -stop-after finalize-isel < %s | FileCheck %s -check-prefix=RV64
+
+define i64 @zero1(i64 %rs1, i1 %rc) {
+  ; RV64-LABEL: name: zero1
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1
+  ; RV64-NEXT:   [[MASKC:%[0-9]+]]:gpr = MASKC [[COPY1]], killed [[ANDI]]
+  ; RV64-NEXT:   $x10 = COPY [[MASKC]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %sel = select i1 %rc, i64 %rs1, i64 0
+  ret i64 %sel
+}
+
+define i64 @zero2(i64 %rs1, i1 %rc) {
+  ; RV64-LABEL: name: zero2
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1
+  ; RV64-NEXT:   [[MASKCN:%[0-9]+]]:gpr = MASKCN [[COPY1]], killed [[ANDI]]
+  ; RV64-NEXT:   $x10 = COPY [[MASKCN]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %sel = select i1 %rc, i64 0, i64 %rs1
+  ret i64 %sel
+}
+
+define i64 @add1(i1 %rc, i64 %rs1, i64 %rs2) {
+  ; RV64-LABEL: name: add1
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x12
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
+  ; RV64-NEXT:   [[MASKC:%[0-9]+]]:gpr = MASKC [[COPY]], killed [[ANDI]]
+  ; RV64-NEXT:   [[ADD:%[0-9]+]]:gpr = ADD [[COPY1]], killed [[MASKC]]
+  ; RV64-NEXT:   $x10 = COPY [[ADD]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %add = add i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %add, i64 %rs1
+  ret i64 %sel
+}
+
+define i64 @add2(i1 %rc, i64 %rs1, i64 %rs2) {
+  ; RV64-LABEL: name: add2
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x12
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
+  ; RV64-NEXT:   [[MASKC:%[0-9]+]]:gpr = MASKC [[COPY1]], killed [[ANDI]]
+  ; RV64-NEXT:   [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], killed [[MASKC]]
+  ; RV64-NEXT:   $x10 = COPY [[ADD]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %add = add i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %add, i64 %rs2
+  ret i64 %sel
+}
+
+define i64 @add3(i1 %rc, i64 %rs1, i64 %rs2) {
+  ; RV64-LABEL: name: add3
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x12
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
+  ; RV64-NEXT:   [[MASKCN:%[0-9]+]]:gpr = MASKCN [[COPY]], killed [[ANDI]]
+  ; RV64-NEXT:   [[ADD:%[0-9]+]]:gpr = ADD [[COPY1]], killed [[MASKCN]]
+  ; RV64-NEXT:   $x10 = COPY [[ADD]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %add = add i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %rs1, i64 %add
+  ret i64 %sel
+}
+
+define i64 @add4(i1 %rc, i64 %rs1, i64 %rs2) {
+  ; RV64-LABEL: name: add4
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x12
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
+  ; RV64-NEXT:   [[MASKCN:%[0-9]+]]:gpr = MASKCN [[COPY1]], killed [[ANDI]]
+  ; RV64-NEXT:   [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], killed [[MASKCN]]
+  ; RV64-NEXT:   $x10 = COPY [[ADD]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %add = add i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %rs2, i64 %add
+  ret i64 %sel
+}
+
+define i64 @sub1(i1 %rc, i64 %rs1, i64 %rs2) {
+  ; RV64-LABEL: name: sub1
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x12
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
+  ; RV64-NEXT:   [[MASKC:%[0-9]+]]:gpr = MASKC [[COPY]], killed [[ANDI]]
+  ; RV64-NEXT:   [[SUB:%[0-9]+]]:gpr = SUB [[COPY1]], killed [[MASKC]]
+  ; RV64-NEXT:   $x10 = COPY [[SUB]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %sub = sub i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %sub, i64 %rs1
+  ret i64 %sel
+}
+
+define i64 @sub2(i1 %rc, i64 %rs1, i64 %rs2) {
+  ; RV64-LABEL: name: sub2
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x12
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
+  ; RV64-NEXT:   [[MASKCN:%[0-9]+]]:gpr = MASKCN [[COPY]], killed [[ANDI]]
+  ; RV64-NEXT:   [[SUB:%[0-9]+]]:gpr = SUB [[COPY1]], killed [[MASKCN]]
+  ; RV64-NEXT:   $x10 = COPY [[SUB]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %sub = sub i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %rs1, i64 %sub
+  ret i64 %sel
+}
+
+define i64 @or1(i1 %rc, i64 %rs1, i64 %rs2) {
+  ; RV64-LABEL: name: or1
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x12
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
+  ; RV64-NEXT:   [[MASKC:%[0-9]+]]:gpr = MASKC [[COPY]], killed [[ANDI]]
+  ; RV64-NEXT:   [[OR:%[0-9]+]]:gpr = OR [[COPY1]], killed [[MASKC]]
+  ; RV64-NEXT:   $x10 = COPY [[OR]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %or = or i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %or, i64 %rs1
+  ret i64 %sel
+}
+
+define i64 @or2(i1 %rc, i64 %rs1, i64 %rs2) {
+  ; RV64-LABEL: name: or2
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x12
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
+  ; RV64-NEXT:   [[MASKC:%[0-9]+]]:gpr = MASKC [[COPY1]], killed [[ANDI]]
+  ; RV64-NEXT:   [[OR:%[0-9]+]]:gpr = OR [[COPY]], killed [[MASKC]]
+  ; RV64-NEXT:   $x10 = COPY [[OR]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %or = or i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %or, i64 %rs2
+  ret i64 %sel
+}
+
+define i64 @or3(i1 %rc, i64 %rs1, i64 %rs2) {
+  ; RV64-LABEL: name: or3
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x12
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
+  ; RV64-NEXT:   [[MASKCN:%[0-9]+]]:gpr = MASKCN [[COPY]], killed [[ANDI]]
+  ; RV64-NEXT:   [[OR:%[0-9]+]]:gpr = OR [[COPY1]], killed [[MASKCN]]
+  ; RV64-NEXT:   $x10 = COPY [[OR]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %or = or i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %rs1, i64 %or
+  ret i64 %sel
+}
+
+define i64 @or4(i1 %rc, i64 %rs1, i64 %rs2) {
+  ; RV64-LABEL: name: or4
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x12
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
+  ; RV64-NEXT:   [[MASKCN:%[0-9]+]]:gpr = MASKCN [[COPY1]], killed [[ANDI]]
+  ; RV64-NEXT:   [[OR:%[0-9]+]]:gpr = OR [[COPY]], killed [[MASKCN]]
+  ; RV64-NEXT:   $x10 = COPY [[OR]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %or = or i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %rs2, i64 %or
+  ret i64 %sel
+}
+
+define i64 @xor1(i1 %rc, i64 %rs1, i64 %rs2) {
+  ; RV64-LABEL: name: xor1
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x12
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
+  ; RV64-NEXT:   [[MASKC:%[0-9]+]]:gpr = MASKC [[COPY]], killed [[ANDI]]
+  ; RV64-NEXT:   [[XOR:%[0-9]+]]:gpr = XOR [[COPY1]], killed [[MASKC]]
+  ; RV64-NEXT:   $x10 = COPY [[XOR]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %xor = xor i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %xor, i64 %rs1
+  ret i64 %sel
+}
+
+define i64 @xor2(i1 %rc, i64 %rs1, i64 %rs2) {
+  ; RV64-LABEL: name: xor2
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x12
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
+  ; RV64-NEXT:   [[MASKC:%[0-9]+]]:gpr = MASKC [[COPY1]], killed [[ANDI]]
+  ; RV64-NEXT:   [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], killed [[MASKC]]
+  ; RV64-NEXT:   $x10 = COPY [[XOR]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %xor = xor i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %xor, i64 %rs2
+  ret i64 %sel
+}
+
+define i64 @xor3(i1 %rc, i64 %rs1, i64 %rs2) {
+  ; RV64-LABEL: name: xor3
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x12
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
+  ; RV64-NEXT:   [[MASKCN:%[0-9]+]]:gpr = MASKCN [[COPY]], killed [[ANDI]]
+  ; RV64-NEXT:   [[XOR:%[0-9]+]]:gpr = XOR [[COPY1]], killed [[MASKCN]]
+  ; RV64-NEXT:   $x10 = COPY [[XOR]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %xor = xor i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %rs1, i64 %xor
+  ret i64 %sel
+}
+
+define i64 @xor4(i1 %rc, i64 %rs1, i64 %rs2) {
+  ; RV64-LABEL: name: xor4
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x12
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
+  ; RV64-NEXT:   [[MASKCN:%[0-9]+]]:gpr = MASKCN [[COPY1]], killed [[ANDI]]
+  ; RV64-NEXT:   [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], killed [[MASKCN]]
+  ; RV64-NEXT:   $x10 = COPY [[XOR]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %xor = xor i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %rs2, i64 %xor
+  ret i64 %sel
+}
+
+define i64 @and1(i1 %rc, i64 %rs1, i64 %rs2) {
+  ; RV64-LABEL: name: and1
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x12
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
+  ; RV64-NEXT:   [[XORI:%[0-9]+]]:gpr = XORI [[COPY]], -1
+  ; RV64-NEXT:   [[MASKC:%[0-9]+]]:gpr = MASKC killed [[XORI]], killed [[ANDI]]
+  ; RV64-NEXT:   [[ANDN:%[0-9]+]]:gpr = ANDN [[COPY1]], killed [[MASKC]]
+  ; RV64-NEXT:   $x10 = COPY [[ANDN]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %and = and i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %and, i64 %rs1
+  ret i64 %sel
+}
+
+define i64 @and2(i1 %rc, i64 %rs1, i64 %rs2) {
+  ; RV64-LABEL: name: and2
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x12
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
+  ; RV64-NEXT:   [[XORI:%[0-9]+]]:gpr = XORI [[COPY1]], -1
+  ; RV64-NEXT:   [[MASKC:%[0-9]+]]:gpr = MASKC killed [[XORI]], killed [[ANDI]]
+  ; RV64-NEXT:   [[ANDN:%[0-9]+]]:gpr = ANDN [[COPY]], killed [[MASKC]]
+  ; RV64-NEXT:   $x10 = COPY [[ANDN]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %and = and i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %and, i64 %rs2
+  ret i64 %sel
+}
+
+define i64 @and3(i1 %rc, i64 %rs1, i64 %rs2) {
+  ; RV64-LABEL: name: and3
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x12
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
+  ; RV64-NEXT:   [[XORI:%[0-9]+]]:gpr = XORI [[COPY]], -1
+  ; RV64-NEXT:   [[MASKCN:%[0-9]+]]:gpr = MASKCN killed [[XORI]], killed [[ANDI]]
+  ; RV64-NEXT:   [[ANDN:%[0-9]+]]:gpr = ANDN [[COPY1]], killed [[MASKCN]]
+  ; RV64-NEXT:   $x10 = COPY [[ANDN]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %and = and i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %rs1, i64 %and
+  ret i64 %sel
+}
+
+define i64 @and4(i1 %rc, i64 %rs1, i64 %rs2) {
+  ; RV64-LABEL: name: and4
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x12
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
+  ; RV64-NEXT:   [[XORI:%[0-9]+]]:gpr = XORI [[COPY1]], -1
+  ; RV64-NEXT:   [[MASKCN:%[0-9]+]]:gpr = MASKCN killed [[XORI]], killed [[ANDI]]
+  ; RV64-NEXT:   [[ANDN:%[0-9]+]]:gpr = ANDN [[COPY]], killed [[MASKCN]]
+  ; RV64-NEXT:   $x10 = COPY [[ANDN]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %and = and i64 %rs1, %rs2
+  %sel = select i1 %rc, i64 %rs2, i64 %and
+  ret i64 %sel
+}
+
+define i64 @basic(i1 %rc, i64 %rs1, i64 %rs2) {
+  ; RV64-LABEL: name: basic
+  ; RV64: bb.0 (%ir-block.0):
+  ; RV64-NEXT:   liveins: $x10, $x11, $x12
+  ; RV64-NEXT: {{  $}}
+  ; RV64-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x12
+  ; RV64-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x11
+  ; RV64-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x10
+  ; RV64-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY2]], 1
+  ; RV64-NEXT:   [[MASKCN:%[0-9]+]]:gpr = MASKCN [[COPY]], [[ANDI]]
+  ; RV64-NEXT:   [[MASKC:%[0-9]+]]:gpr = MASKC [[COPY1]], [[ANDI]]
+  ; RV64-NEXT:   [[OR:%[0-9]+]]:gpr = OR killed [[MASKC]], killed [[MASKCN]]
+  ; RV64-NEXT:   $x10 = COPY [[OR]]
+  ; RV64-NEXT:   PseudoRET implicit $x10
+  %sel = select i1 %rc, i64 %rs1, i64 %rs2
+  ret i64 %sel
+}

llvm/test/MC/RISCV/rv64xventanacondops-invalid.s

+# RUN: not llvm-mc -triple riscv64 -mattr=+xventanacondops < %s 2>&1 | FileCheck %s
+
+# Too few operands
+vt.maskc t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+# Too few operands
+vt.maskcn t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv64xventanacondops-valid.s

+# With Xventanacondops base extension:
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xventanacondops -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xventanacondops < %s \
+# RUN:     | llvm-objdump --mattr=+xventanacondops -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: vt.maskc t0, t1, t2
+# CHECK-ASM: encoding: [0xfb,0x62,0x73,0x00]
+vt.maskc t0, t1, t2
+# CHECK-ASM-AND-OBJ: vt.maskcn t0, t1, t2
+# CHECK-ASM: encoding: [0xfb,0x72,0x73,0x00]
+vt.maskcn t0, t1, t2