[RISCV] Add codegen support for RISCV XVentanaCondOps Extension

In D139394#4004119, @craig.topper wrote:

In D139394#4004118, @kconsul wrote:

In D139394#4004113, @craig.topper wrote:

I think we can commit this and work on improvements in separate patches.

Do I do a "git push" for this or will one of you do this for me ?
Sorry but I am new to LLVM reviews.llvm.org procedures for committing a change.

If you don't have commit access. I can push it. Should I use "Kautuk Consul <kconsul@ventanamicro.com>" for the commit author?

In D139394#4004113, @craig.topper wrote:

I think we can commit this and work on improvements in separate patches.

In D139394#3997124, @craig.topper wrote:

"Ops" in "XVentanaCondops" is capitalized in the specification and the code, but not in your patch title or patch description

In D139394#3995937, @jrtc27 wrote:

Subject and first line of the description should be clear it's about code generation. As it stands it still sounds like you're adding MC support.

[RISCV] Add support for RISCV XVentanaCondops Extension patterns

This patch adds support for part of XVentanaCondops extension.
This extension is designed to reduce the number of branches in
the generated RISCV assembly by replacing branches with conditional
move instructions as defined by XVentanaCondops specification.

[RISCV] Add support for RISCV XVentanaCondops Extension

[RISCV] Add support for RISCV XVentanaCondops Extension

[RISCV] Add support for RISCV XVentanaCondops Extension