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Differential D136150

[AArch64]SME2 Single and Multi vector Shift and Multiply instructions
ClosedPublic

Authored by CarolineConcatto on Oct 18 2022, 2:57 AM.

Details

Reviewers
sdesmalen
kmclaughlin
david-arm
paulwalker-arm
aemerson
Commits
rGd917276cd8e8: [AArch64]SME2 Single and Multi vector Shift and Multiply instructions
Summary

This patch adds the assembly/disassembly for the following instructions:

SQRSHR (four registers): Multi-vector signed saturating rounding shift right narrow by immediate.
       (two registers): Multi-vector signed saturating rounding shift right narrow by immediate.
SQRSHRN: Multi-vector signed saturating rounding shift right narrow by immediate and interleave.
SQRSHRU (four registers): Multi-vector signed saturating rounding shift right unsigned narrow by immediate.
        (two registers): Multi-vector signed saturating rounding shift right unsigned narrow by immediate.
SQRSHRUN: Multi-vector signed saturating rounding shift right unsigned narrow by immediate and interleave.
UQRSHR (four registers): Multi-vector unsigned saturating rounding shift right narrow by immediate
       (two registers): Multi-vector unsigned saturating rounding shift right narrow by immediate.
UQRSHRN: Multi-vector unsigned saturating rounding shift right narrow by immediate and interleave.

The reference can be found here:

https://developer.arm.com/documentation/ddi0602/2022-09

Diff Detail

Event Timeline

CarolineConcatto created this revision.Oct 18 2022, 2:57 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 18 2022, 2:57 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
CarolineConcatto requested review of this revision.Oct 18 2022, 2:57 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 18 2022, 2:57 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B192692: Diff 468466.Oct 18 2022, 2:57 AM
CarolineConcatto updated this revision to Diff 468467.Oct 18 2022, 3:05 AM

-Undo changes unwanted changes in sqdmulh-diagnostics.s

Harbormaster completed remote builds in B192693: Diff 468467.Oct 18 2022, 3:07 AM
CarolineConcatto added a child revision: D136155: [AArch64]SME2 Multi vector Frint instructions.Oct 20 2022, 2:52 AM
CarolineConcatto added a parent revision: D136142: [AArch64]SME2 MOV Instructions.
CarolineConcatto added a comment.Oct 20 2022, 10:23 AM

This patch needs to be rebase, this instructions
defm SQDMULH_2Z2Z : sme2_sqdmulh_vector_vg2_multi<"sqdmulh">;
defm SQDMULH_4Z4Z : sme2_sqdmulh_vector_vg4_multi<"sqdmulh">;
Should not be here.

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
251

This needs to be removed.
It is already in:
https://reviews.llvm.org/D135575

Matt added a subscriber: Matt.Oct 21 2022, 12:39 PM
CarolineConcatto updated this revision to Diff 470535.Oct 25 2022, 9:47 AM
CarolineConcatto edited the summary of this revision. (Show Details)
  • Remove redundant instructions
CarolineConcatto added a reviewer: david-arm.Oct 25 2022, 9:47 AM
Harbormaster completed remote builds in B194210: Diff 470535.Oct 25 2022, 9:47 AM
CarolineConcatto removed a reviewer: david-arm.Oct 25 2022, 9:48 AM
CarolineConcatto added reviewers: sdesmalen, kmclaughlin, david-arm, paulwalker-arm, aemerson.Oct 26 2022, 4:49 PM
paulwalker-arm added inline comments.Oct 30 2022, 5:08 AM
llvm/lib/Target/AArch64/SMEInstrFormats.td
3574

Can you create a multiclass for this that means the instructions get an element type suffix? Either that or just add the suffix to the instruction name, but I think we'll need a multiclass anyway for when we wire in code generation support.

3598–3600

Please see sve_int_bin_pred_shift_imm_left for how we usually handle variable length shift imm fields. Following that idiom sme2_sat_shift_vector_vg4 will match the encoding group (i.e. include entries for tsize and imm5) with the multiclass passing in the fixed parts and the fills in the rest using the imm of the required bit length for its datatype.

CarolineConcatto updated this revision to Diff 472380.Nov 1 2022, 12:57 PM
  • Address review comments
CarolineConcatto marked 2 inline comments as done.Nov 1 2022, 12:57 PM
Harbormaster completed remote builds in B195533: Diff 472380.Nov 1 2022, 12:58 PM
paulwalker-arm accepted this revision.Nov 1 2022, 5:50 PM

A couple of small requests but otherwise looks good.

llvm/lib/Target/AArch64/SMEInstrFormats.td
3591

This should be _H? because we typically reference the result element type, like you've done for the vg4 variants.

3604–3605

I'm not a fan of leaving holes in Inst like this. However, in this instance the hole is probably a bit big to hide within an opcode parameter so perhaps just add a comment like

// Inst{20-16} = imm5;
3613

Can this be kept as op and the split done within sme2_sat_shift_vector_vg4?

This revision is now accepted and ready to land.Nov 1 2022, 5:50 PM
This revision was landed with ongoing or failed builds.Nov 8 2022, 4:33 AM
Closed by commit rGd917276cd8e8: [AArch64]SME2 Single and Multi vector Shift and Multiply instructions (authored by CarolineConcatto). · Explain Why
This revision was automatically updated to reflect the committed changes.
CarolineConcatto added a commit: rGd917276cd8e8: [AArch64]SME2 Single and Multi vector Shift and Multiply instructions.
CarolineConcatto marked 3 inline comments as done.Nov 8 2022, 4:41 AM

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
12 lines
51 lines
test/
MC/
AArch64/
SME2/
55 lines
88 lines
30 lines
63 lines
35 lines
87 lines
30 lines
63 lines
55 lines
88 lines
30 lines
63 lines

Diff 470535

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

Show First 20 Lines • Show All 242 Lines • ▼ Show 20 Linesdef : Pat<(i64 (AArch64ObscureCopy (i64 GPR64:$idx))),
(OBSCURE_COPY GPR64:$idx)>; (OBSCURE_COPY GPR64:$idx)>;
} // End let Predicates = [HasSME] } // End let Predicates = [HasSME]
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SME2 Instructions // SME2 Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasSME2] in { let Predicates = [HasSME2] in {
defm ADD_VG2_M2ZZ_S : sme2_dot_mla_add_sub_array_vg24_single<"add", 0b0011010, MatrixOp32, ZZ_s, ZPR4b32>; defm ADD_VG2_M2ZZ_S : sme2_dot_mla_add_sub_array_vg24_single<"add", 0b0011010, MatrixOp32, ZZ_s, ZPR4b32>;
defm ADD_VG4_M4ZZ_S : sme2_dot_mla_add_sub_array_vg24_single<"add", 0b0111010, MatrixOp32, ZZZZ_s, ZPR4b32>; defm ADD_VG4_M4ZZ_S : sme2_dot_mla_add_sub_array_vg24_single<"add", 0b0111010, MatrixOp32, ZZZZ_s, ZPR4b32>;
CarolineConcattoAuthorUnsubmitted
Done
ReplyInline Actions

This needs to be removed.
It is already in:
https://reviews.llvm.org/D135575

CarolineConcatto: This needs to be removed. It is already in: https://reviews.llvm.org/D135575
defm ADD_VG2_M2Z2Z_S : sme2_dot_mla_add_sub_array_vg2_multi<"add", 0b011010, MatrixOp32, ZZ_s_mul_r>; defm ADD_VG2_M2Z2Z_S : sme2_dot_mla_add_sub_array_vg2_multi<"add", 0b011010, MatrixOp32, ZZ_s_mul_r>;
defm ADD_VG4_M4Z4Z_S : sme2_dot_mla_add_sub_array_vg4_multi<"add", 0b011010, MatrixOp32, ZZZZ_s_mul_r>; defm ADD_VG4_M4Z4Z_S : sme2_dot_mla_add_sub_array_vg4_multi<"add", 0b011010, MatrixOp32, ZZZZ_s_mul_r>;
defm ADD_VG2_2ZZ : sme2_int_sve_destructive_vector_vg2_single<"add", 0b0110000>; defm ADD_VG2_2ZZ : sme2_int_sve_destructive_vector_vg2_single<"add", 0b0110000>;
defm ADD_VG4_4ZZ : sme2_int_sve_destructive_vector_vg4_single<"add", 0b0110000>; defm ADD_VG4_4ZZ : sme2_int_sve_destructive_vector_vg4_single<"add", 0b0110000>;
defm SUB_VG2_M2ZZ_S : sme2_dot_mla_add_sub_array_vg24_single<"sub", 0b0011011, MatrixOp32, ZZ_s, ZPR4b32>; defm SUB_VG2_M2ZZ_S : sme2_dot_mla_add_sub_array_vg24_single<"sub", 0b0011011, MatrixOp32, ZZ_s, ZPR4b32>;
defm SUB_VG4_M4ZZ_S : sme2_dot_mla_add_sub_array_vg24_single<"sub", 0b0111011, MatrixOp32, ZZZZ_s, ZPR4b32>; defm SUB_VG4_M4ZZ_S : sme2_dot_mla_add_sub_array_vg24_single<"sub", 0b0111011, MatrixOp32, ZZZZ_s, ZPR4b32>;
▲ Show 20 Lines • Show All 343 Lines • ▼ Show 20 Lines
defm EXTRACT_2ZTI : sme2_mova_tile_to_vec_vg2_multi<"mov">; defm EXTRACT_2ZTI : sme2_mova_tile_to_vec_vg2_multi<"mov">;
defm EXTRACT_4ZTI : sme2_mova_tile_to_vec_vg4_multi<"mov">; defm EXTRACT_4ZTI : sme2_mova_tile_to_vec_vg4_multi<"mov">;
defm INSERT_VG2_2ZMI : sme2_mova_vec_to_array_vg2_multi<"mova">; defm INSERT_VG2_2ZMI : sme2_mova_vec_to_array_vg2_multi<"mova">;
defm INSERT_VG4_4ZMI : sme2_mova_vec_to_array_vg4_multi<"mova">; defm INSERT_VG4_4ZMI : sme2_mova_vec_to_array_vg4_multi<"mova">;
defm EXTRACT_VG2_2ZMI : sme2_mova_array_to_vec_vg2_multi<"mova">; defm EXTRACT_VG2_2ZMI : sme2_mova_array_to_vec_vg2_multi<"mova">;
defm EXTRACT_VG4_4ZMI : sme2_mova_array_to_vec_vg4_multi<"mova">; defm EXTRACT_VG4_4ZMI : sme2_mova_array_to_vec_vg4_multi<"mova">;
def SQRSHR_VG2_Z2ZI : sme2_sat_shift_vector_vg2<"sqrshr", 0b0, 0b0>;
defm SQRSHR_VG4_Z4ZI : sme2_sat_shift_vector_vg4<"sqrshr", 0b000>;
def UQRSHR_VG2_Z2ZI : sme2_sat_shift_vector_vg2<"uqrshr", 0b0, 0b1>;
defm UQRSHR_VG4_Z4ZI : sme2_sat_shift_vector_vg4<"uqrshr", 0b001>;
def SQRSHRU_VG2_Z2ZI : sme2_sat_shift_vector_vg2<"sqrshru", 0b1, 0b0>;
defm SQRSHRU_VG4_Z4ZI : sme2_sat_shift_vector_vg4<"sqrshru", 0b010>;
defm SQRSHRN_VG4_Z4ZI : sme2_sat_shift_vector_vg4<"sqrshrn", 0b100>;
defm UQRSHRN_VG4_Z4ZI : sme2_sat_shift_vector_vg4<"uqrshrn", 0b101>;
defm SQRSHRUN_VG4_Z4ZI : sme2_sat_shift_vector_vg4<"sqrshrun", 0b110>;
} }
let Predicates = [HasSME2, HasSMEI16I64] in { let Predicates = [HasSME2, HasSMEI16I64] in {
defm ADD_VG2_M2ZZ_D : sme2_dot_mla_add_sub_array_vg24_single<"add", 0b1011010, MatrixOp64, ZZ_d, ZPR4b64>; defm ADD_VG2_M2ZZ_D : sme2_dot_mla_add_sub_array_vg24_single<"add", 0b1011010, MatrixOp64, ZZ_d, ZPR4b64>;
defm ADD_VG4_M4ZZ_D : sme2_dot_mla_add_sub_array_vg24_single<"add", 0b1111010, MatrixOp64, ZZZZ_d, ZPR4b64>; defm ADD_VG4_M4ZZ_D : sme2_dot_mla_add_sub_array_vg24_single<"add", 0b1111010, MatrixOp64, ZZZZ_d, ZPR4b64>;
defm ADD_VG2_M2Z2Z_D : sme2_dot_mla_add_sub_array_vg2_multi<"add", 0b111010, MatrixOp64, ZZ_d_mul_r>; defm ADD_VG2_M2Z2Z_D : sme2_dot_mla_add_sub_array_vg2_multi<"add", 0b111010, MatrixOp64, ZZ_d_mul_r>;
defm ADD_VG4_M4Z4Z_D : sme2_dot_mla_add_sub_array_vg4_multi<"add", 0b111010, MatrixOp64, ZZZZ_d_mul_r>; defm ADD_VG4_M4Z4Z_D : sme2_dot_mla_add_sub_array_vg4_multi<"add", 0b111010, MatrixOp64, ZZZZ_d_mul_r>;
▲ Show 20 Lines • Show All 87 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/SMEInstrFormats.td

Show First 20 Lines • Show All 3,562 Lines • ▼ Show 20 Lines defm : sme2_mova_tile_or_array_to_vec_aliases<0, !cast<Instruction>(NAME),
ZZZZ_s_mul_r, MatrixOp32, ZZZZ_s_mul_r, MatrixOp32,
MatrixIndexGPR32Op8_11, MatrixIndexGPR32Op8_11,
sme_elm_idx0_7, "mov", "vgx4">; sme_elm_idx0_7, "mov", "vgx4">;
defm : sme2_mova_tile_or_array_to_vec_aliases<1, !cast<Instruction>(NAME), defm : sme2_mova_tile_or_array_to_vec_aliases<1, !cast<Instruction>(NAME),
ZZZZ_d_mul_r, MatrixOp64, ZZZZ_d_mul_r, MatrixOp64,
MatrixIndexGPR32Op8_11, MatrixIndexGPR32Op8_11,
sme_elm_idx0_7, "mov", "vgx4">; sme_elm_idx0_7, "mov", "vgx4">;
} }
//===----------------------------------------------------------------------===//
// SME2 multi-vec saturating shift right narrow
class sme2_sat_shift_vector_vg2<string mnemonic, bit op, bit u>
paulwalker-armUnsubmitted
Done
ReplyInline Actions

Can you create a multiclass for this that means the instructions get an element type suffix? Either that or just add the suffix to the instruction name, but I think we'll need a multiclass anyway for when we wire in code generation support.

paulwalker-arm: Can you create a multiclass for this that means the instructions get an element type suffix?
: I<(outs ZPR16:$Zd), (ins ZZ_s_mul_r:$Zn, vecshiftR16:$imm4),
mnemonic, "\t$Zd, $Zn, $imm4",
"", []>, Sched<[]> {
bits<4> imm4;
bits<4> Zn;
bits<5> Zd;
let Inst{31-21} = 0b11000001111;
let Inst{20} = op;
let Inst{19-16} = imm4;
let Inst{15-10} = 0b110101;
let Inst{9-6} = Zn;
let Inst{5} = u;
let Inst{4-0} = Zd;
}
class sme2_sat_shift_vector_vg4<bit n, bits<2> op,
ZPRRegOp zpr_ty, RegisterOperand vector_ty,
paulwalker-armUnsubmitted
Done
ReplyInline Actions

This should be _H? because we typically reference the result element type, like you've done for the vg4 variants.

paulwalker-arm: This should be `_H`? because we typically reference the result element type, like you've done…
Operand imm_ty, string mnemonic>
: I<(outs zpr_ty:$Zd), (ins vector_ty:$Zn, imm_ty:$imm),
mnemonic, "\t$Zd, $Zn, $imm",
"", []>, Sched<[]> {
bits<3> Zn;
bits<5> Zd;
let Inst{31-24} = 0b11000001;
let Inst{21} = 0b1;
let Inst{15-11} = 0b11011;
paulwalker-armUnsubmitted
Done
ReplyInline Actions

Please see sve_int_bin_pred_shift_imm_left for how we usually handle variable length shift imm fields. Following that idiom sme2_sat_shift_vector_vg4 will match the encoding group (i.e. include entries for tsize and imm5) with the multiclass passing in the fixed parts and the fills in the rest using the imm of the required bit length for its datatype.

paulwalker-arm: Please see `sve_int_bin_pred_shift_imm_left` for how we usually handle variable length shift…
let Inst{10} = n;
let Inst{9-7} = Zn;
let Inst{6-5} = op;
let Inst{4-0} = Zd;
}
paulwalker-armUnsubmitted
Done
ReplyInline Actions

I'm not a fan of leaving holes in Inst like this. However, in this instance the hole is probably a bit big to hide within an opcode parameter so perhaps just add a comment like

// Inst{20-16} = imm5;
paulwalker-arm: I'm not a fan of leaving holes in `Inst` like this. However, in this instance the hole is…
multiclass sme2_sat_shift_vector_vg4<string mnemonic, bits<3> op> {
def _B : sme2_sat_shift_vector_vg4<op{2}, op{1-0}, ZPR8, ZZZZ_s_mul_r, vecshiftR32,
mnemonic>{
bits<5> imm;
let Inst{23-22} = 0b01;
let Inst{20-16} = imm;
}
paulwalker-armUnsubmitted
Done
ReplyInline Actions

Can this be kept as op and the split done within sme2_sat_shift_vector_vg4?

paulwalker-arm: Can this be kept as `op` and the split done within `sme2_sat_shift_vector_vg4`?
def _H : sme2_sat_shift_vector_vg4<op{2}, op{1-0}, ZPR16, ZZZZ_d_mul_r,
vecshiftR64, mnemonic> {
bits<6> imm;
let Inst{23} = 0b1;
let Inst{22} = imm{5};
let Inst{20-16} = imm{4-0};
}
}

llvm/test/MC/AArch64/SME2/sqrshr-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
sqrshr z0.b, {z0.s-z4.s}, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: sqrshr z0.b, {z0.s-z4.s}, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshr z0.h, {z10.s-z12.s}, #15
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqrshr z0.h, {z10.s-z12.s}, #15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshr z0.h, {z1.d-z4.d}, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: sqrshr z0.h, {z1.d-z4.d}, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshr z0.h, {z1.s-z2.s}, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: sqrshr z0.h, {z1.s-z2.s}, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid immediate
sqrshr z31.h, {z28.d-z31.d}, #65
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64].
// CHECK-NEXT: sqrshr z31.h, {z28.d-z31.d}, #65
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshr z31.h, {z28.s-z29.s}, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16].
// CHECK-NEXT: sqrshr z31.h, {z28.s-z29.s}, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshr z31.b, {z28.s-z31.s}, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32].
// CHECK-NEXT: sqrshr z31.b, {z28.s-z31.s}, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
sqrshr z23.s, {z12.s-z15.s}, #15
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshr z23.s, {z12.s-z15.s}, #15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshr z23.b, {z12.d-z15.d}, #15
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqrshr z23.b, {z12.d-z15.d}, #15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/sqrshr.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
sqrshr z0.h, {z0.s - z1.s}, #16 // 11000001-11100000-11010100-00000000
// CHECK-INST: sqrshr z0.h, { z0.s, z1.s }, #16
// CHECK-ENCODING: [0x00,0xd4,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0d400 <unknown>
sqrshr z21.h, {z10.s - z11.s}, #11 // 11000001-11100101-11010101-01010101
// CHECK-INST: sqrshr z21.h, { z10.s, z11.s }, #11
// CHECK-ENCODING: [0x55,0xd5,0xe5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e5d555 <unknown>
sqrshr z23.h, {z12.s - z13.s}, #8 // 11000001-11101000-11010101-10010111
// CHECK-INST: sqrshr z23.h, { z12.s, z13.s }, #8
// CHECK-ENCODING: [0x97,0xd5,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8d597 <unknown>
sqrshr z31.h, {z30.s - z31.s}, #1 // 11000001-11101111-11010111-11011111
// CHECK-INST: sqrshr z31.h, { z30.s, z31.s }, #1
// CHECK-ENCODING: [0xdf,0xd7,0xef,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1efd7df <unknown>
sqrshr z0.b, {z0.s - z3.s}, #32 // 11000001-01100000-11011000-00000000
// CHECK-INST: sqrshr z0.b, { z0.s - z3.s }, #32
// CHECK-ENCODING: [0x00,0xd8,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160d800 <unknown>
sqrshr z21.b, {z8.s - z11.s}, #11 // 11000001-01110101-11011001-00010101
// CHECK-INST: sqrshr z21.b, { z8.s - z11.s }, #11
// CHECK-ENCODING: [0x15,0xd9,0x75,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c175d915 <unknown>
sqrshr z23.b, {z12.s - z15.s}, #24 // 11000001-01101000-11011001-10010111
// CHECK-INST: sqrshr z23.b, { z12.s - z15.s }, #24
// CHECK-ENCODING: [0x97,0xd9,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168d997 <unknown>
sqrshr z31.b, {z28.s - z31.s}, #1 // 11000001-01111111-11011011-10011111
// CHECK-INST: sqrshr z31.b, { z28.s - z31.s }, #1
// CHECK-ENCODING: [0x9f,0xdb,0x7f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c17fdb9f <unknown>
sqrshr z0.h, {z0.d - z3.d}, #64 // 11000001-10100000-11011000-00000000
// CHECK-INST: sqrshr z0.h, { z0.d - z3.d }, #64
// CHECK-ENCODING: [0x00,0xd8,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0d800 <unknown>
sqrshr z21.h, {z8.d - z11.d}, #11 // 11000001-11110101-11011001-00010101
// CHECK-INST: sqrshr z21.h, { z8.d - z11.d }, #11
// CHECK-ENCODING: [0x15,0xd9,0xf5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f5d915 <unknown>
sqrshr z23.h, {z12.d - z15.d}, #24 // 11000001-11101000-11011001-10010111
// CHECK-INST: sqrshr z23.h, { z12.d - z15.d }, #24
// CHECK-ENCODING: [0x97,0xd9,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8d997 <unknown>
sqrshr z31.h, {z28.d - z31.d}, #1 // 11000001-11111111-11011011-10011111
// CHECK-INST: sqrshr z31.h, { z28.d - z31.d }, #1
// CHECK-ENCODING: [0x9f,0xdb,0xff,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1ffdb9f <unknown>

llvm/test/MC/AArch64/SME2/sqrshrn-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
sqrshrn z0.b, {z0.s-z4.s}, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: sqrshrn z0.b, {z0.s-z4.s}, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrn z0.h, {z1.d-z4.d}, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: sqrshrn z0.h, {z1.d-z4.d}, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid immediate
sqrshrn z31.h, {z28.d-z31.d}, #65
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64].
// CHECK-NEXT: sqrshrn z31.h, {z28.d-z31.d}, #65
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
sqrshrn z23.s, {z12.s-z15.s}, #24
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrn z23.s, {z12.s-z15.s}, #24
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/sqrshrn.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
sqrshrn z0.b, {z0.s - z3.s}, #32 // 11000001-01100000-11011100-00000000
// CHECK-INST: sqrshrn z0.b, { z0.s - z3.s }, #32
// CHECK-ENCODING: [0x00,0xdc,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160dc00 <unknown>
sqrshrn z21.b, {z8.s - z11.s}, #11 // 11000001-01110101-11011101-00010101
// CHECK-INST: sqrshrn z21.b, { z8.s - z11.s }, #11
// CHECK-ENCODING: [0x15,0xdd,0x75,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c175dd15 <unknown>
sqrshrn z23.b, {z12.s - z15.s}, #24 // 11000001-01101000-11011101-10010111
// CHECK-INST: sqrshrn z23.b, { z12.s - z15.s }, #24
// CHECK-ENCODING: [0x97,0xdd,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168dd97 <unknown>
sqrshrn z31.b, {z28.s - z31.s}, #1 // 11000001-01111111-11011111-10011111
// CHECK-INST: sqrshrn z31.b, { z28.s - z31.s }, #1
// CHECK-ENCODING: [0x9f,0xdf,0x7f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c17fdf9f <unknown>
sqrshrn z0.h, {z0.d - z3.d}, #64 // 11000001-10100000-11011100-00000000
// CHECK-INST: sqrshrn z0.h, { z0.d - z3.d }, #64
// CHECK-ENCODING: [0x00,0xdc,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0dc00 <unknown>
sqrshrn z21.h, {z8.d - z11.d}, #11 // 11000001-11110101-11011101-00010101
// CHECK-INST: sqrshrn z21.h, { z8.d - z11.d }, #11
// CHECK-ENCODING: [0x15,0xdd,0xf5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f5dd15 <unknown>
sqrshrn z23.h, {z12.d - z15.d}, #24 // 11000001-11101000-11011101-10010111
// CHECK-INST: sqrshrn z23.h, { z12.d - z15.d }, #24
// CHECK-ENCODING: [0x97,0xdd,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8dd97 <unknown>
sqrshrn z31.h, {z28.d - z31.d}, #1 // 11000001-11111111-11011111-10011111
// CHECK-INST: sqrshrn z31.h, { z28.d - z31.d }, #1
// CHECK-ENCODING: [0x9f,0xdf,0xff,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1ffdf9f <unknown>

llvm/test/MC/AArch64/SME2/sqrshru-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
sqrshru z0.b, {z0.s-z4.s}, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: sqrshru z0.b, {z0.s-z4.s}, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshru z0.h, {z1.d-z4.d}, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: sqrshru z0.h, {z1.d-z4.d}, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid immediate
sqrshru z31.h, {z28.d-z31.d}, #65
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64].
// CHECK-NEXT: sqrshru z31.h, {z28.d-z31.d}, #65
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshru z31.h, {z28.d-z31.d}, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64].
// CHECK-NEXT: sqrshru z31.h, {z28.d-z31.d}, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
sqrshru z23.s, {z12.s-z15.s}, #24
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshru z23.s, {z12.s-z15.s}, #24
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/sqrshru.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
sqrshru z0.h, {z0.s - z1.s}, #16 // 11000001-11110000-11010100-00000000
// CHECK-INST: sqrshru z0.h, { z0.s, z1.s }, #16
// CHECK-ENCODING: [0x00,0xd4,0xf0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f0d400 <unknown>
sqrshru z21.h, {z10.s - z11.s}, #11 // 11000001-11110101-11010101-01010101
// CHECK-INST: sqrshru z21.h, { z10.s, z11.s }, #11
// CHECK-ENCODING: [0x55,0xd5,0xf5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f5d555 <unknown>
sqrshru z23.h, {z12.s - z13.s}, #8 // 11000001-11111000-11010101-10010111
// CHECK-INST: sqrshru z23.h, { z12.s, z13.s }, #8
// CHECK-ENCODING: [0x97,0xd5,0xf8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f8d597 <unknown>
sqrshru z31.h, {z30.s - z31.s}, #1 // 11000001-11111111-11010111-11011111
// CHECK-INST: sqrshru z31.h, { z30.s, z31.s }, #1
// CHECK-ENCODING: [0xdf,0xd7,0xff,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1ffd7df <unknown>
sqrshru z0.b, {z0.s - z3.s}, #32 // 11000001-01100000-11011000-01000000
// CHECK-INST: sqrshru z0.b, { z0.s - z3.s }, #32
// CHECK-ENCODING: [0x40,0xd8,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160d840 <unknown>
sqrshru z21.b, {z8.s - z11.s}, #11 // 11000001-01110101-11011001-01010101
// CHECK-INST: sqrshru z21.b, { z8.s - z11.s }, #11
// CHECK-ENCODING: [0x55,0xd9,0x75,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c175d955 <unknown>
sqrshru z23.b, {z12.s - z15.s}, #24 // 11000001-01101000-11011001-11010111
// CHECK-INST: sqrshru z23.b, { z12.s - z15.s }, #24
// CHECK-ENCODING: [0xd7,0xd9,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168d9d7 <unknown>
sqrshru z31.b, {z28.s - z31.s}, #1 // 11000001-01111111-11011011-11011111
// CHECK-INST: sqrshru z31.b, { z28.s - z31.s }, #1
// CHECK-ENCODING: [0xdf,0xdb,0x7f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c17fdbdf <unknown>
sqrshru z0.h, {z0.d - z3.d}, #64 // 11000001-10100000-11011000-01000000
// CHECK-INST: sqrshru z0.h, { z0.d - z3.d }, #64
// CHECK-ENCODING: [0x40,0xd8,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0d840 <unknown>
sqrshru z21.h, {z8.d - z11.d}, #11 // 11000001-11110101-11011001-01010101
// CHECK-INST: sqrshru z21.h, { z8.d - z11.d }, #11
// CHECK-ENCODING: [0x55,0xd9,0xf5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f5d955 <unknown>
sqrshru z23.h, {z12.d - z15.d}, #24 // 11000001-11101000-11011001-11010111
// CHECK-INST: sqrshru z23.h, { z12.d - z15.d }, #24
// CHECK-ENCODING: [0xd7,0xd9,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8d9d7 <unknown>
sqrshru z31.h, {z28.d - z31.d}, #1 // 11000001-11111111-11011011-11011111
// CHECK-INST: sqrshru z31.h, { z28.d - z31.d }, #1
// CHECK-ENCODING: [0xdf,0xdb,0xff,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1ffdbdf <unknown>

llvm/test/MC/AArch64/SME2/sqrshrun-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
sqrshrun z0.b, {z0.s-z4.s}, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: sqrshrun z0.b, {z0.s-z4.s}, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqrshrun z0.h, {z1.d-z4.d}, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: sqrshrun z0.h, {z1.d-z4.d}, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid immediate
sqrshrun z31.h, {z28.d-z31.d}, #65
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64].
// CHECK-NEXT: sqrshrun z31.h, {z28.d-z31.d}, #65
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
sqrshrun z23.s, {z12.s-z15.s}, #24
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqrshrun z23.s, {z12.s-z15.s}, #24
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/sqrshrun.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
sqrshrun z0.b, {z0.s - z3.s}, #32 // 11000001-01100000-11011100-01000000
// CHECK-INST: sqrshrun z0.b, { z0.s - z3.s }, #32
// CHECK-ENCODING: [0x40,0xdc,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160dc40 <unknown>
sqrshrun z21.b, {z8.s - z11.s}, #11 // 11000001-01110101-11011101-01010101
// CHECK-INST: sqrshrun z21.b, { z8.s - z11.s }, #11
// CHECK-ENCODING: [0x55,0xdd,0x75,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c175dd55 <unknown>
sqrshrun z23.b, {z12.s - z15.s}, #24 // 11000001-01101000-11011101-11010111
// CHECK-INST: sqrshrun z23.b, { z12.s - z15.s }, #24
// CHECK-ENCODING: [0xd7,0xdd,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168ddd7 <unknown>
sqrshrun z31.b, {z28.s - z31.s}, #1 // 11000001-01111111-11011111-11011111
// CHECK-INST: sqrshrun z31.b, { z28.s - z31.s }, #1
// CHECK-ENCODING: [0xdf,0xdf,0x7f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c17fdfdf <unknown>
sqrshrun z0.h, {z0.d - z3.d}, #64 // 11000001-10100000-11011100-01000000
// CHECK-INST: sqrshrun z0.h, { z0.d - z3.d }, #64
// CHECK-ENCODING: [0x40,0xdc,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0dc40 <unknown>
sqrshrun z21.h, {z8.d - z11.d}, #11 // 11000001-11110101-11011101-01010101
// CHECK-INST: sqrshrun z21.h, { z8.d - z11.d }, #11
// CHECK-ENCODING: [0x55,0xdd,0xf5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f5dd55 <unknown>
sqrshrun z23.h, {z12.d - z15.d}, #24 // 11000001-11101000-11011101-11010111
// CHECK-INST: sqrshrun z23.h, { z12.d - z15.d }, #24
// CHECK-ENCODING: [0xd7,0xdd,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8ddd7 <unknown>
sqrshrun z31.h, {z28.d - z31.d}, #1 // 11000001-11111111-11011111-11011111
// CHECK-INST: sqrshrun z31.h, { z28.d - z31.d }, #1
// CHECK-ENCODING: [0xdf,0xdf,0xff,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1ffdfdf <unknown>

llvm/test/MC/AArch64/SME2/uqrshr-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
uqrshr z0.b, {z0.s-z4.s}, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: uqrshr z0.b, {z0.s-z4.s}, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshr z0.h, {z10.s-z12.s}, #15
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uqrshr z0.h, {z10.s-z12.s}, #15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshr z0.h, {z1.d-z4.d}, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: uqrshr z0.h, {z1.d-z4.d}, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshr z0.h, {z1.s-z2.s}, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: uqrshr z0.h, {z1.s-z2.s}, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid immediate
uqrshr z31.h, {z28.d-z31.d}, #65
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64].
// CHECK-NEXT: uqrshr z31.h, {z28.d-z31.d}, #65
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshr z31.h, {z28.s-z29.s}, #0
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16].
// CHECK-NEXT: uqrshr z31.h, {z28.s-z29.s}, #0
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshr z31.b, {z28.s-z31.s}, #33
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32].
// CHECK-NEXT: uqrshr z31.b, {z28.s-z31.s}, #33
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
uqrshr z23.s, {z12.s-z15.s}, #15
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqrshr z23.s, {z12.s-z15.s}, #15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshr z23.b, {z12.d-z15.d}, #15
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uqrshr z23.b, {z12.d-z15.d}, #15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/uqrshr.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
uqrshr z0.h, {z0.s - z1.s}, #16 // 11000001-11100000-11010100-00100000
// CHECK-INST: uqrshr z0.h, { z0.s, z1.s }, #16
// CHECK-ENCODING: [0x20,0xd4,0xe0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e0d420 <unknown>
uqrshr z21.h, {z10.s - z11.s}, #11 // 11000001-11100101-11010101-01110101
// CHECK-INST: uqrshr z21.h, { z10.s, z11.s }, #11
// CHECK-ENCODING: [0x75,0xd5,0xe5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e5d575 <unknown>
uqrshr z23.h, {z12.s - z13.s}, #8 // 11000001-11101000-11010101-10110111
// CHECK-INST: uqrshr z23.h, { z12.s, z13.s }, #8
// CHECK-ENCODING: [0xb7,0xd5,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8d5b7 <unknown>
uqrshr z31.h, {z30.s - z31.s}, #1 // 11000001-11101111-11010111-11111111
// CHECK-INST: uqrshr z31.h, { z30.s, z31.s }, #1
// CHECK-ENCODING: [0xff,0xd7,0xef,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1efd7ff <unknown>
uqrshr z0.b, {z0.s - z3.s}, #32 // 11000001-01100000-11011000-00100000
// CHECK-INST: uqrshr z0.b, { z0.s - z3.s }, #32
// CHECK-ENCODING: [0x20,0xd8,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160d820 <unknown>
uqrshr z21.b, {z8.s - z11.s}, #11 // 11000001-01110101-11011001-00110101
// CHECK-INST: uqrshr z21.b, { z8.s - z11.s }, #11
// CHECK-ENCODING: [0x35,0xd9,0x75,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c175d935 <unknown>
uqrshr z23.b, {z12.s - z15.s}, #24 // 11000001-01101000-11011001-10110111
// CHECK-INST: uqrshr z23.b, { z12.s - z15.s }, #24
// CHECK-ENCODING: [0xb7,0xd9,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168d9b7 <unknown>
uqrshr z31.b, {z28.s - z31.s}, #1 // 11000001-01111111-11011011-10111111
// CHECK-INST: uqrshr z31.b, { z28.s - z31.s }, #1
// CHECK-ENCODING: [0xbf,0xdb,0x7f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c17fdbbf <unknown>
uqrshr z0.h, {z0.d - z3.d}, #64 // 11000001-10100000-11011000-00100000
// CHECK-INST: uqrshr z0.h, { z0.d - z3.d }, #64
// CHECK-ENCODING: [0x20,0xd8,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0d820 <unknown>
uqrshr z21.h, {z8.d - z11.d}, #11 // 11000001-11110101-11011001-00110101
// CHECK-INST: uqrshr z21.h, { z8.d - z11.d }, #11
// CHECK-ENCODING: [0x35,0xd9,0xf5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f5d935 <unknown>
uqrshr z23.h, {z12.d - z15.d}, #24 // 11000001-11101000-11011001-10110111
// CHECK-INST: uqrshr z23.h, { z12.d - z15.d }, #24
// CHECK-ENCODING: [0xb7,0xd9,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8d9b7 <unknown>
uqrshr z31.h, {z28.d - z31.d}, #1 // 11000001-11111111-11011011-10111111
// CHECK-INST: uqrshr z31.h, { z28.d - z31.d }, #1
// CHECK-ENCODING: [0xbf,0xdb,0xff,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1ffdbbf <unknown>

llvm/test/MC/AArch64/SME2/uqrshrn-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
uqrshrn z0.b, {z0.s-z4.s}, #32
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: uqrshrn z0.b, {z0.s-z4.s}, #32
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uqrshrn z0.h, {z1.d-z4.d}, #1
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: uqrshrn z0.h, {z1.d-z4.d}, #1
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid immediate
uqrshrn z31.h, {z28.d-z31.d}, #65
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64].
// CHECK-NEXT: uqrshrn z31.h, {z28.d-z31.d}, #65
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
uqrshrn z23.s, {z12.s-z15.s}, #24
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uqrshrn z23.s, {z12.s-z15.s}, #24
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/uqrshrn.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
uqrshrn z0.b, {z0.s - z3.s}, #32 // 11000001-01100000-11011100-00100000
// CHECK-INST: uqrshrn z0.b, { z0.s - z3.s }, #32
// CHECK-ENCODING: [0x20,0xdc,0x60,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c160dc20 <unknown>
uqrshrn z21.b, {z8.s - z11.s}, #11 // 11000001-01110101-11011101-00110101
// CHECK-INST: uqrshrn z21.b, { z8.s - z11.s }, #11
// CHECK-ENCODING: [0x35,0xdd,0x75,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c175dd35 <unknown>
uqrshrn z23.b, {z12.s - z15.s}, #24 // 11000001-01101000-11011101-10110111
// CHECK-INST: uqrshrn z23.b, { z12.s - z15.s }, #24
// CHECK-ENCODING: [0xb7,0xdd,0x68,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c168ddb7 <unknown>
uqrshrn z31.b, {z28.s - z31.s}, #1 // 11000001-01111111-11011111-10111111
// CHECK-INST: uqrshrn z31.b, { z28.s - z31.s }, #1
// CHECK-ENCODING: [0xbf,0xdf,0x7f,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c17fdfbf <unknown>
uqrshrn z0.h, {z0.d - z3.d}, #64 // 11000001-10100000-11011100-00100000
// CHECK-INST: uqrshrn z0.h, { z0.d - z3.d }, #64
// CHECK-ENCODING: [0x20,0xdc,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1a0dc20 <unknown>
uqrshrn z21.h, {z8.d - z11.d}, #11 // 11000001-11110101-11011101-00110101
// CHECK-INST: uqrshrn z21.h, { z8.d - z11.d }, #11
// CHECK-ENCODING: [0x35,0xdd,0xf5,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1f5dd35 <unknown>
uqrshrn z23.h, {z12.d - z15.d}, #24 // 11000001-11101000-11011101-10110111
// CHECK-INST: uqrshrn z23.h, { z12.d - z15.d }, #24
// CHECK-ENCODING: [0xb7,0xdd,0xe8,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1e8ddb7 <unknown>
uqrshrn z31.h, {z28.d - z31.d}, #1 // 11000001-11111111-11011111-10111111
// CHECK-INST: uqrshrn z31.h, { z28.d - z31.d }, #1
// CHECK-ENCODING: [0xbf,0xdf,0xff,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c1ffdfbf <unknown>