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[AArch64] SME2 multi-vec unpack, ZIP, frint for two and four registers
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Authored by CarolineConcatto on Oct 17 2022, 9:15 AM.

Details

Summary

This patch adds the assembly/disassembly for the following instructions:

SUNPK: Unpack and sign-extend multi-vector elements.
UUNPK: Unpack and zero-extend multi-vector elements.
ZIP (four registers): Interleave elements from four vectors.
ZIP (two registers): Interleave elements from two vectors.
FRINTA: Multi-vector floating-point round to integral value, to nearest with ties away from zero.
FRINTM: Multi-vector floating-point round to integral value, toward minus Infinity.
FRINTN: Multi-vector floating-point round to integral value, to nearest with ties to even.
FRINTP: Multi-vector floating-point round to integral value, toward plus Infinity.

The reference can be found here:

https://developer.arm.com/documentation/ddi0602/2022-09

Diff Detail

Event Timeline

Herald added a project: Restricted Project. · View Herald TranscriptOct 17 2022, 9:15 AM
CarolineConcatto requested review of this revision.Oct 17 2022, 9:15 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 17 2022, 9:15 AM
Matt added a subscriber: Matt.Oct 21 2022, 12:39 PM

Reuse clamp class
Rebase

  • Reuse cvt class for zip
llvm/lib/Target/AArch64/AArch64RegisterInfo.td
1116

I'd expect this to be ZPR2Mul2?

1139

ZPR4Mul4?

llvm/lib/Target/AArch64/SMEInstrFormats.td
1820

Have you reached the point where this class can just represent SME2 Multi-vector - SVE Constructive Unary? Perhaps not all instructions within that encoding group fit but looking at this new definition of Inst, which I very much like by the way, suggests that is what this class effectively represents. So you just need to change a few opcodes to match the documentation.

llvm/lib/Target/AArch64/SMEInstrFormats.td
1820

Actually looking at the register layouts perhaps this is not quite so clear cut, but I do think it's worth investigating to see if there's an options for more reuse. If you decide the current class is still the best route then I do think streaming the opcode across three variables is not great.

  • Address review comments
llvm/lib/Target/AArch64/SMEInstrFormats.td
1820

I looked before trying to merge them, but the registers sizes change between the group of instructions.

I reduced from 4 to 3 set of bit. The problem is that for cvt we need 3 bits to select the instructions, and for zip it doesn't, the same 3 bits need to be set because they are also the size.

paulwalker-arm added inline comments.Oct 30 2022, 4:50 AM
llvm/lib/Target/AArch64/SMEInstrFormats.td
1820

Sure I get the register sizes are different so we cannot have a single register class but it looks like we could have a smaller number of base classes based on register sizes? For example a class which represents the "SME2 Multi-vector - SVE Constructive Unary" encoding group can support all instructions where both registers are 3 bit. So:

SME2 multi-vec FP to int convert four registers
SME2 multi-vec int to FP four registers
SME2 multi-vec quadwords ZIP four registers
SME2 multi-vec ZIP four registers
SME2 multi-vec FRINT four registers

Likewise and class similar to the above but where the registers are 4bit can be used for:

SME2 multi-vec FP to int convert two registers
SME2 multi-vec int to FP two registers
SME2 multi-vec FRINT two registers

So with these 2 base classes you cover half of the groups within this parent encoding group. It starts to be a case of diminishing returns after this but even then "SME2 multi-vec FP down convert two registers" and "SME2 multi-vec int down convert two registers" can be grouped together.

  • Refactor the classes for all the instructions under Multi-vector - SVE Constructive Unary

Hey Paul,
I also pushed FRINT instructions to be in this class

llvm/lib/Target/AArch64/SMEInstrFormats.td
1820

I could not do what you asked. So I refactored the entire class.
Now I have a main class sme2_sve_constructive_unary
and many other small classes derived from sme2_sve_constructive_unary.
The Zd and Zn size are different in every class that I had to create.

  • More refactoring in the classes
CarolineConcatto retitled this revision from [AArch64] SME2 multi-vec unpack and ZIP two and four registers to [AArch64] SME2 multi-vec unpack, ZIP, frint for two and four registers.
CarolineConcatto edited the summary of this revision. (Show Details)
  • Update commit message

Hi Paul,
After we had a chat I try again to merge more classes.
I believe that is what we want.

paulwalker-arm accepted this revision.Nov 3 2022, 6:17 PM
paulwalker-arm added inline comments.
llvm/lib/Target/AArch64/SMEInstrFormats.td
1776–1777

Inst{21-18} = 0b1000;

1785

This should be NAME because you're already suffixing the instructions with _StoS.

This revision is now accepted and ready to land.Nov 3 2022, 6:17 PM