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Differential D135593

[AArch64]]SME2 multi-vec to multi-vec FP/INT down convert 2/4 registers
ClosedPublic

Authored by CarolineConcatto on Oct 10 2022, 8:45 AM.

Details

Reviewers
sdesmalen
david-arm
paulwalker-arm
aemerson
kmclaughlin
Commits
rG440005b3c353: [AArch64]]SME2 multi-vec to multi-vec FP/INT down convert 2/4 registers
Summary

This patch implements:
FCVTZS: Multi-vector floating-point convert to signed integer, rounding toward zero.
FCVTZU: Multi-vector floating-point convert to unsigned integer, rounding toward zero.
SCVTF: Multi-vector signed integer convert to floating-point.
UCVTF: Multi-vector unsigned integer convert to floating-point.
for 2 and 4 registers

The reference can be found here:

https://developer.arm.com/documentation/ddi0602/2022-09

Depends on: D135563

Diff Detail

Event Timeline

CarolineConcatto created this revision.Oct 10 2022, 8:45 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 10 2022, 8:45 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
CarolineConcatto requested review of this revision.Oct 10 2022, 8:45 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 10 2022, 8:45 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
CarolineConcatto edited the summary of this revision. (Show Details)Oct 10 2022, 8:45 AM
Harbormaster completed remote builds in B191288: Diff 466516.Oct 10 2022, 8:45 AM
CarolineConcatto added a parent revision: D135563: [AArch64]SME2 Multi-single vector SVE Destructive 2 and 4 Registers.Oct 10 2022, 9:15 AM
Matt added a subscriber: Matt.Oct 10 2022, 10:53 PM
CarolineConcatto added reviewers: sdesmalen, david-arm, paulwalker-arm, aemerson, kmclaughlin.Oct 20 2022, 10:36 AM

It needs to be rebased to update the vector list print.
But I think it can be checked

sdesmalen added inline comments.Oct 21 2022, 4:04 AM
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
294–301

Can you rename the suffix for these from _S -> _StoS ?

CarolineConcatto added a parent revision: D135588: [AArch64]SME2 multi-vec FP/INT down convert 2/4 registers.Oct 21 2022, 5:04 AM
CarolineConcatto updated this revision to Diff 469612.Oct 21 2022, 7:56 AM

Address review comments
rebase

CarolineConcatto marked an inline comment as done.Oct 21 2022, 8:00 AM
sdesmalen accepted this revision.Oct 21 2022, 8:09 AM
This revision is now accepted and ready to land.Oct 21 2022, 8:09 AM
Harbormaster completed remote builds in B193524: Diff 469612.Oct 21 2022, 8:38 AM
CarolineConcatto added a child revision: D135599: [AArch64]SME2 Single and multiple vectors SVE Destructive two/four registers[part2].Oct 21 2022, 9:08 AM
paulwalker-arm added inline comments.Oct 21 2022, 10:51 AM
llvm/test/MC/AArch64/SME2/fcvtzs-diagnostics.s
10

Hi @CarolineConcatto , nothing to hold up this patch but out of interest do you know why this CHECK-NOT line exists? We repeat the same idiom for all SVE/SME negative tests but I don't know what's special about this specific pattern for us to care so much.

sdesmalen added inline comments.Oct 24 2022, 1:05 AM
llvm/test/MC/AArch64/SME2/fcvtzs-diagnostics.s
10

The CHECK-NOT line is historically there because in the past we'd ended up with duplicate printing of the asm due to a bug in the assembler (D39894)

paulwalker-arm added inline comments.Oct 24 2022, 3:09 AM
llvm/test/MC/AArch64/SME2/fcvtzs-diagnostics.s
10

I see. Thanks @sdesmalen.

This revision was landed with ongoing or failed builds.Oct 24 2022, 12:21 PM
Closed by commit rG440005b3c353: [AArch64]]SME2 multi-vec to multi-vec FP/INT down convert 2/4 registers (authored by CarolineConcatto). · Explain Why
This revision was automatically updated to reflect the committed changes.
CarolineConcatto added a commit: rG440005b3c353: [AArch64]]SME2 multi-vec to multi-vec FP/INT down convert 2/4 registers.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
9 lines
29 lines
test/
MC/
AArch64/
SME2/
23 lines
63 lines
23 lines
63 lines
27 lines
63 lines
27 lines
63 lines

Diff 466516

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

Show First 20 Lines • Show All 285 Lines • ▼ Show 20 Lines
def UQCVT_Z2Z_StoH : sme2_cvt_vg2_single<"uqcvt", 0b01, 0b11>; def UQCVT_Z2Z_StoH : sme2_cvt_vg2_single<"uqcvt", 0b01, 0b11>;
defm UQCVT_Z4Z : sme2_int_cvt_vg4_single<"uqcvt", 0b001>; defm UQCVT_Z4Z : sme2_int_cvt_vg4_single<"uqcvt", 0b001>;
def SQCVTU_Z2Z_StoH : sme2_cvt_vg2_single<"sqcvtu", 0b10, 0b11>; def SQCVTU_Z2Z_StoH : sme2_cvt_vg2_single<"sqcvtu", 0b10, 0b11>;
defm SQCVTU_Z4Z : sme2_int_cvt_vg4_single<"sqcvtu", 0b100>; defm SQCVTU_Z4Z : sme2_int_cvt_vg4_single<"sqcvtu", 0b100>;
defm SQCVTN_Z4Z : sme2_int_cvt_vg4_single<"sqcvtn", 0b010>; defm SQCVTN_Z4Z : sme2_int_cvt_vg4_single<"sqcvtn", 0b010>;
defm SQCVTUN_Z4Z : sme2_int_cvt_vg4_single<"sqcvtun", 0b110>; defm SQCVTUN_Z4Z : sme2_int_cvt_vg4_single<"sqcvtun", 0b110>;
defm UQCVTN_Z4Z : sme2_int_cvt_vg4_single<"uqcvtn", 0b011>; defm UQCVTN_Z4Z : sme2_int_cvt_vg4_single<"uqcvtn", 0b011>;
def FCVTZS_2Z2Z_S : sme2_fp_cvt_vg2_multi<"fcvtzs", 0b010>;
def FCVTZS_4Z4Z_S : sme2_fp_cvt_vg4_multi<"fcvtzs", 0b010>;
def FCVTZU_2Z2Z_S : sme2_fp_cvt_vg2_multi<"fcvtzu", 0b011>;
def FCVTZU_4Z4Z_S : sme2_fp_cvt_vg4_multi<"fcvtzu", 0b011>;
def SCVTF_2Z2Z_S : sme2_fp_cvt_vg2_multi<"scvtf", 0b100>;
def SCVTF_4Z4Z_S : sme2_fp_cvt_vg4_multi<"scvtf", 0b100>;
def UCVTF_2Z2Z_S : sme2_fp_cvt_vg2_multi<"ucvtf", 0b101>;
def UCVTF_4Z4Z_S : sme2_fp_cvt_vg4_multi<"ucvtf", 0b101>;
sdesmalenUnsubmitted
Done
ReplyInline Actions

Can you rename the suffix for these from _S -> _StoS ?

sdesmalen: Can you rename the suffix for these from `_S` -> `_StoS` ?
} }
let Predicates = [HasSME2, HasSMEI64] in { let Predicates = [HasSME2, HasSMEI64] in {
defm ADD_VG2_M2ZZ_D : sme2_mul_add_sub_array_vg2_single_D<"add", 0b10>; defm ADD_VG2_M2ZZ_D : sme2_mul_add_sub_array_vg2_single_D<"add", 0b10>;
defm ADD_VG4_M4ZZ_D : sme2_mul_add_sub_array_vg4_single_D<"add", 0b10>; defm ADD_VG4_M4ZZ_D : sme2_mul_add_sub_array_vg4_single_D<"add", 0b10>;
defm ADD_VG2_M2Z2Z_D : sme2_mul_add_sub_array_vg2_multi_D<"add", 0b10>; defm ADD_VG2_M2Z2Z_D : sme2_mul_add_sub_array_vg2_multi_D<"add", 0b10>;
Show All 19 Lines

llvm/lib/Target/AArch64/SMEInstrFormats.td

Show First 20 Lines • Show All 1,474 Lines • ▼ Show 20 Lines
} }
multiclass sme2_int_cvt_vg4_single<string mnemonic, bits<3> op> { multiclass sme2_int_cvt_vg4_single<string mnemonic, bits<3> op> {
def _StoB : sme2_cvt_vg4_single<0b0, op, ZPR8, ZZZZ_s_mul_r, mnemonic>; def _StoB : sme2_cvt_vg4_single<0b0, op, ZPR8, ZZZZ_s_mul_r, mnemonic>;
def _DtoH : sme2_cvt_vg4_single<0b1, op, ZPR16, ZZZZ_d_mul_r, mnemonic>; def _DtoH : sme2_cvt_vg4_single<0b1, op, ZPR16, ZZZZ_d_mul_r, mnemonic>;
} }
class sme2_fp_cvt_vg2_multi<string mnemonic, bits<3> op>
: I<(outs ZZ_s_mul_r:$Zd), (ins ZZ_s_mul_r:$Zn),
mnemonic, "\t$Zd, $Zn", "", []>, Sched<[]> {
bits<4> Zn;
bits<4> Zd;
let Inst{31-18} = 0b11000001001000;
let Inst{17-16} = op{2-1};
let Inst{15-10} = 0b111000;
let Inst{9-6} = Zn;
let Inst{5} = op{0};
let Inst{4-1} = Zd;
let Inst{0} = 0b0;
}
class sme2_fp_cvt_vg4_multi<string mnemonic, bits<3> op>
: I<(outs ZZZZ_s_mul_r:$Zd), (ins ZZZZ_s_mul_r:$Zn),
mnemonic, "\t$Zd, $Zn", "", []>, Sched<[]> {
bits<3> Zn;
bits<3> Zd;
let Inst{31-18} = 0b11000001001100;
let Inst{17-16} = op{2-1};
let Inst{15-10} = 0b111000;
let Inst{9-7} = Zn;
let Inst{6} = 0b0;
let Inst{5} = op{0};
let Inst{4-2} = Zd;
let Inst{1-0} = 0b00;
}

llvm/test/MC/AArch64/SME2/fcvtzs-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
fcvtzs {z0.s-z1.s}, {z0.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvtzs {z0.s-z1.s}, {z0.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
paulwalker-armUnsubmitted
Not Done
ReplyInline Actions

Hi @CarolineConcatto , nothing to hold up this patch but out of interest do you know why this CHECK-NOT line exists? We repeat the same idiom for all SVE/SME negative tests but I don't know what's special about this specific pattern for us to care so much.

paulwalker-arm: Hi @CarolineConcatto , nothing to hold up this patch but out of interest do you know why this…
sdesmalenUnsubmitted
Not Done
ReplyInline Actions

The CHECK-NOT line is historically there because in the past we'd ended up with duplicate printing of the asm due to a bug in the assembler (D39894)

sdesmalen: The CHECK-NOT line is historically there because in the past we'd ended up with duplicate…
paulwalker-armUnsubmitted
Not Done
ReplyInline Actions

I see. Thanks @sdesmalen.

paulwalker-arm: I see. Thanks @sdesmalen.
fcvtzs {z1.s-z2.s}, {z0.s-z1.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with correct element type
// CHECK-NEXT: fcvtzs {z1.s-z2.s}, {z0.s-z1.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
fcvtzs {z0.d-z1.d}, {z0.s-z1.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvtzs {z0.d-z1.d}, {z0.s-z1.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/fcvtzs.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
fcvtzs {z0.s-z1.s}, {z0.s-z1.s} // 11000001-00100001-11100000-00000000
// CHECK-INST: fcvtzs { z0.s-z1.s }, { z0.s-z1.s }
// CHECK-ENCODING: [0x00,0xe0,0x21,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c121e000 <unknown>
fcvtzs {z20.s-z21.s}, {z10.s-z11.s} // 11000001-00100001-11100001-01010100
// CHECK-INST: fcvtzs { z20.s-z21.s }, { z10.s-z11.s }
// CHECK-ENCODING: [0x54,0xe1,0x21,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c121e154 <unknown>
fcvtzs {z22.s-z23.s}, {z12.s-z13.s} // 11000001-00100001-11100001-10010110
// CHECK-INST: fcvtzs { z22.s-z23.s }, { z12.s-z13.s }
// CHECK-ENCODING: [0x96,0xe1,0x21,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c121e196 <unknown>
fcvtzs {z30.s-z31.s}, {z30.s-z31.s} // 11000001-00100001-11100011-11011110
// CHECK-INST: fcvtzs { z30.s-z31.s }, { z30.s-z31.s }
// CHECK-ENCODING: [0xde,0xe3,0x21,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c121e3de <unknown>
fcvtzs {z0.s-z3.s}, {z0.s-z3.s} // 11000001-00110001-11100000-00000000
// CHECK-INST: fcvtzs { z0.s-z3.s }, { z0.s-z3.s }
// CHECK-ENCODING: [0x00,0xe0,0x31,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c131e000 <unknown>
fcvtzs {z20.s-z23.s}, {z8.s-z11.s} // 11000001-00110001-11100001-00010100
// CHECK-INST: fcvtzs { z20.s-z23.s }, { z8.s-z11.s }
// CHECK-ENCODING: [0x14,0xe1,0x31,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c131e114 <unknown>
fcvtzs {z20.s-z23.s}, {z12.s-z15.s} // 11000001-00110001-11100001-10010100
// CHECK-INST: fcvtzs { z20.s-z23.s }, { z12.s-z15.s }
// CHECK-ENCODING: [0x94,0xe1,0x31,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c131e194 <unknown>
fcvtzs {z28.s-z31.s}, {z28.s-z31.s} // 11000001-00110001-11100011-10011100
// CHECK-INST: fcvtzs { z28.s-z31.s }, { z28.s-z31.s }
// CHECK-ENCODING: [0x9c,0xe3,0x31,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c131e39c <unknown>

llvm/test/MC/AArch64/SME2/fcvtzu-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
fcvtzu {z0.s-z1.s}, {z0.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvtzu {z0.s-z1.s}, {z0.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
fcvtzu {z1.s-z2.s}, {z0.s-z1.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with correct element type
// CHECK-NEXT: fcvtzu {z1.s-z2.s}, {z0.s-z1.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
fcvtzu {z0.d-z1.d}, {z0.s-z1.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvtzu {z0.d-z1.d}, {z0.s-z1.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/fcvtzu.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
fcvtzu {z0.s-z1.s}, {z0.s-z1.s} // 11000001-00100001-11100000-00100000
// CHECK-INST: fcvtzu { z0.s-z1.s }, { z0.s-z1.s }
// CHECK-ENCODING: [0x20,0xe0,0x21,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c121e020 <unknown>
fcvtzu {z20.s-z21.s}, {z10.s-z11.s} // 11000001-00100001-11100001-01110100
// CHECK-INST: fcvtzu { z20.s-z21.s }, { z10.s-z11.s }
// CHECK-ENCODING: [0x74,0xe1,0x21,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c121e174 <unknown>
fcvtzu {z22.s-z23.s}, {z12.s-z13.s} // 11000001-00100001-11100001-10110110
// CHECK-INST: fcvtzu { z22.s-z23.s }, { z12.s-z13.s }
// CHECK-ENCODING: [0xb6,0xe1,0x21,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c121e1b6 <unknown>
fcvtzu {z30.s-z31.s}, {z30.s-z31.s} // 11000001-00100001-11100011-11111110
// CHECK-INST: fcvtzu { z30.s-z31.s }, { z30.s-z31.s }
// CHECK-ENCODING: [0xfe,0xe3,0x21,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c121e3fe <unknown>
fcvtzu {z0.s-z3.s}, {z0.s-z3.s} // 11000001-00110001-11100000-00100000
// CHECK-INST: fcvtzu { z0.s-z3.s }, { z0.s-z3.s }
// CHECK-ENCODING: [0x20,0xe0,0x31,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c131e020 <unknown>
fcvtzu {z20.s-z23.s}, {z8.s-z11.s} // 11000001-00110001-11100001-00110100
// CHECK-INST: fcvtzu { z20.s-z23.s }, { z8.s-z11.s }
// CHECK-ENCODING: [0x34,0xe1,0x31,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c131e134 <unknown>
fcvtzu {z20.s-z23.s}, {z12.s-z15.s} // 11000001-00110001-11100001-10110100
// CHECK-INST: fcvtzu { z20.s-z23.s }, { z12.s-z15.s }
// CHECK-ENCODING: [0xb4,0xe1,0x31,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c131e1b4 <unknown>
fcvtzu {z28.s-z31.s}, {z28.s-z31.s} // 11000001-00110001-11100011-10111100
// CHECK-INST: fcvtzu { z28.s-z31.s }, { z28.s-z31.s }
// CHECK-ENCODING: [0xbc,0xe3,0x31,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c131e3bc <unknown>

llvm/test/MC/AArch64/SME2/scvtf-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
scvtf {z0.s-z3.s}, {z0.s-z4.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: scvtf {z0.s-z3.s}, {z0.s-z4.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
scvtf {z1.s-z2.s}, {z0.s-z1.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with correct element type
// CHECK-NEXT: scvtf {z1.s-z2.s}, {z0.s-z1.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
scvtf {z0.s-z3.s}, {z1.s-z5.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: scvtf {z0.s-z3.s}, {z1.s-z5.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
scvtf {z0.s-z3.s}, {z1.h-z3.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: scvtf {z0.s-z3.s}, {z1.h-z3.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/scvtf.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
scvtf {z0.s-z1.s}, {z0.s-z1.s} // 11000001-00100010-11100000-00000000
// CHECK-INST: scvtf { z0.s-z1.s }, { z0.s-z1.s }
// CHECK-ENCODING: [0x00,0xe0,0x22,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c122e000 <unknown>
scvtf {z20.s-z21.s}, {z10.s-z11.s} // 11000001-00100010-11100001-01010100
// CHECK-INST: scvtf { z20.s-z21.s }, { z10.s-z11.s }
// CHECK-ENCODING: [0x54,0xe1,0x22,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c122e154 <unknown>
scvtf {z22.s-z23.s}, {z12.s-z13.s} // 11000001-00100010-11100001-10010110
// CHECK-INST: scvtf { z22.s-z23.s }, { z12.s-z13.s }
// CHECK-ENCODING: [0x96,0xe1,0x22,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c122e196 <unknown>
scvtf {z30.s-z31.s}, {z30.s-z31.s} // 11000001-00100010-11100011-11011110
// CHECK-INST: scvtf { z30.s-z31.s }, { z30.s-z31.s }
// CHECK-ENCODING: [0xde,0xe3,0x22,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c122e3de <unknown>
scvtf {z0.s-z3.s}, {z0.s-z3.s} // 11000001-00110010-11100000-00000000
// CHECK-INST: scvtf { z0.s-z3.s }, { z0.s-z3.s }
// CHECK-ENCODING: [0x00,0xe0,0x32,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c132e000 <unknown>
scvtf {z20.s-z23.s}, {z8.s-z11.s} // 11000001-00110010-11100001-00010100
// CHECK-INST: scvtf { z20.s-z23.s }, { z8.s-z11.s }
// CHECK-ENCODING: [0x14,0xe1,0x32,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c132e114 <unknown>
scvtf {z20.s-z23.s}, {z12.s-z15.s} // 11000001-00110010-11100001-10010100
// CHECK-INST: scvtf { z20.s-z23.s }, { z12.s-z15.s }
// CHECK-ENCODING: [0x94,0xe1,0x32,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c132e194 <unknown>
scvtf {z28.s-z31.s}, {z28.s-z31.s} // 11000001-00110010-11100011-10011100
// CHECK-INST: scvtf { z28.s-z31.s }, { z28.s-z31.s }
// CHECK-ENCODING: [0x9c,0xe3,0x32,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c132e39c <unknown>

llvm/test/MC/AArch64/SME2/ucvtf-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid vector list
ucvtf {z0.s-z3.s}, {z0.s-z4.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: ucvtf {z0.s-z3.s}, {z0.s-z4.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ucvtf {z1.s-z2.s}, {z0.s-z1.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with correct element type
// CHECK-NEXT: ucvtf {z1.s-z2.s}, {z0.s-z1.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ucvtf {z0.s-z3.s}, {z1.s-z5.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: ucvtf {z0.s-z3.s}, {z1.s-z5.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid Register Suffix
ucvtf {z0.s-z3.s}, {z1.h-z3.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ucvtf {z0.s-z3.s}, {z1.h-z3.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/ucvtf.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
ucvtf {z0.s-z1.s}, {z0.s-z1.s} // 11000001-00100010-11100000-00100000
// CHECK-INST: ucvtf { z0.s-z1.s }, { z0.s-z1.s }
// CHECK-ENCODING: [0x20,0xe0,0x22,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c122e020 <unknown>
ucvtf {z20.s-z21.s}, {z10.s-z11.s} // 11000001-00100010-11100001-01110100
// CHECK-INST: ucvtf { z20.s-z21.s }, { z10.s-z11.s }
// CHECK-ENCODING: [0x74,0xe1,0x22,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c122e174 <unknown>
ucvtf {z22.s-z23.s}, {z12.s-z13.s} // 11000001-00100010-11100001-10110110
// CHECK-INST: ucvtf { z22.s-z23.s }, { z12.s-z13.s }
// CHECK-ENCODING: [0xb6,0xe1,0x22,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c122e1b6 <unknown>
ucvtf {z30.s-z31.s}, {z30.s-z31.s} // 11000001-00100010-11100011-11111110
// CHECK-INST: ucvtf { z30.s-z31.s }, { z30.s-z31.s }
// CHECK-ENCODING: [0xfe,0xe3,0x22,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c122e3fe <unknown>
ucvtf {z0.s-z3.s}, {z0.s-z3.s} // 11000001-00110010-11100000-00100000
// CHECK-INST: ucvtf { z0.s-z3.s }, { z0.s-z3.s }
// CHECK-ENCODING: [0x20,0xe0,0x32,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c132e020 <unknown>
ucvtf {z20.s-z23.s}, {z8.s-z11.s} // 11000001-00110010-11100001-00110100
// CHECK-INST: ucvtf { z20.s-z23.s }, { z8.s-z11.s }
// CHECK-ENCODING: [0x34,0xe1,0x32,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c132e134 <unknown>
ucvtf {z20.s-z23.s}, {z12.s-z15.s} // 11000001-00110010-11100001-10110100
// CHECK-INST: ucvtf { z20.s-z23.s }, { z12.s-z15.s }
// CHECK-ENCODING: [0xb4,0xe1,0x32,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c132e1b4 <unknown>
ucvtf {z28.s-z31.s}, {z28.s-z31.s} // 11000001-00110010-11100011-10111100
// CHECK-INST: ucvtf { z28.s-z31.s }, { z28.s-z31.s }
// CHECK-ENCODING: [0xbc,0xe3,0x32,0xc1]
// CHECK-ERROR: instruction requires: sme2
// CHECK-UNKNOWN: c132e3bc <unknown>