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[VP][RISCV] Add vp.smax/smin/umax/umin intrinsics
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Authored by craig.topper on Oct 6 2022, 5:58 PM.

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craig.topper created this revision.Oct 6 2022, 5:58 PM
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craig.topper requested review of this revision.Oct 6 2022, 5:58 PM
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craig.topper retitled this revision from [RISCV] Add vp.smax/smin/umax/umin intrinsics to [VP][RISCV] Add vp.smax/smin/umax/umin intrinsics.Oct 6 2022, 5:59 PM

Fix a few issues in the LangRef

Fix some test case names

eopXD added a comment.Oct 6 2022, 6:49 PM

Looks good to me except a nit and a question to the FIXME. I would prefer another person to also review the patch and approve it though.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp
458

This should trigger clang-foramt.

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
10

Nit: %b to %vb

365

Just to make sure, do you mean that LMUL should be m4 here?

craig.topper added inline comments.Oct 6 2022, 7:06 PM
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll
365

I copied this from the vadd test. The VL is 128 so the upper half VL is zero as you can see in the vsetvli. But we don't strip any of the unneed code.

clang-format

frasercrmck added inline comments.Oct 7 2022, 3:40 AM
llvm/docs/LangRef.rst
19058

This should link to umin <int_umin>

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
175

I note that we call PromoteIntRes_UMINUMAX for regular UMIN/UMAX. Is there something there that we want to do for the VP versions too?

craig.topper added inline comments.Oct 7 2022, 8:51 AM
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
175

I think that uses sext for scalar i32 on RISC-V by calling isSExtCheaperThanZExt

Fix LangRef link.

reames accepted this revision.Oct 7 2022, 11:54 AM

LGTM

This revision is now accepted and ready to land.Oct 7 2022, 11:54 AM
This revision was landed with ongoing or failed builds.Oct 7 2022, 5:14 PM
This revision was automatically updated to reflect the committed changes.