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Differential D132211

[RISCV] Optimize x > 1 ? x : 1 -> x > 0 ? x : 1
ClosedPublic

Authored by liaolucy on Aug 19 2022, 1:10 AM.

Details

Reviewers
craig.topper
Commits
rG1fb87ace4d09: [RISCV] Optimize x > 1 ? x : 1 -> x > 0 ? x : 1
Summary

if x == 1,

x > 1 ? x : 1  return x, which is also 1.
x > 0 ? x : 1  return 1.

Reduce the number of load 1 instructions.

Diff Detail

Event Timeline

liaolucy created this revision.Aug 19 2022, 1:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 19 2022, 1:10 AM
Herald added subscribers: StephenFan, frasercrmck, luismarques and 21 others. · View Herald Transcript
liaolucy requested review of this revision.Aug 19 2022, 1:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 19 2022, 1:10 AM
Herald added subscribers: llvm-commits, • pcwang-thead, MaskRay. · View Herald Transcript
liaolucy retitled this revision from Optimize x > 1 ? x : 1 -> x > 0 ? x : 1 to [RISCV] Optimize x > 1 ? x : 1 -> x > 0 ? x : 1.Aug 19 2022, 1:10 AM
Herald added subscribers: sunshaoce, eopXD, VincentWu and 7 others. · View Herald TranscriptAug 19 2022, 1:10 AM
liaolucy updated this revision to Diff 453919.Aug 19 2022, 1:19 AM

update

liaolucy updated this revision to Diff 453932.Aug 19 2022, 2:09 AM

iFix error , add RHS == TrueV

Harbormaster completed remote builds in B182180: Diff 453932.Aug 19 2022, 3:09 AM
craig.topper accepted this revision.Aug 19 2022, 10:05 AM

LGTM

This revision is now accepted and ready to land.Aug 19 2022, 10:05 AM
craig.topper added inline comments.Aug 19 2022, 10:34 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
4086

Update this comment to x < 1 ? x : 1 -> 0 < x ? x : 1

4086

Oops. I mean 1 < x ? x : 1 -> 0 < x ? x : 1

craig.topper mentioned this in D132252: [RISCV] Optimize x <s -1 ? x : -1. Improve x >u 1 ? x : 1..Aug 19 2022, 10:40 AM
craig.topper added a child revision: D132252: [RISCV] Optimize x <s -1 ? x : -1. Improve x >u 1 ? x : 1..Aug 19 2022, 10:41 AM
liaolucy updated this revision to Diff 454301.Aug 21 2022, 5:25 AM

Update comment to 1 < x ? x : 1 -> 0 < x ? x : 1

This revision was landed with ongoing or failed builds.Aug 21 2022, 5:26 AM
Closed by commit rG1fb87ace4d09: [RISCV] Optimize x > 1 ? x : 1 -> x > 0 ? x : 1 (authored by liaolucy). · Explain Why
This revision was automatically updated to reflect the committed changes.
liaolucy added a commit: rG1fb87ace4d09: [RISCV] Optimize x > 1 ? x : 1 -> x > 0 ? x : 1.
Harbormaster completed remote builds in B182446: Diff 454301.Aug 21 2022, 6:00 AM
craig.topper mentioned this in rG1a042dd6ed21: [RISCV] Optimize x <s -1 ? x : -1. Improve x >u 1 ? x : 1..Aug 21 2022, 12:15 PM

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
6 lines
test/
CodeGen/
RISCV/
12 lines

Diff 454302

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,077 Lines • ▼ Show 20 Lines if (isa<ConstantSDNode>(TrueV) && isa<ConstantSDNode>(FalseV) &&
const APInt &FalseVal = cast<ConstantSDNode>(FalseV)->getAPIntValue(); const APInt &FalseVal = cast<ConstantSDNode>(FalseV)->getAPIntValue();
if (TrueVal - 1 == FalseVal) if (TrueVal - 1 == FalseVal)
return DAG.getNode(ISD::ADD, DL, VT, CondV, FalseV); return DAG.getNode(ISD::ADD, DL, VT, CondV, FalseV);
if (TrueVal + 1 == FalseVal) if (TrueVal + 1 == FalseVal)
return DAG.getNode(ISD::SUB, DL, VT, FalseV, CondV); return DAG.getNode(ISD::SUB, DL, VT, FalseV, CondV);
} }
translateSetCCForBranch(DL, LHS, RHS, CCVal, DAG); translateSetCCForBranch(DL, LHS, RHS, CCVal, DAG);
// 1 < x ? x : 1 -> 0 < x ? x : 1
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Update this comment to x < 1 ? x : 1 -> 0 < x ? x : 1

craig.topper: Update this comment to `x < 1 ? x : 1 -> 0 < x ? x : 1`
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Oops. I mean 1 < x ? x : 1 -> 0 < x ? x : 1

craig.topper: Oops. I mean `1 < x ? x : 1 -> 0 < x ? x : 1`
if (isOneConstant(LHS) && !isa<ConstantSDNode>(RHS) &&
(CCVal == ISD::SETLT || CCVal == ISD::SETULT) && RHS == TrueV &&
isOneConstant(FalseV)) {
LHS = DAG.getConstant(0, DL, VT);
}
SDValue TargetCC = DAG.getCondCode(CCVal); SDValue TargetCC = DAG.getCondCode(CCVal);
SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV}; SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
return DAG.getNode(RISCVISD::SELECT_CC, DL, VT, Ops); return DAG.getNode(RISCVISD::SELECT_CC, DL, VT, Ops);
} }
// Otherwise: // Otherwise:
// (select condv, truev, falsev) // (select condv, truev, falsev)
▲ Show 20 Lines • Show All 8,863 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/forced-atomics.ll

Show First 20 Lines • Show All 989 Lines • ▼ Show 20 Lines
; RV32-NO-ATOMIC-NEXT: li a3, 5 ; RV32-NO-ATOMIC-NEXT: li a3, 5
; RV32-NO-ATOMIC-NEXT: li a4, 5 ; RV32-NO-ATOMIC-NEXT: li a4, 5
; RV32-NO-ATOMIC-NEXT: mv a0, s0 ; RV32-NO-ATOMIC-NEXT: mv a0, s0
; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt ; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt
; RV32-NO-ATOMIC-NEXT: lw a1, 4(sp) ; RV32-NO-ATOMIC-NEXT: lw a1, 4(sp)
; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB23_4 ; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB23_4
; RV32-NO-ATOMIC-NEXT: .LBB23_2: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: .LBB23_2: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NO-ATOMIC-NEXT: li a0, 1
; RV32-NO-ATOMIC-NEXT: mv a2, a1 ; RV32-NO-ATOMIC-NEXT: mv a2, a1
; RV32-NO-ATOMIC-NEXT: blt a0, a1, .LBB23_1 ; RV32-NO-ATOMIC-NEXT: bgtz a1, .LBB23_1
; RV32-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB23_2 Depth=1 ; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB23_2 Depth=1
; RV32-NO-ATOMIC-NEXT: li a2, 1 ; RV32-NO-ATOMIC-NEXT: li a2, 1
; RV32-NO-ATOMIC-NEXT: j .LBB23_1 ; RV32-NO-ATOMIC-NEXT: j .LBB23_1
; RV32-NO-ATOMIC-NEXT: .LBB23_4: # %atomicrmw.end ; RV32-NO-ATOMIC-NEXT: .LBB23_4: # %atomicrmw.end
; RV32-NO-ATOMIC-NEXT: mv a0, a1 ; RV32-NO-ATOMIC-NEXT: mv a0, a1
; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NO-ATOMIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
▲ Show 20 Lines • Show All 169 Lines • ▼ Show 20 Lines
; RV32-NO-ATOMIC-NEXT: li a3, 5 ; RV32-NO-ATOMIC-NEXT: li a3, 5
; RV32-NO-ATOMIC-NEXT: li a4, 5 ; RV32-NO-ATOMIC-NEXT: li a4, 5
; RV32-NO-ATOMIC-NEXT: mv a0, s0 ; RV32-NO-ATOMIC-NEXT: mv a0, s0
; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt ; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4@plt
; RV32-NO-ATOMIC-NEXT: lw a1, 4(sp) ; RV32-NO-ATOMIC-NEXT: lw a1, 4(sp)
; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB25_4 ; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB25_4
; RV32-NO-ATOMIC-NEXT: .LBB25_2: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: .LBB25_2: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NO-ATOMIC-NEXT: li a0, 1
; RV32-NO-ATOMIC-NEXT: mv a2, a1 ; RV32-NO-ATOMIC-NEXT: mv a2, a1
; RV32-NO-ATOMIC-NEXT: bltu a0, a1, .LBB25_1 ; RV32-NO-ATOMIC-NEXT: bltu zero, a1, .LBB25_1
; RV32-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV32-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB25_2 Depth=1 ; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB25_2 Depth=1
; RV32-NO-ATOMIC-NEXT: li a2, 1 ; RV32-NO-ATOMIC-NEXT: li a2, 1
; RV32-NO-ATOMIC-NEXT: j .LBB25_1 ; RV32-NO-ATOMIC-NEXT: j .LBB25_1
; RV32-NO-ATOMIC-NEXT: .LBB25_4: # %atomicrmw.end ; RV32-NO-ATOMIC-NEXT: .LBB25_4: # %atomicrmw.end
; RV32-NO-ATOMIC-NEXT: mv a0, a1 ; RV32-NO-ATOMIC-NEXT: mv a0, a1
; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NO-ATOMIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32-NO-ATOMIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
▲ Show 20 Lines • Show All 1,361 Lines • ▼ Show 20 Lines
; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a3, 5
; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5
; RV64-NO-ATOMIC-NEXT: mv a0, s0 ; RV64-NO-ATOMIC-NEXT: mv a0, s0
; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt ; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt
; RV64-NO-ATOMIC-NEXT: ld a1, 8(sp) ; RV64-NO-ATOMIC-NEXT: ld a1, 8(sp)
; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB49_4 ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB49_4
; RV64-NO-ATOMIC-NEXT: .LBB49_2: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: .LBB49_2: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NO-ATOMIC-NEXT: li a0, 1
; RV64-NO-ATOMIC-NEXT: mv a2, a1 ; RV64-NO-ATOMIC-NEXT: mv a2, a1
; RV64-NO-ATOMIC-NEXT: blt a0, a1, .LBB49_1 ; RV64-NO-ATOMIC-NEXT: bgtz a1, .LBB49_1
; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB49_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB49_2 Depth=1
; RV64-NO-ATOMIC-NEXT: li a2, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 1
; RV64-NO-ATOMIC-NEXT: j .LBB49_1 ; RV64-NO-ATOMIC-NEXT: j .LBB49_1
; RV64-NO-ATOMIC-NEXT: .LBB49_4: # %atomicrmw.end ; RV64-NO-ATOMIC-NEXT: .LBB49_4: # %atomicrmw.end
; RV64-NO-ATOMIC-NEXT: mv a0, a1 ; RV64-NO-ATOMIC-NEXT: mv a0, a1
; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 174 Lines • ▼ Show 20 Lines
; RV64-NO-ATOMIC-NEXT: li a3, 5 ; RV64-NO-ATOMIC-NEXT: li a3, 5
; RV64-NO-ATOMIC-NEXT: li a4, 5 ; RV64-NO-ATOMIC-NEXT: li a4, 5
; RV64-NO-ATOMIC-NEXT: mv a0, s0 ; RV64-NO-ATOMIC-NEXT: mv a0, s0
; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt ; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8@plt
; RV64-NO-ATOMIC-NEXT: ld a1, 8(sp) ; RV64-NO-ATOMIC-NEXT: ld a1, 8(sp)
; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB51_4 ; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB51_4
; RV64-NO-ATOMIC-NEXT: .LBB51_2: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: .LBB51_2: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1 ; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NO-ATOMIC-NEXT: li a0, 1
; RV64-NO-ATOMIC-NEXT: mv a2, a1 ; RV64-NO-ATOMIC-NEXT: mv a2, a1
; RV64-NO-ATOMIC-NEXT: bltu a0, a1, .LBB51_1 ; RV64-NO-ATOMIC-NEXT: bltu zero, a1, .LBB51_1
; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start ; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV64-NO-ATOMIC-NEXT: li a2, 1 ; RV64-NO-ATOMIC-NEXT: li a2, 1
; RV64-NO-ATOMIC-NEXT: j .LBB51_1 ; RV64-NO-ATOMIC-NEXT: j .LBB51_1
; RV64-NO-ATOMIC-NEXT: .LBB51_4: # %atomicrmw.end ; RV64-NO-ATOMIC-NEXT: .LBB51_4: # %atomicrmw.end
; RV64-NO-ATOMIC-NEXT: mv a0, a1 ; RV64-NO-ATOMIC-NEXT: mv a0, a1
; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 873 Lines • Show Last 20 Lines