[RISCV] Optimize x <s -1 ? x : -1. Improve x >u 1 ? x : 1.

[craig.topper]

Summary

Similar to D132211, we can optimize x <s -1 ? x : -1 -> x <s 0 ? x : -1

Also improve the unsigned case from D132211 to use x != 0 which
will give a bnez instruction which might be compressible.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4089

I dropped the non-constant RHS check here because it doesn't matter for the correctness of the combine and an all constant setcc should have been DAG combined away.

4090

Remove the second call to isOneConstant by checking if LHS == FalseV since we already know LHS is 1. These two changes improve the similarity with the new combine introduced here.

[liaolucy]

LGTM, thanks.
Note, rebase first.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (isa<ConstantSDNode>(TrueV) && isa<ConstantSDNode>(FalseV) &&
       if (TrueVal - 1 == FalseVal)
         return DAG.getNode(ISD::ADD, DL, VT, CondV, FalseV);
       if (TrueVal + 1 == FalseVal)
         return DAG.getNode(ISD::SUB, DL, VT, FalseV, CondV);
     }
 
     translateSetCCForBranch(DL, LHS, RHS, CCVal, DAG);
     // 1 < x ? x : 1 -> 0 < x ? x : 1
-    if (isOneConstant(LHS) && !isa<ConstantSDNode>(RHS) &&
+    if (isOneConstant(LHS) &&
         (CCVal == ISD::SETLT || CCVal == ISD::SETULT) && RHS == TrueV &&
-        isOneConstant(FalseV)) {
+        LHS == FalseV) {
       LHS = DAG.getConstant(0, DL, VT);
+      // 0 <u x is the same as x != 0.
+      if (CCVal == ISD::SETULT) {
+        std::swap(LHS, RHS);
+        CCVal = ISD::SETNE;
+      }
+    }
+
+    // x <s -1 ? x : -1 -> x <s 0 ? x : -1
+    if (isAllOnesConstant(RHS) && CCVal == ISD::SETLT && LHS == TrueV &&
+        RHS == FalseV) {
+      RHS = DAG.getConstant(0, DL, VT);
     }
 
     SDValue TargetCC = DAG.getCondCode(CCVal);
     SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
     return DAG.getNode(RISCVISD::SELECT_CC, DL, VT, Ops);
   }
 
   // Otherwise:

llvm/test/CodeGen/RISCV/forced-atomics.ll

 ; RV32-NO-ATOMIC-NEXT:    li a4, 5
 ; RV32-NO-ATOMIC-NEXT:    mv a0, s0
 ; RV32-NO-ATOMIC-NEXT:    call __atomic_compare_exchange_4@plt
 ; RV32-NO-ATOMIC-NEXT:    lw a1, 4(sp)
 ; RV32-NO-ATOMIC-NEXT:    bnez a0, .LBB25_4
 ; RV32-NO-ATOMIC-NEXT:  .LBB25_2: # %atomicrmw.start
 ; RV32-NO-ATOMIC-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV32-NO-ATOMIC-NEXT:    mv a2, a1
-; RV32-NO-ATOMIC-NEXT:    bltu zero, a1, .LBB25_1
+; RV32-NO-ATOMIC-NEXT:    bnez a1, .LBB25_1
 ; RV32-NO-ATOMIC-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV32-NO-ATOMIC-NEXT:    # in Loop: Header=BB25_2 Depth=1
 ; RV32-NO-ATOMIC-NEXT:    li a2, 1
 ; RV32-NO-ATOMIC-NEXT:    j .LBB25_1
 ; RV32-NO-ATOMIC-NEXT:  .LBB25_4: # %atomicrmw.end
 ; RV32-NO-ATOMIC-NEXT:    mv a0, a1
 ; RV32-NO-ATOMIC-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-NO-ATOMIC-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload

 ; RV64-NO-ATOMIC-NEXT:    li a4, 5
 ; RV64-NO-ATOMIC-NEXT:    mv a0, s0
 ; RV64-NO-ATOMIC-NEXT:    call __atomic_compare_exchange_8@plt
 ; RV64-NO-ATOMIC-NEXT:    ld a1, 8(sp)
 ; RV64-NO-ATOMIC-NEXT:    bnez a0, .LBB51_4
 ; RV64-NO-ATOMIC-NEXT:  .LBB51_2: # %atomicrmw.start
 ; RV64-NO-ATOMIC-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64-NO-ATOMIC-NEXT:    mv a2, a1
-; RV64-NO-ATOMIC-NEXT:    bltu zero, a1, .LBB51_1
+; RV64-NO-ATOMIC-NEXT:    bnez a1, .LBB51_1
 ; RV64-NO-ATOMIC-NEXT:  # %bb.3: # %atomicrmw.start
 ; RV64-NO-ATOMIC-NEXT:    # in Loop: Header=BB51_2 Depth=1
 ; RV64-NO-ATOMIC-NEXT:    li a2, 1
 ; RV64-NO-ATOMIC-NEXT:    j .LBB51_1
 ; RV64-NO-ATOMIC-NEXT:  .LBB51_4: # %atomicrmw.end
 ; RV64-NO-ATOMIC-NEXT:    mv a0, a1
 ; RV64-NO-ATOMIC-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64-NO-ATOMIC-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload

llvm/test/CodeGen/RISCV/min-max.ll

 ; ZBB-NEXT:    li a1, 16
 ; ZBB-NEXT:    max a0, a0, a1
 ; ZBB-NEXT:    ret
   %b = and i32 %a, -8
   %c = call i32 @llvm.smax.i32(i32 %b, i32 16)
   %d = and i32 %c, -4
   ret i32 %d
 }
+
+define signext i32 @smin_i32_negone(i32 signext %a) {
+; NOZBB-LABEL: smin_i32_negone:
+; NOZBB:       # %bb.0:
+; NOZBB-NEXT:    bltz a0, .LBB26_2
+; NOZBB-NEXT:  # %bb.1:
+; NOZBB-NEXT:    li a0, -1
+; NOZBB-NEXT:  .LBB26_2:
+; NOZBB-NEXT:    ret
+;
+; ZBB-LABEL: smin_i32_negone:
+; ZBB:       # %bb.0:
+; ZBB-NEXT:    li a1, -1
+; ZBB-NEXT:    min a0, a0, a1
+; ZBB-NEXT:    ret
+  %c = call i32 @llvm.smin.i32(i32 %a, i32 -1)
+  ret i32 %c
+}
+
+define i64 @smin_i64_negone(i64 %a) {
+; RV32I-LABEL: smin_i64_negone:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    li a2, -1
+; RV32I-NEXT:    mv a3, a0
+; RV32I-NEXT:    bge a1, a2, .LBB27_4
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    bne a1, a2, .LBB27_5
+; RV32I-NEXT:  .LBB27_2:
+; RV32I-NEXT:    bgez a1, .LBB27_6
+; RV32I-NEXT:  .LBB27_3:
+; RV32I-NEXT:    ret
+; RV32I-NEXT:  .LBB27_4:
+; RV32I-NEXT:    li a3, -1
+; RV32I-NEXT:    beq a1, a2, .LBB27_2
+; RV32I-NEXT:  .LBB27_5:
+; RV32I-NEXT:    mv a0, a3
+; RV32I-NEXT:    bltz a1, .LBB27_3
+; RV32I-NEXT:  .LBB27_6:
+; RV32I-NEXT:    li a1, -1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: smin_i64_negone:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    bltz a0, .LBB27_2
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    li a0, -1
+; RV64I-NEXT:  .LBB27_2:
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: smin_i64_negone:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    li a2, -1
+; RV32ZBB-NEXT:    mv a3, a0
+; RV32ZBB-NEXT:    bge a1, a2, .LBB27_3
+; RV32ZBB-NEXT:  # %bb.1:
+; RV32ZBB-NEXT:    bne a1, a2, .LBB27_4
+; RV32ZBB-NEXT:  .LBB27_2:
+; RV32ZBB-NEXT:    min a1, a1, a2
+; RV32ZBB-NEXT:    ret
+; RV32ZBB-NEXT:  .LBB27_3:
+; RV32ZBB-NEXT:    li a3, -1
+; RV32ZBB-NEXT:    beq a1, a2, .LBB27_2
+; RV32ZBB-NEXT:  .LBB27_4:
+; RV32ZBB-NEXT:    mv a0, a3
+; RV32ZBB-NEXT:    min a1, a1, a2
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: smin_i64_negone:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    li a1, -1
+; RV64ZBB-NEXT:    min a0, a0, a1
+; RV64ZBB-NEXT:    ret
+  %c = call i64 @llvm.smin.i64(i64 %a, i64 -1)
+  ret i64 %c
+}