[RISCV] Move xori creation for scalar setccs to lowering.

[craig.topper]

Summary

This patch enables expansion or custom lowering for some integer
condition codes so that any xori that is needed is created before
the last DAG combine to enable optimization.

I've seen cases where we end up with
(or (xori (setcc), 1), (xori (setcc), 1)) which we would ideally
convert to (xori (and (setcc), (setcc)), 1). This patch doesn't
accomplish that yet, but it should allow us to add DAG
combines as follow ups. Example https://godbolt.org/z/Y4qnvsq1b

[craig.topper]

llvm/test/CodeGen/RISCV/rv32zbt.ll

656

The two xoris were the true and false values of the first cmov. The later two cmovs use the first cmov as a condition. We are now able to pull the xoris through the first cmov and fold it into the condition of the other two by swapping their true and false values.

llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

510

This appears to be a scheduling change only

llvm/test/CodeGen/RISCV/xaluo.ll

788–789

This is a special case related to the constant value -2. Originally we had setugt x, -2, which was converted to seteq x, -1 since that's the the only value unsigned greater than -2. We now convert it to the setult -2, x and the DAG combine misses the seteq opportunity since the constant is on the left hand side. This allows use to use the -2 for both the sub and the sltu.

[reames]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

3637

I'm not following something here. You're increment the rhs of a GT or UGT in the manner I'd expect to apply to a GE or UGE, but also not changing the condition code?

This looks like a dag combine btw, why does this need to be done during lowering at all?

3642

Why is swapping the operands correct here? I don't follow?

8351

I think the setcc here is only providing the 0 or 1 fact for N1, is there any way we can generalize? (e.g. known bits?) If so, we can probably separate and test separately.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

3637

The condition code was swapped on line 3623.

3642

Line 3623 swapped the condition code so it is now setlt or setltu

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

3637

Prior to LegalizeDAG it would probably be reversed by DAGCombiner. I think there's an setcc+xor combine that only checks CondCodeLegal after LegalOperations. I could write an opposite DAGCombine that only runs after lowering?

[reames]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

3637

I'm still not following.

Original:
GT LHS, RHS

New:
LTE LHS, RHS+1

That doesn't look correct? Unless maybe there's some implicit restriction on LHS and RHS I'm missing?

3642

Agreed.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

3637

We started with GT LHS, RHS. Swapped the condition code to LT, and emitted (xor (LT LHS, RHS+1), 1).

[craig.topper]

Add more comments to the setcc lowering code. Swap the operands when we swap
the condition code. Use isInt<12> for the range check after guarding against
signed integer overflow.

[craig.topper]

Fix a place that still used RHS when it needs to be LHS after the swap.

[craig.topper]

Use LHS instead of RHS in another place. Maybe I shouldn't have use std::swap...

[craig.topper]

-Refactor after an offline conversation with Philip.
-Remove one use check on the constant. It's too error prone at this level. We can't tell if the other use of the constant will be folded.

[craig.topper]

Rebase on D132000

[reames]

LGTM

Thanks for explaining this offline, the new structure makes a lot more sense to me.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   // TODO: add all necessary setOperationAction calls.
   setOperationAction(ISD::DYNAMIC_STACKALLOC, XLenVT, Expand);
 
   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
   setOperationAction(ISD::BR_CC, XLenVT, Expand);
   setOperationAction(ISD::BRCOND, MVT::Other, Custom);
   setOperationAction(ISD::SELECT_CC, XLenVT, Expand);
 
+  setCondCodeAction(ISD::SETLE, XLenVT, Expand);
+  setCondCodeAction(ISD::SETGT, XLenVT, Custom);
+  setCondCodeAction(ISD::SETGE, XLenVT, Expand);
+  setCondCodeAction(ISD::SETULE, XLenVT, Expand);
+  setCondCodeAction(ISD::SETUGT, XLenVT, Custom);
+  setCondCodeAction(ISD::SETUGE, XLenVT, Expand);
+
   setOperationAction({ISD::STACKSAVE, ISD::STACKRESTORE}, MVT::Other, Expand);
 
   setOperationAction(ISD::VASTART, MVT::Other, Custom);
   setOperationAction({ISD::VAARG, ISD::VACOPY, ISD::VAEND}, MVT::Other, Expand);
 
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
 
   setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
if (Op.getOperand(1).getValueType().isFixedLengthVector())
       return lowerFixedLengthVectorStoreToRVV(Op, DAG);
     return Op;
   case ISD::MLOAD:
   case ISD::VP_LOAD:
     return lowerMaskedLoad(Op, DAG);
   case ISD::MSTORE:
   case ISD::VP_STORE:
     return lowerMaskedStore(Op, DAG);
-  case ISD::SETCC:
+  case ISD::SELECT_CC: {
+    // This occurs because we custom legalize SETGT and SETUGT for setcc. That
+    // causes LegalizeDAG to think we need to custom legalize select_cc. Expand
+    // into separate SETCC+SELECT_CC just like LegalizeDAG.
+    SDValue Tmp1 = Op.getOperand(0);
+    SDValue Tmp2 = Op.getOperand(1);
+    SDValue True = Op.getOperand(2);
+    SDValue False = Op.getOperand(3);
+    EVT VT = Op.getValueType();
+    SDValue CC = Op.getOperand(4);
+    EVT CmpVT = Tmp1.getValueType();
+    EVT CCVT =
+        getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), CmpVT);
+    SDLoc DL(Op);
+    SDValue Cond =
+        DAG.getNode(ISD::SETCC, DL, CCVT, Tmp1, Tmp2, CC, Op->getFlags());
+    return DAG.getSelect(DL, VT, Cond, True, False);
+  }
+  case ISD::SETCC: {
+    MVT OpVT = Op.getOperand(0).getSimpleValueType();
+    if (OpVT.isScalarInteger()) {
+      MVT VT = Op.getSimpleValueType();
+      SDValue LHS = Op.getOperand(0);
+      SDValue RHS = Op.getOperand(1);
+      ISD::CondCode CCVal = cast<CondCodeSDNode>(Op.getOperand(2))->get();
+      assert((CCVal == ISD::SETGT || CCVal == ISD::SETUGT) &&
+             "Unexpected CondCode");
+      // Swap the operands and condition code to SETLT/SETULT.
+      CCVal = ISD::getSetCCSwappedOperands(CCVal);
+      std::swap(LHS, RHS);
+
+      SDLoc DL(Op);
+      // If the LHS is a constant, we're now forced to put it in a register.
+      // If the constant is in the range [-2049, 0) or (0, 2046], we can
+      // increment the constant and use slti(u)+xori without swapping the
+      // operands. This is equivalent to (set(u)ge OrigLHS, OrigRHS+1).
+      // FIXME: Is the one use check here necessary? It was copied when this
+      // was moved from an isel pattern.
+      if (isa<ConstantSDNode>(LHS) && RHS.hasOneUse()) {
+        int64_t Imm = cast<ConstantSDNode>(RHS)->getSExtValue();
+        if (Imm != 0 && Imm != INT64_MAX && isInt<12>(Imm + 1)) {
+          // If the constant is -1 and this an unsigned compare, we can't
+          // increment the immediate but the result is always false.
+          if (Imm == -1 && CCVal == ISD::SETULT)
+            return DAG.getConstant(0, DL, VT);
+          SDValue SetCC = DAG.getSetCC(
+              DL, VT, RHS, DAG.getConstant(Imm + 1, DL, OpVT), CCVal);
+          return DAG.getLogicalNOT(DL, SetCC, VT);
+        }
+      }
+
+      // Not a constant we could handle, create a swapped setcc.
+      return DAG.getSetCC(DL, VT, LHS, RHS, CCVal);
+    }
+
     return lowerFixedLengthVectorSetccToRVV(Op, DAG);
+  }
   case ISD::ADD:
     return lowerToScalableOp(Op, DAG, RISCVISD::ADD_VL, /*HasMergeOp*/ true);
   case ISD::SUB:
     return lowerToScalableOp(Op, DAG, RISCVISD::SUB_VL, /*HasMergeOp*/ true);
   case ISD::MUL:
     return lowerToScalableOp(Op, DAG, RISCVISD::MUL_VL, /*HasMergeOp*/ true);
   case ISD::MULHS:
     return lowerToScalableOp(Op, DAG, RISCVISD::MULHS_VL, /*HasMergeOp*/ true);

 
 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
 
   // Prefer to make this 'add 0/1' rather than 'sub 0/1'
   // sub constant(!0), 0/1 -> add constant - 1, 1/0
   // NODE: constant == 0, No redundant instructions are generated.
   // (sub constant, (setcc x, y, eq/neq)) ->
   // (add (setcc x, y, neq/eq), constant - 1)
   auto *Nnz0 = dyn_cast<ConstantSDNode>(N0);
   if (Nnz0 && N1.getOpcode() == ISD::SETCC && N1.hasOneUse()) {
     const auto *CC = cast<CondCodeSDNode>(N1->getOperand(2));
     ISD::CondCode CCVal = CC->get();
     if (!Nnz0->isZero() && isIntEqualitySetCC(CCVal)) {
       EVT VT = N->getValueType(0);
       const APInt &ImmVal = Nnz0->getAPIntValue();
       SDValue CCInverse =
           DAG.getCondCode(ISD::getSetCCInverse(CCVal, N0.getValueType()));
       SDValue NewN0 = DAG.getNode(ISD::SETCC, SDLoc(N), VT, N1->getOperand(0),
                                   N1->getOperand(1), CCInverse);
       SDValue NewN1 = DAG.getConstant(ImmVal - 1, SDLoc(N), VT);
       return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewN0, NewN1);
     }
   }
 
+  // Fold (neg (xor (setcc), 1)) -> (add (setcc), -1)
+  // The is equivalent to 1-X and negating gives X-1.
+  if (isNullConstant(N0) && N1.getOpcode() == ISD::XOR &&
+      N1.getOperand(0).getOpcode() == ISD::SETCC &&
+      isOneConstant(N1.getOperand(1))) {
+    SDLoc dl(N);
+    EVT VT = N->getValueType(0);
+    return DAG.getNode(ISD::ADD, dl, VT, N1.getOperand(0),
+                       DAG.getConstant(-1, dl, VT));
+  }
+
   // fold (sub x, (select lhs, rhs, cc, 0, y)) ->
   //      (select lhs, rhs, cc, x, (sub x, y))
   return combineSelectAndUse(N, N1, N0, DAG, /*AllOnes*/ false);
 }
 
 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
                                  const RISCVSubtarget &Subtarget) {
   SDValue N0 = N->getOperand(0);

llvm/lib/Target/RISCV/RISCVInstrInfo.td

def : Pat<(seteq GPR:$rs1, -2048),
           (SLTIU (XORI GPR:$rs1, -2048), 1)>;
 def : Pat<(setne GPR:$rs1, 0), (SLTU X0, GPR:$rs1)>;
 def : Pat<(setne GPR:$rs1, GPR:$rs2), (SLTU X0, (XOR GPR:$rs1, GPR:$rs2))>;
 def : Pat<(setne GPR:$rs1, simm12_plus1:$imm12),
           (SLTU X0, (ADDI GPR:$rs1, (NegImm simm12_plus1:$imm12)))>;
 def : Pat<(setne GPR:$rs1, -2048),
           (SLTU X0, (XORI GPR:$rs1, -2048))>;
 def : Pat<(setne GPR:$rs1, -1), (SLTIU GPR:$rs1, -1)>;
-def : Pat<(setugt GPR:$rs1, GPR:$rs2), (SLTU GPR:$rs2, GPR:$rs1)>;
-def : Pat<(setuge GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs1, GPR:$rs2), 1)>;
-def : Pat<(setule GPR:$rs1, GPR:$rs2), (XORI (SLTU GPR:$rs2, GPR:$rs1), 1)>;
-def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>;
-def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>;
-def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>;
-def : Pat<(setgt GPR:$rs1, simm12_minus1_nonzero:$imm),
-          (XORI (SLTI GPR:$rs1, (ImmPlus1 simm12_minus1_nonzero:$imm)), 1)>;
-def : Pat<(setugt GPR:$rs1, simm12_minus1_nonzero:$imm),
-          (XORI (SLTIU GPR:$rs1, (ImmPlus1 simm12_minus1_nonzero:$imm)), 1)>;
-
-// If negating a pattern that requires an XORI above, we can fold the XORI with
-// the NEG. The XORI is equivalent to 1-X and negating gives X-1.
-def : Pat<(ineg (setuge GPR:$rs1, GPR:$rs2)),
-          (ADDI (SLTU GPR:$rs1, GPR:$rs2), -1)>;
-def : Pat<(ineg (setule GPR:$rs1, GPR:$rs2)),
-          (ADDI (SLTU GPR:$rs2, GPR:$rs1), -1)>;
-def : Pat<(ineg (setge GPR:$rs1, GPR:$rs2)),
-          (ADDI (SLT GPR:$rs1, GPR:$rs2), -1)>;
-def : Pat<(ineg (setle GPR:$rs1, GPR:$rs2)),
-          (ADDI (SLT GPR:$rs2, GPR:$rs1), -1)>;
-def : Pat<(ineg (setgt GPR:$rs1, simm12_minus1_nonzero:$imm)),
-          (ADDI (SLTI GPR:$rs1, (ImmPlus1 simm12_minus1_nonzero:$imm)), -1)>;
-def : Pat<(ineg (setugt GPR:$rs1, simm12_minus1_nonzero:$imm)),
-          (ADDI (SLTIU GPR:$rs1, (ImmPlus1 simm12_minus1_nonzero:$imm)), -1)>;
-
-def ineg_allwusers : PatFrag<(ops node:$src),
-                             (ineg node:$src), [{
-  return hasAllWUsers(Node);
-}]>;
-
-let Predicates = [IsRV64] in {
-def : Pat<(ineg_allwusers (setuge GPR:$rs1, GPR:$rs2)),
-          (ADDIW (SLTU GPR:$rs1, GPR:$rs2), -1)>;
-def : Pat<(ineg_allwusers (setule GPR:$rs1, GPR:$rs2)),
-          (ADDIW (SLTU GPR:$rs2, GPR:$rs1), -1)>;
-def : Pat<(ineg_allwusers (setge GPR:$rs1, GPR:$rs2)),
-          (ADDIW (SLT GPR:$rs1, GPR:$rs2), -1)>;
-def : Pat<(ineg_allwusers (setle GPR:$rs1, GPR:$rs2)),
-          (ADDIW (SLT GPR:$rs2, GPR:$rs1), -1)>;
-def : Pat<(ineg_allwusers (setgt GPR:$rs1, simm12_minus1_nonzero:$imm)),
-          (ADDIW (SLTI GPR:$rs1, (ImmPlus1 simm12_minus1_nonzero:$imm)), -1)>;
-def : Pat<(ineg_allwusers (setugt GPR:$rs1, simm12_minus1_nonzero:$imm)),
-          (ADDIW (SLTIU GPR:$rs1, (ImmPlus1 simm12_minus1_nonzero:$imm)), -1)>;
-}
 
 def IntCCtoRISCVCC : SDNodeXForm<riscv_selectcc, [{
   ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
   RISCVCC::CondCode BrCC = getRISCVCCForIntCC(CC);
   return CurDAG->getTargetConstant(BrCC, SDLoc(N), Subtarget->getXLenVT());
 }]>;
 
 def riscv_selectcc_frag : PatFrag<(ops node:$lhs, node:$rhs, node:$cc,

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

 def : Pat<(select (XLenVT (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, GPR:$rs3),
           (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
 def : Pat<(select (XLenVT (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>;
 def : Pat<(select (XLenVT (setne GPR:$x, GPR:$y)), GPR:$rs1, GPR:$rs3),
           (CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
 def : Pat<(select (XLenVT (seteq GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
           (CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>;
-def : Pat<(select (XLenVT (setuge GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
-          (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
-def : Pat<(select (XLenVT (setule GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1),
-          (CMOV GPR:$rs1, (SLTU GPR:$x, GPR:$y), GPR:$rs3)>;
-def : Pat<(select (XLenVT (setge GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1),
-          (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
-def : Pat<(select (XLenVT (setle GPR:$y, GPR:$x)), GPR:$rs3, GPR:$rs1),
-          (CMOV GPR:$rs1, (SLT GPR:$x, GPR:$y), GPR:$rs3)>;
-
-// setge X, Imm is canonicalized to setgt X, (Imm - 1).
-def : Pat<(select (XLenVT (setgt GPR:$x, simm12_minus1_nonzero:$imm)), GPR:$rs3, GPR:$rs1),
-          (CMOV GPR:$rs1, (SLTI GPR:$x, (ImmPlus1 simm12_minus1_nonzero:$imm)), GPR:$rs3)>;
-def : Pat<(select (XLenVT (setugt GPR:$x, simm12_minus1_nonzero:$imm)), GPR:$rs3, GPR:$rs1),
-          (CMOV GPR:$rs1, (SLTIU GPR:$x, (ImmPlus1 simm12_minus1_nonzero:$imm)), GPR:$rs3)>;
 
 def : Pat<(select GPR:$rs2, GPR:$rs1, GPR:$rs3),
           (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 } // Predicates = [HasStdExtZbt]
 
 let Predicates = [HasStdExtZbt] in {
 def : Pat<(riscv_fsl GPR:$rs1, GPR:$rs3, GPR:$rs2),
           (FSL GPR:$rs1, GPR:$rs2, GPR:$rs3)>;

llvm/test/CodeGen/RISCV/rv32zbt.ll

 ; RV32I-NEXT:  .LBB31_3:
 ; RV32I-NEXT:    mv a0, a6
 ; RV32I-NEXT:    mv a1, a7
 ; RV32I-NEXT:  .LBB31_4:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_sle_i64:
 ; RV32ZBT:       # %bb.0:
-; RV32ZBT-NEXT:    xor t0, a3, a5
 ; RV32ZBT-NEXT:    sltu a2, a4, a2
-; RV32ZBT-NEXT:    xori a2, a2, 1
+; RV32ZBT-NEXT:    xor a4, a3, a5
 ; RV32ZBT-NEXT:    slt a3, a5, a3
-; RV32ZBT-NEXT:    xori a3, a3, 1
-; RV32ZBT-NEXT:    cmov a2, t0, a3, a2
-; RV32ZBT-NEXT:    cmov a0, a2, a0, a6
-; RV32ZBT-NEXT:    cmov a1, a2, a1, a7
+; RV32ZBT-NEXT:    cmov a2, a4, a3, a2
+; RV32ZBT-NEXT:    cmov a0, a2, a6, a0
+; RV32ZBT-NEXT:    cmov a1, a2, a7, a1
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp sle i64 %b, %c
   %cond = select i1 %tobool, i64 %a, i64 %d
   ret i64 %cond
 }
 
 define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
 ; RV32I-LABEL: cmov_sge_i64:

 ; RV32I-NEXT:  .LBB32_3:
 ; RV32I-NEXT:    mv a0, a6
 ; RV32I-NEXT:    mv a1, a7
 ; RV32I-NEXT:  .LBB32_4:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_sge_i64:
 ; RV32ZBT:       # %bb.0:
-; RV32ZBT-NEXT:    xor t0, a3, a5
 ; RV32ZBT-NEXT:    sltu a2, a2, a4
-; RV32ZBT-NEXT:    xori a2, a2, 1
+; RV32ZBT-NEXT:    xor a4, a3, a5
 ; RV32ZBT-NEXT:    slt a3, a3, a5
-; RV32ZBT-NEXT:    xori a3, a3, 1
-; RV32ZBT-NEXT:    cmov a2, t0, a3, a2
-; RV32ZBT-NEXT:    cmov a0, a2, a0, a6
-; RV32ZBT-NEXT:    cmov a1, a2, a1, a7
+; RV32ZBT-NEXT:    cmov a2, a4, a3, a2
+; RV32ZBT-NEXT:    cmov a0, a2, a6, a0
+; RV32ZBT-NEXT:    cmov a1, a2, a7, a1
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp sge i64 %b, %c
   %cond = select i1 %tobool, i64 %a, i64 %d
   ret i64 %cond
 }
 
 define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
 ; RV32I-LABEL: cmov_ule_i64:

 ; RV32I-NEXT:  .LBB33_3:
 ; RV32I-NEXT:    mv a0, a6
 ; RV32I-NEXT:    mv a1, a7
 ; RV32I-NEXT:  .LBB33_4:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_ule_i64:
 ; RV32ZBT:       # %bb.0:
-; RV32ZBT-NEXT:    xor t0, a3, a5
 ; RV32ZBT-NEXT:    sltu a2, a4, a2
-; RV32ZBT-NEXT:    xori a2, a2, 1
+; RV32ZBT-NEXT:    xor a4, a3, a5
 ; RV32ZBT-NEXT:    sltu a3, a5, a3
-; RV32ZBT-NEXT:    xori a3, a3, 1
-; RV32ZBT-NEXT:    cmov a2, t0, a3, a2
-; RV32ZBT-NEXT:    cmov a0, a2, a0, a6
-; RV32ZBT-NEXT:    cmov a1, a2, a1, a7
+; RV32ZBT-NEXT:    cmov a2, a4, a3, a2
+; RV32ZBT-NEXT:    cmov a0, a2, a6, a0
+; RV32ZBT-NEXT:    cmov a1, a2, a7, a1
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp ule i64 %b, %c
   %cond = select i1 %tobool, i64 %a, i64 %d
   ret i64 %cond
 }
 
 define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
 ; RV32I-LABEL: cmov_uge_i64:

 ; RV32I-NEXT:  .LBB34_3:
 ; RV32I-NEXT:    mv a0, a6
 ; RV32I-NEXT:    mv a1, a7
 ; RV32I-NEXT:  .LBB34_4:
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: cmov_uge_i64:
 ; RV32ZBT:       # %bb.0:
-; RV32ZBT-NEXT:    xor t0, a3, a5
 ; RV32ZBT-NEXT:    sltu a2, a2, a4
-; RV32ZBT-NEXT:    xori a2, a2, 1
+; RV32ZBT-NEXT:    xor a4, a3, a5
 ; RV32ZBT-NEXT:    sltu a3, a3, a5
-; RV32ZBT-NEXT:    xori a3, a3, 1
-; RV32ZBT-NEXT:    cmov a2, t0, a3, a2
-; RV32ZBT-NEXT:    cmov a0, a2, a0, a6
-; RV32ZBT-NEXT:    cmov a1, a2, a1, a7
+; RV32ZBT-NEXT:    cmov a2, a4, a3, a2
+; RV32ZBT-NEXT:    cmov a0, a2, a6, a0
+; RV32ZBT-NEXT:    cmov a1, a2, a7, a1
 ; RV32ZBT-NEXT:    ret
   %tobool = icmp uge i64 %b, %c
   %cond = select i1 %tobool, i64 %a, i64 %d
   ret i64 %cond
 }
 
 declare i32 @llvm.fshl.i32(i32, i32, i32)
 

llvm/test/CodeGen/RISCV/select-cc.ll

 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:  .LBB3_5:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBT-LABEL: select_sge_int32min:
 ; RV32ZBT:       # %bb.0:
+; RV32ZBT-NEXT:    li a6, -1
+; RV32ZBT-NEXT:    slt a6, a6, a1
 ; RV32ZBT-NEXT:    slti a0, a0, 0
-; RV32ZBT-NEXT:    addi a6, a1, 1
-; RV32ZBT-NEXT:    slti a1, a1, 0
-; RV32ZBT-NEXT:    xori a1, a1, 1
-; RV32ZBT-NEXT:    cmov a1, a6, a1, a0
+; RV32ZBT-NEXT:    addi a1, a1, 1
+; RV32ZBT-NEXT:    cmov a1, a1, a6, a0
 ; RV32ZBT-NEXT:    cmov a0, a1, a2, a4
 ; RV32ZBT-NEXT:    cmov a1, a1, a3, a5
 ; RV32ZBT-NEXT:    ret
 ;
 ; RV64I-LABEL: select_sge_int32min:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a3, 524288
 ; RV64I-NEXT:    addi a3, a3, -1

llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

 ; RV32-NEXT:    srli s2, a1, 11
 ; RV32-NEXT:    andi a0, a1, 2047
 ; RV32-NEXT:    li a1, 683
 ; RV32-NEXT:    call __mulsi3@plt
 ; RV32-NEXT:    slli a1, a0, 10
 ; RV32-NEXT:    slli a0, a0, 21
 ; RV32-NEXT:    srli a0, a0, 22
 ; RV32-NEXT:    or a0, a0, a1
-; RV32-NEXT:    andi s3, a0, 2047
+; RV32-NEXT:    andi a0, a0, 2047
+; RV32-NEXT:    sltiu s3, a0, 342
 ; RV32-NEXT:    li a1, 819
 ; RV32-NEXT:    mv a0, s1
 ; RV32-NEXT:    call __mulsi3@plt
 ; RV32-NEXT:    addi a0, a0, -1638
 ; RV32-NEXT:    andi a0, a0, 2047
 ; RV32-NEXT:    li a1, 1
 ; RV32-NEXT:    sltu s1, a1, a0
 ; RV32-NEXT:    li a1, 1463
 ; RV32-NEXT:    mv a0, s2
 ; RV32-NEXT:    call __mulsi3@plt
 ; RV32-NEXT:    addi a0, a0, -1463
 ; RV32-NEXT:    andi a0, a0, 2047
-; RV32-NEXT:    sltiu a1, s3, 342
-; RV32-NEXT:    addi a1, a1, -1
 ; RV32-NEXT:    sltiu a0, a0, 293
+; RV32-NEXT:    addi a1, s3, -1
 ; RV32-NEXT:    addi a0, a0, -1
 ; RV32-NEXT:    neg a2, s1
 ; RV32-NEXT:    slli a2, a2, 21
 ; RV32-NEXT:    srli a2, a2, 31
 ; RV32-NEXT:    sb a2, 4(s0)
 ; RV32-NEXT:    andi a1, a1, 2047
 ; RV32-NEXT:    andi a0, a0, 2047
 ; RV32-NEXT:    slli a0, a0, 11

 ; RV64-NEXT:    srli s2, a0, 22
 ; RV64-NEXT:    andi a0, a0, 2047
 ; RV64-NEXT:    li a1, 683
 ; RV64-NEXT:    call __muldi3@plt
 ; RV64-NEXT:    slli a1, a0, 10
 ; RV64-NEXT:    slli a0, a0, 53
 ; RV64-NEXT:    srli a0, a0, 54
 ; RV64-NEXT:    or a0, a0, a1
-; RV64-NEXT:    andi s3, a0, 2047
+; RV64-NEXT:    andi a0, a0, 2047
+; RV64-NEXT:    sltiu s3, a0, 342
 ; RV64-NEXT:    li a1, 819
 ; RV64-NEXT:    mv a0, s2
 ; RV64-NEXT:    call __muldi3@plt
 ; RV64-NEXT:    addiw a0, a0, -1638
 ; RV64-NEXT:    andi a0, a0, 2047
 ; RV64-NEXT:    li a1, 1
 ; RV64-NEXT:    sltu s2, a1, a0
 ; RV64-NEXT:    li a1, 1463
 ; RV64-NEXT:    mv a0, s1
 ; RV64-NEXT:    call __muldi3@plt
 ; RV64-NEXT:    addiw a0, a0, -1463
 ; RV64-NEXT:    andi a0, a0, 2047
-; RV64-NEXT:    sltiu a1, s3, 342
-; RV64-NEXT:    addiw a1, a1, -1
 ; RV64-NEXT:    sltiu a0, a0, 293
+; RV64-NEXT:    addiw a1, s3, -1
 ; RV64-NEXT:    addiw a0, a0, -1
 ; RV64-NEXT:    andi a1, a1, 2047
 ; RV64-NEXT:    andi a0, a0, 2047
 ; RV64-NEXT:    slli a0, a0, 11
 ; RV64-NEXT:    or a0, a1, a0
 ; RV64-NEXT:    slli a1, s2, 22
 ; RV64-NEXT:    sub a0, a0, a1
 ; RV64-NEXT:    sw a0, 0(s0)

 ; RV32M-NEXT:    andi a2, a2, 2047
 ; RV32M-NEXT:    li a4, 683
 ; RV32M-NEXT:    mul a2, a2, a4
 ; RV32M-NEXT:    slli a4, a2, 10
 ; RV32M-NEXT:    slli a2, a2, 21
 ; RV32M-NEXT:    srli a2, a2, 22
 ; RV32M-NEXT:    or a2, a2, a4
 ; RV32M-NEXT:    andi a2, a2, 2047
+; RV32M-NEXT:    sltiu a2, a2, 342
 ; RV32M-NEXT:    li a4, 819
 ; RV32M-NEXT:    mul a1, a1, a4
 ; RV32M-NEXT:    addi a1, a1, -1638
 ; RV32M-NEXT:    andi a1, a1, 2047
 ; RV32M-NEXT:    li a4, 1
 ; RV32M-NEXT:    sltu a1, a4, a1
 ; RV32M-NEXT:    li a4, 1463
 ; RV32M-NEXT:    mul a3, a3, a4
 ; RV32M-NEXT:    addi a3, a3, -1463
 ; RV32M-NEXT:    andi a3, a3, 2047
-; RV32M-NEXT:    sltiu a2, a2, 342
-; RV32M-NEXT:    addi a2, a2, -1
 ; RV32M-NEXT:    sltiu a3, a3, 293
+; RV32M-NEXT:    addi a2, a2, -1
 ; RV32M-NEXT:    addi a3, a3, -1
 ; RV32M-NEXT:    neg a4, a1
 ; RV32M-NEXT:    slli a4, a4, 21
 ; RV32M-NEXT:    srli a4, a4, 31
 ; RV32M-NEXT:    sb a4, 4(a0)
 ; RV32M-NEXT:    andi a2, a2, 2047
 ; RV32M-NEXT:    andi a3, a3, 2047
 ; RV32M-NEXT:    slli a3, a3, 11

 ; RV64M-NEXT:    andi a1, a1, 2047
 ; RV64M-NEXT:    li a4, 683
 ; RV64M-NEXT:    mul a1, a1, a4
 ; RV64M-NEXT:    slli a4, a1, 10
 ; RV64M-NEXT:    slli a1, a1, 53
 ; RV64M-NEXT:    srli a1, a1, 54
 ; RV64M-NEXT:    or a1, a1, a4
 ; RV64M-NEXT:    andi a1, a1, 2047
+; RV64M-NEXT:    sltiu a1, a1, 342
 ; RV64M-NEXT:    li a4, 819
 ; RV64M-NEXT:    mulw a3, a3, a4
 ; RV64M-NEXT:    addiw a3, a3, -1638
 ; RV64M-NEXT:    andi a3, a3, 2047
 ; RV64M-NEXT:    li a4, 1
 ; RV64M-NEXT:    sltu a3, a4, a3
 ; RV64M-NEXT:    li a4, 1463
 ; RV64M-NEXT:    mulw a2, a2, a4
 ; RV64M-NEXT:    addiw a2, a2, -1463
 ; RV64M-NEXT:    andi a2, a2, 2047
-; RV64M-NEXT:    sltiu a1, a1, 342
-; RV64M-NEXT:    addiw a1, a1, -1
 ; RV64M-NEXT:    sltiu a2, a2, 293
+; RV64M-NEXT:    addiw a1, a1, -1
 ; RV64M-NEXT:    addiw a2, a2, -1
 ; RV64M-NEXT:    andi a1, a1, 2047
 ; RV64M-NEXT:    andi a2, a2, 2047
 ; RV64M-NEXT:    slli a2, a2, 11
 ; RV64M-NEXT:    or a1, a1, a2
 ; RV64M-NEXT:    slli a2, a3, 22
 ; RV64M-NEXT:    sub a1, a1, a2
 ; RV64M-NEXT:    sw a1, 0(a0)

llvm/test/CodeGen/RISCV/xaluo.ll

entry:
   %obit = extractvalue {i32, i1} %t, 1
   store i32 %val, i32* %res
   ret i1 %obit
 }
 
 define zeroext i1 @usubo.i32.constant.lhs(i32 %v1, i32* %res) {
 ; RV32-LABEL: usubo.i32.constant.lhs:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:    li a2, -2
-; RV32-NEXT:    sub a2, a2, a0
-; RV32-NEXT:    addi a0, a2, 1
-; RV32-NEXT:    seqz a0, a0
-; RV32-NEXT:    sw a2, 0(a1)
+; RV32-NEXT:    sub a3, a2, a0
+; RV32-NEXT:    sltu a0, a2, a3
+; RV32-NEXT:    sw a3, 0(a1)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: usubo.i32.constant.lhs:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    li a2, -2
 ; RV64-NEXT:    subw a2, a2, a0
 ; RV64-NEXT:    addi a0, a2, 1
 ; RV64-NEXT:    seqz a0, a0
 ; RV64-NEXT:    sw a2, 0(a1)
 ; RV64-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: usubo.i32.constant.lhs:
 ; RV32ZBA:       # %bb.0: # %entry
 ; RV32ZBA-NEXT:    li a2, -2
-; RV32ZBA-NEXT:    sub a2, a2, a0
-; RV32ZBA-NEXT:    addi a0, a2, 1
-; RV32ZBA-NEXT:    seqz a0, a0
-; RV32ZBA-NEXT:    sw a2, 0(a1)
+; RV32ZBA-NEXT:    sub a3, a2, a0
+; RV32ZBA-NEXT:    sltu a0, a2, a3
+; RV32ZBA-NEXT:    sw a3, 0(a1)
 ; RV32ZBA-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: usubo.i32.constant.lhs:
 ; RV64ZBA:       # %bb.0: # %entry
 ; RV64ZBA-NEXT:    li a2, -2
 ; RV64ZBA-NEXT:    subw a2, a2, a0
 ; RV64ZBA-NEXT:    addi a0, a2, 1
 ; RV64ZBA-NEXT:    seqz a0, a0