[RISCV] Fold (sub C, (xor (setcc), 1)) -> (add (setcc), C-1).

[craig.topper]

Summary

Extracted from D131729 where we handled C==0. It's now generalized
to more constants.

[reames]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (N1.getOpcode() == ISD::SETCC && N1.hasOneUse()) {
     // (add (setcc x, y, neq/eq), constant - 1)
     ISD::CondCode CCVal = cast<CondCodeSDNode>(N1.getOperand(2))->get();
     EVT SetCCOpVT = N1.getOperand(0).getValueType();
     if (!isIntEqualitySetCC(CCVal) || !SetCCOpVT.isInteger())
       return SDValue();
     CCVal = ISD::getSetCCInverse(CCVal, SetCCOpVT);
     NewLHS =
         DAG.getSetCC(SDLoc(N1), VT, N1.getOperand(0), N1.getOperand(1), CCVal);
+  } else if (N1.getOpcode() == ISD::XOR && isOneConstant(N1.getOperand(1)) &&
+             N1.getOperand(0).getOpcode() == ISD::SETCC) {
+    // (sub C, (xor (setcc), 1)) -> (add (setcc), C-1).
+    // Since setcc returns a bool the xor is equivalent to 1-setcc.
+    NewLHS = N1.getOperand(0);
   } else
     return SDValue();
 
   SDValue NewRHS = DAG.getConstant(ImmValMinus1, DL, VT);
   return DAG.getNode(ISD::ADD, DL, VT, NewLHS, NewRHS);
 }
 
 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG) {

llvm/test/CodeGen/RISCV/double-select-fcmp.ll

; CHECK-NEXT:    ret
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }
 
 define signext i32 @select_fcmp_uge_negone_zero(double %a, double %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge_negone_zero:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.d a0, fa0, fa1
-; CHECK-NEXT:    xori a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    addi a0, a0, -1
 ; CHECK-NEXT:    ret
   %1 = fcmp ugt double %a, %b
   %2 = select i1 %1, i32 -1, i32 0
   ret i32 %2
 }
 
 define signext i32 @select_fcmp_uge_1_2(double %a, double %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge_1_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.d a0, fa0, fa1
-; CHECK-NEXT:    xori a0, a0, 1
-; CHECK-NEXT:    li a1, 2
-; CHECK-NEXT:    sub a0, a1, a0
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    ret
   %1 = fcmp ugt double %a, %b
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/float-select-fcmp.ll

; CHECK-NEXT:    ret
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }
 
 define signext i32 @select_fcmp_uge_negone_zero(float %a, float %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge_negone_zero:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.s a0, fa0, fa1
-; CHECK-NEXT:    xori a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    addi a0, a0, -1
 ; CHECK-NEXT:    ret
   %1 = fcmp ugt float %a, %b
   %2 = select i1 %1, i32 -1, i32 0
   ret i32 %2
 }
 
 define signext i32 @select_fcmp_uge_1_2(float %a, float %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge_1_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.s a0, fa0, fa1
-; CHECK-NEXT:    xori a0, a0, 1
-; CHECK-NEXT:    li a1, 2
-; CHECK-NEXT:    sub a0, a1, a0
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    ret
   %1 = fcmp ugt float %a, %b
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/half-select-fcmp.ll

; CHECK-NEXT:    ret
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }
 
 define signext i32 @select_fcmp_uge_negone_zero(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge_negone_zero:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa0, fa1
-; CHECK-NEXT:    xori a0, a0, 1
-; CHECK-NEXT:    neg a0, a0
+; CHECK-NEXT:    addi a0, a0, -1
 ; CHECK-NEXT:    ret
   %1 = fcmp ugt half %a, %b
   %2 = select i1 %1, i32 -1, i32 0
   ret i32 %2
 }
 
 define signext i32 @select_fcmp_uge_1_2(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge_1_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa0, fa1
-; CHECK-NEXT:    xori a0, a0, 1
-; CHECK-NEXT:    li a1, 2
-; CHECK-NEXT:    sub a0, a1, a0
+; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    ret
   %1 = fcmp ugt half %a, %b
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }