[RISCV] Optimize SELECT_CC when the true value of select is Constant

[liaolucy]

Summary

(select (setcc lhs, rhs, CC), constant, falsev) -> (select (setcc lhs, rhs, InverseCC), falsev, constant)

This patch removes unnecessary copies

[craig.topper]

Without mention SELECT_CC, this title sounds very confusing.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4299

This transform is equally valid to turn SETNE into SETEQ right?

[liaolucy]

address craig.topper's comments and thanks

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4299

This is valid for any condition code isn't it? We just need to invert the condition code.

[liaolucy]

1. address craig.topper's comments, remove condition code check.

2. Also remove ConstantSDNode->isZero().

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4210

There's already ISD::getSetCCInverse in ISDOpcodes.h

[liaolucy]

address craig.topper's comments , thanks

[frasercrmck]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4302

InverseCC might be more canonical here?

4305

Could we instead just std::swap(TrueV, FalseV) and let it fall through? I think that's clearer to read.

[asb]

Did you investigate any cases where this results in slightly worse codegen? one example would be 20100416-1.c from the GCC torture suite (-march=rv64imafdc -mabi=lp64d -O3). Overall the change seems to be positive, but there do seem to be a few cases like this where enabling this transformation results in an increase in instructions.

It needn't necessarily block this patch, as it does seem like a sensible transformation to make - but it would be useful to understand why these regressions occur, and capture some representative test cases.

[liaolucy]

1. Address @frasercrmck's comments
2. Address @asb's comments. Fix negative optimization of 20100416-1.c from the GCC torture suite. No optimization is required when TrueV and FalseV are both constants.

selectcc-to-shiftand.ll has an example already covering this type.

define i32 @pos_sel_constants(i32 signext %a) {
; CHECK-LABEL: pos_sel_constants:
; CHECK:       # %bb.0:
; CHECK-NEXT:    mv a1, a0
; CHECK-NEXT:    li a0, 5
; CHECK-NEXT:    bgez a1, .LBB4_2
; CHECK-NEXT:  # %bb.1:
; CHECK-NEXT:    li a0, 0
; CHECK-NEXT:  .LBB4_2:
; CHECK-NEXT:    ret
  %tmp.1 = icmp sgt i32 %a, -1
  %retval = select i1 %tmp.1, i32 5, i32 0
  ret i32 %retval
}

[jrtc27]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4305

This still isn't falling through. Ops and the return are identical to outside the if, you can just reuse them.

[asb]

In D129757#3661387, @liaolucy wrote:

1. Address @frasercrmck's comments
2. Address @asb's comments. Fix negative optimization of 20100416-1.c from the GCC torture suite. No optimization is required when TrueV and FalseV are both constants.

selectcc-to-shiftand.ll has an example already covering this type.

Thanks, that fixes that regression. I also see increased instruction counts for other tests including: pr20100-1, pr25125, pr37102, pr68506, pr83383, pr89634 (O3, rv64imafdc, lp64d). The overall impact across the suite seems positive, but it's likely worth taking a look.

[liaolucy]

Thanks, that fixes that regression. I also see increased instruction counts for other tests including: pr20100-1, pr25125, pr37102, pr68506, pr83383, pr89634 (O3, rv64imafdc, lp64d). The overall impact across the suite seems positive, but it's likely worth taking a look.

I used a stupid way to count valid static instructions. Dump .s file and remove comments, label and other useless information. If there is a better way I am willing to try it.

pr20100-1: The number of instructions is the same, both are 70.

pr37102, pr68506, pr89634: This patch has 1 more j instructions.
pr83383: This patch has 2 more j instructions.

Eg, from Pr83383.c: 
original：
       li      a0, 0
       beqz    a4, .LBB0_2

This patch:
       bnez    a3, .LBB0_2
newbb: li      a0, 0 
       j       .LBB0_3      -------------------------------- +1

Pr25125.c: +3 instructions.

original：
f:                                      # @f
# %bb.0:                                # %entry
        li      a1, 0
        bgtz    a0, .LBB0_2
# %bb.1:                                # %entry
        lui     a1, 8
        xor     a1, a1, a0
.LBB0_2:                                # %entry
        slli    a0, a1, 48
        srli    a0, a0, 48
        ret


This patch：
f:                                      # @f
# %bb.0:                                # %entry
        blez    a0, .LBB0_2
# %bb.1:                                # %entry
        li      a0, 0
        slli    a0, a0, 48  --------------------copy--------- +1
        srli    a0, a0, 48  --------------------copy--------- +2
        ret                 --------------------copy--------- +3
.LBB0_2:
        lui     a1, 8
        xor     a0, a0, a1
        slli    a0, a0, 48
        srli    a0, a0, 48
        ret

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4305

I'll update it back later.
SDValue Ops[] = {LHS, RHS, TargetCC, FalseV, TrueV,};

[liaolucy]

Address jrtc27's comment

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4305

This is still not the addressing the comment. This was the request

if (isa<ConstantSDNode>(TrueV) && !isa<ConstantSDNode>(FalseV)) {
  std::swap(TrueV, FalseV)
  TargetCC =
      DAG.getCondCode(ISD::getSetCCInverse(CCVal, LHS.getValueType()));
}

SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
return DAG.getNode(RISCVISD::SELECT_CC, DL, Op.getValueType(), Ops);

[liaolucy]

Update. I am sorry that I didn't understand well. Thanks,craig.topper.

[craig.topper]

I lost track of this patch for a while, but I just stumbled onto a case that would benefit. Can you rebase this?

[liaolucy]

rebase

[craig.topper]

LGTM

[liaolucy]

rebase

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op,
   case TLSModel::GeneralDynamic:
     Addr = getDynamicTLSAddr(N, DAG);
     break;
   }
 
   return Addr;
 }
 
 SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
   SDValue CondV = Op.getOperand(0);
   SDValue TrueV = Op.getOperand(1);
   SDValue FalseV = Op.getOperand(2);
   SDLoc DL(Op);
   MVT VT = Op.getSimpleValueType();
   MVT XLenVT = Subtarget.getXLenVT();
 
   // Lower vector SELECTs to VSELECTs by splatting the condition.
if (CondV.getOpcode() == ISD::SETCC &&
 
     // x <s -1 ? x : -1 -> x <s 0 ? x : -1
     if (isAllOnesConstant(RHS) && CCVal == ISD::SETLT && LHS == TrueV &&
         RHS == FalseV) {
       RHS = DAG.getConstant(0, DL, VT);
     }
 
     SDValue TargetCC = DAG.getCondCode(CCVal);
+
+    if (isa<ConstantSDNode>(TrueV) && !isa<ConstantSDNode>(FalseV)) {
+      // (select (setcc lhs, rhs, CC), constant, falsev)
+      // -> (select (setcc lhs, rhs, InverseCC), falsev, constant)
+      std::swap(TrueV, FalseV);
+      TargetCC =
+          DAG.getCondCode(ISD::getSetCCInverse(CCVal, LHS.getValueType()));
+    }
+
     SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
     return DAG.getNode(RISCVISD::SELECT_CC, DL, VT, Ops);
   }
 
   // Otherwise:
   // (select condv, truev, falsev)
   // -> (riscvisd::select_cc condv, zero, setne, truev, falsev)
   SDValue Zero = DAG.getConstant(0, DL, XLenVT);

llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll

 ; RV32I-NEXT:    call __mulsi3@plt
 ; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lui a0, %hi(.LCPI3_0)
 ; RV32I-NEXT:    addi s4, a0, %lo(.LCPI3_0)
 ; RV32I-NEXT:    neg a0, s2
 ; RV32I-NEXT:    and a0, s2, a0
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    call __mulsi3@plt
-; RV32I-NEXT:    li a1, 32
-; RV32I-NEXT:    beqz s2, .LBB3_2
+; RV32I-NEXT:    bnez s2, .LBB3_3
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    srli a0, a0, 27
-; RV32I-NEXT:    add a0, s4, a0
-; RV32I-NEXT:    lbu a1, 0(a0)
+; RV32I-NEXT:    li a0, 32
+; RV32I-NEXT:    beqz s0, .LBB3_4
 ; RV32I-NEXT:  .LBB3_2:
-; RV32I-NEXT:    bnez s0, .LBB3_4
-; RV32I-NEXT:  # %bb.3:
-; RV32I-NEXT:    addi a0, a1, 32
-; RV32I-NEXT:    j .LBB3_5
-; RV32I-NEXT:  .LBB3_4:
 ; RV32I-NEXT:    srli a0, s1, 27
 ; RV32I-NEXT:    add a0, s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
+; RV32I-NEXT:    j .LBB3_5
+; RV32I-NEXT:  .LBB3_3:
+; RV32I-NEXT:    srli a0, a0, 27
+; RV32I-NEXT:    add a0, s4, a0
+; RV32I-NEXT:    lbu a0, 0(a0)
+; RV32I-NEXT:    bnez s0, .LBB3_2
+; RV32I-NEXT:  .LBB3_4:
+; RV32I-NEXT:    addi a0, a0, 32
 ; RV32I-NEXT:  .LBB3_5:
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    ret
 ;
 ; RV32M-LABEL: test_cttz_i64:
 ; RV32M:       # %bb.0:
 ; RV32M-NEXT:    lui a2, 30667
 ; RV32M-NEXT:    addi a2, a2, 1329
 ; RV32M-NEXT:    lui a3, %hi(.LCPI3_0)
 ; RV32M-NEXT:    addi a3, a3, %lo(.LCPI3_0)
-; RV32M-NEXT:    li a4, 32
-; RV32M-NEXT:    beqz a1, .LBB3_2
+; RV32M-NEXT:    bnez a1, .LBB3_3
 ; RV32M-NEXT:  # %bb.1:
-; RV32M-NEXT:    neg a4, a1
-; RV32M-NEXT:    and a1, a1, a4
-; RV32M-NEXT:    mul a1, a1, a2
-; RV32M-NEXT:    srli a1, a1, 27
-; RV32M-NEXT:    add a1, a3, a1
-; RV32M-NEXT:    lbu a4, 0(a1)
+; RV32M-NEXT:    li a1, 32
+; RV32M-NEXT:    beqz a0, .LBB3_4
 ; RV32M-NEXT:  .LBB3_2:
-; RV32M-NEXT:    bnez a0, .LBB3_4
-; RV32M-NEXT:  # %bb.3:
-; RV32M-NEXT:    addi a0, a4, 32
-; RV32M-NEXT:    li a1, 0
-; RV32M-NEXT:    ret
-; RV32M-NEXT:  .LBB3_4:
 ; RV32M-NEXT:    neg a1, a0
 ; RV32M-NEXT:    and a0, a0, a1
 ; RV32M-NEXT:    mul a0, a0, a2
 ; RV32M-NEXT:    srli a0, a0, 27
 ; RV32M-NEXT:    add a0, a3, a0
 ; RV32M-NEXT:    lbu a0, 0(a0)
 ; RV32M-NEXT:    li a1, 0
 ; RV32M-NEXT:    ret
+; RV32M-NEXT:  .LBB3_3:
+; RV32M-NEXT:    neg a4, a1
+; RV32M-NEXT:    and a1, a1, a4
+; RV32M-NEXT:    mul a1, a1, a2
+; RV32M-NEXT:    srli a1, a1, 27
+; RV32M-NEXT:    add a1, a3, a1
+; RV32M-NEXT:    lbu a1, 0(a1)
+; RV32M-NEXT:    bnez a0, .LBB3_2
+; RV32M-NEXT:  .LBB3_4:
+; RV32M-NEXT:    addi a0, a1, 32
+; RV32M-NEXT:    li a1, 0
+; RV32M-NEXT:    ret
 ;
 ; RV64M-LABEL: test_cttz_i64:
 ; RV64M:       # %bb.0:
 ; RV64M-NEXT:    beqz a0, .LBB3_2
 ; RV64M-NEXT:  # %bb.1: # %cond.false
 ; RV64M-NEXT:    lui a1, %hi(.LCPI3_0)
 ; RV64M-NEXT:    ld a1, %lo(.LCPI3_0)(a1)
 ; RV64M-NEXT:    neg a2, a0

llvm/test/CodeGen/RISCV/double-convert-strict.ll

 }
 declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 define i32 @fcvt_wu_d_multiple_use(double %x, i32* %y) nounwind {
 ; CHECKIFD-LABEL: fcvt_wu_d_multiple_use:
 ; CHECKIFD:       # %bb.0:
-; CHECKIFD-NEXT:    fcvt.wu.d a1, fa0, rtz
-; CHECKIFD-NEXT:    li a0, 1
-; CHECKIFD-NEXT:    beqz a1, .LBB4_2
+; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rtz
+; CHECKIFD-NEXT:    bnez a0, .LBB4_2
 ; CHECKIFD-NEXT:  # %bb.1:
-; CHECKIFD-NEXT:    mv a0, a1
+; CHECKIFD-NEXT:    li a0, 1
 ; CHECKIFD-NEXT:  .LBB4_2:
 ; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_d_multiple_use:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunsdfsi@plt
-; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    li a0, 1
-; RV32I-NEXT:    beqz a1, .LBB4_2
+; RV32I-NEXT:    bnez a0, .LBB4_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:    li a0, 1
 ; RV32I-NEXT:  .LBB4_2:
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_wu_d_multiple_use:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __fixunsdfsi@plt
-; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    li a0, 1
-; RV64I-NEXT:    beqz a1, .LBB4_2
+; RV64I-NEXT:    bnez a0, .LBB4_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    mv a0, a1
+; RV64I-NEXT:    li a0, 1
 ; RV64I-NEXT:  .LBB4_2:
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %a = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %x, metadata !"fpexcept.strict") strictfp
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c

llvm/test/CodeGen/RISCV/double-convert.ll

 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lui a3, 794112
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gedf2@plt
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __fixdfsi@plt
-; RV32I-NEXT:    lui a1, 524288
-; RV32I-NEXT:    lui s4, 524288
-; RV32I-NEXT:    bltz s3, .LBB3_2
+; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    lui a0, 524288
+; RV32I-NEXT:    bgez s4, .LBB3_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    lui s3, 524288
 ; RV32I-NEXT:  .LBB3_2: # %start
 ; RV32I-NEXT:    blez s2, .LBB3_4
-; RV32I-NEXT:  # %bb.3:
-; RV32I-NEXT:    addi s4, a1, -1
+; RV32I-NEXT:  # %bb.3: # %start
+; RV32I-NEXT:    addi s3, a0, -1
 ; RV32I-NEXT:  .LBB3_4: # %start
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    mv a2, s1
 ; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:    call __unorddf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a0, a0, s4
+; RV32I-NEXT:    and a0, a0, s3
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_w_d_sat:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s3, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    li a0, -497
 ; RV64I-NEXT:    slli a1, a0, 53
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gedf2@plt
-; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __fixdfdi@plt
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lui s3, 524288
-; RV64I-NEXT:    lui s2, 524288
-; RV64I-NEXT:    bltz s1, .LBB3_2
+; RV64I-NEXT:    bgez s2, .LBB3_2
 ; RV64I-NEXT:  # %bb.1: # %start
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    lui s1, 524288
 ; RV64I-NEXT:  .LBB3_2: # %start
 ; RV64I-NEXT:    li a0, 527
 ; RV64I-NEXT:    slli a0, a0, 31
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    slli a1, a0, 22
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gtdf2@plt
 ; RV64I-NEXT:    blez a0, .LBB3_4
-; RV64I-NEXT:  # %bb.3:
-; RV64I-NEXT:    addiw s2, s3, -1
+; RV64I-NEXT:  # %bb.3: # %start
+; RV64I-NEXT:    addiw s1, s3, -1
 ; RV64I-NEXT:  .LBB3_4: # %start
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    call __unorddf2@plt
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    and a0, a0, s2
+; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 start:
; RV64I-NEXT:    ret
   ret i32 %1
 }
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 define i32 @fcvt_wu_d_multiple_use(double %x, i32* %y) nounwind {
 ; CHECKIFD-LABEL: fcvt_wu_d_multiple_use:
 ; CHECKIFD:       # %bb.0:
-; CHECKIFD-NEXT:    fcvt.wu.d a1, fa0, rtz
-; CHECKIFD-NEXT:    li a0, 1
-; CHECKIFD-NEXT:    beqz a1, .LBB5_2
+; CHECKIFD-NEXT:    fcvt.wu.d a0, fa0, rtz
+; CHECKIFD-NEXT:    bnez a0, .LBB5_2
 ; CHECKIFD-NEXT:  # %bb.1:
-; CHECKIFD-NEXT:    mv a0, a1
+; CHECKIFD-NEXT:    li a0, 1
 ; CHECKIFD-NEXT:  .LBB5_2:
 ; CHECKIFD-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_d_multiple_use:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunsdfsi@plt
-; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    li a0, 1
-; RV32I-NEXT:    beqz a1, .LBB5_2
+; RV32I-NEXT:    bnez a0, .LBB5_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:    li a0, 1
 ; RV32I-NEXT:  .LBB5_2:
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_wu_d_multiple_use:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __fixunsdfsi@plt
-; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    li a0, 1
-; RV64I-NEXT:    beqz a1, .LBB5_2
+; RV64I-NEXT:    bnez a0, .LBB5_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    mv a0, a1
+; RV64I-NEXT:    li a0, 1
 ; RV64I-NEXT:  .LBB5_2:
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %a = fptoui double %x to i32
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c

 ; RV64I-NEXT:    call __fixunsdfdi@plt
 ; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    li a0, 1055
 ; RV64I-NEXT:    slli a0, a0, 31
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    slli a1, a0, 21
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __gtdf2@plt
-; RV64I-NEXT:    bgtz a0, .LBB6_2
+; RV64I-NEXT:    blez a0, .LBB6_2
 ; RV64I-NEXT:  # %bb.1: # %start
+; RV64I-NEXT:    li a0, -1
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    j .LBB6_3
+; RV64I-NEXT:  .LBB6_2:
 ; RV64I-NEXT:    slti a0, s0, 0
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    and a0, a0, s1
-; RV64I-NEXT:    j .LBB6_3
-; RV64I-NEXT:  .LBB6_2:
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:  .LBB6_3: # %start
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
 start:

 ; RV32I-NEXT:    mv a3, s2
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    lui a3, 802304
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gedf2@plt
-; RV32I-NEXT:    mv s5, a0
+; RV32I-NEXT:    mv s6, a0
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __fixdfdi@plt
 ; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s5, a1
 ; RV32I-NEXT:    lui a0, 524288
-; RV32I-NEXT:    lui s6, 524288
-; RV32I-NEXT:    bltz s5, .LBB12_2
+; RV32I-NEXT:    bgez s6, .LBB12_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv s6, a1
+; RV32I-NEXT:    lui s5, 524288
 ; RV32I-NEXT:  .LBB12_2: # %start
 ; RV32I-NEXT:    blez s4, .LBB12_4
-; RV32I-NEXT:  # %bb.3:
-; RV32I-NEXT:    addi s6, a0, -1
+; RV32I-NEXT:  # %bb.3: # %start
+; RV32I-NEXT:    addi s5, a0, -1
 ; RV32I-NEXT:  .LBB12_4: # %start
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    mv a2, s1
 ; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:    call __unorddf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and s4, a0, s6
+; RV32I-NEXT:    and s4, a0, s5
 ; RV32I-NEXT:    lui a3, 802304
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    addi a0, a0, -1
 ; RV32I-NEXT:    and s3, a0, s3

 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    li a0, -481
 ; RV64I-NEXT:    slli a1, a0, 53
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gedf2@plt
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __fixdfdi@plt
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    li s3, -1
-; RV64I-NEXT:    bltz s2, .LBB12_2
+; RV64I-NEXT:    bgez s2, .LBB12_2
 ; RV64I-NEXT:  # %bb.1: # %start
-; RV64I-NEXT:    mv s1, a0
-; RV64I-NEXT:    j .LBB12_3
-; RV64I-NEXT:  .LBB12_2:
 ; RV64I-NEXT:    slli s1, s3, 63
-; RV64I-NEXT:  .LBB12_3: # %start
+; RV64I-NEXT:  .LBB12_2: # %start
 ; RV64I-NEXT:    li a0, 543
 ; RV64I-NEXT:    slli a0, a0, 53
 ; RV64I-NEXT:    addi a1, a0, -1
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gtdf2@plt
-; RV64I-NEXT:    blez a0, .LBB12_5
-; RV64I-NEXT:  # %bb.4:
+; RV64I-NEXT:    blez a0, .LBB12_4
+; RV64I-NEXT:  # %bb.3: # %start
 ; RV64I-NEXT:    srli s1, s3, 1
-; RV64I-NEXT:  .LBB12_5: # %start
+; RV64I-NEXT:  .LBB12_4: # %start
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    call __unorddf2@plt
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload

 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lui a3, 790016
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gedf2@plt
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __fixdfsi@plt
-; RV32I-NEXT:    lui s4, 1048568
-; RV32I-NEXT:    bltz s3, .LBB26_2
+; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    bgez s4, .LBB26_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    lui s3, 1048568
 ; RV32I-NEXT:  .LBB26_2: # %start
 ; RV32I-NEXT:    blez s2, .LBB26_4
-; RV32I-NEXT:  # %bb.3:
+; RV32I-NEXT:  # %bb.3: # %start
 ; RV32I-NEXT:    lui a0, 8
-; RV32I-NEXT:    addi s4, a0, -1
+; RV32I-NEXT:    addi s3, a0, -1
 ; RV32I-NEXT:  .LBB26_4: # %start
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    mv a2, s1
 ; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:    call __unorddf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a0, a0, s4
+; RV32I-NEXT:    and a0, a0, s3
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srai a0, a0, 16
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_w_s_sat_i16:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -32
 ; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    li a0, -505
 ; RV64I-NEXT:    slli a1, a0, 53
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gedf2@plt
-; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __fixdfdi@plt
-; RV64I-NEXT:    lui s2, 1048568
-; RV64I-NEXT:    bltz s1, .LBB26_2
+; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    bgez s2, .LBB26_2
 ; RV64I-NEXT:  # %bb.1: # %start
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    lui s1, 1048568
 ; RV64I-NEXT:  .LBB26_2: # %start
 ; RV64I-NEXT:    lui a0, 4152
 ; RV64I-NEXT:    addiw a0, a0, -1
 ; RV64I-NEXT:    slli a1, a0, 38
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gtdf2@plt
 ; RV64I-NEXT:    blez a0, .LBB26_4
-; RV64I-NEXT:  # %bb.3:
+; RV64I-NEXT:  # %bb.3: # %start
 ; RV64I-NEXT:    lui a0, 8
-; RV64I-NEXT:    addiw s2, a0, -1
+; RV64I-NEXT:    addiw s1, a0, -1
 ; RV64I-NEXT:  .LBB26_4: # %start
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    call __unorddf2@plt
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    and a0, a0, s2
+; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srai a0, a0, 48
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret

 ; RV32I-NEXT:    li a3, 0
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s1
 ; RV32I-NEXT:    call __fixunsdfsi@plt
 ; RV32I-NEXT:    lui a1, 16
 ; RV32I-NEXT:    addi a1, a1, -1
-; RV32I-NEXT:    mv a2, a1
-; RV32I-NEXT:    bgtz s3, .LBB28_2
+; RV32I-NEXT:    blez s3, .LBB28_2
 ; RV32I-NEXT:  # %bb.1: # %start
+; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:    j .LBB28_3
+; RV32I-NEXT:  .LBB28_2:
 ; RV32I-NEXT:    slti a2, s0, 0
 ; RV32I-NEXT:    addi a2, a2, -1
-; RV32I-NEXT:    and a2, a2, a0
-; RV32I-NEXT:  .LBB28_2: # %start
-; RV32I-NEXT:    and a0, a2, a1
+; RV32I-NEXT:    and a0, a2, a0
+; RV32I-NEXT:  .LBB28_3: # %start
+; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;

 ; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lui a0, 8312
 ; RV64I-NEXT:    addiw a0, a0, -1
 ; RV64I-NEXT:    slli a1, a0, 37
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __gtdf2@plt
 ; RV64I-NEXT:    lui a1, 16
 ; RV64I-NEXT:    addiw a1, a1, -1
-; RV64I-NEXT:    mv a2, a1
-; RV64I-NEXT:    bgtz a0, .LBB28_2
+; RV64I-NEXT:    blez a0, .LBB28_2
 ; RV64I-NEXT:  # %bb.1: # %start
+; RV64I-NEXT:    mv a0, a1
+; RV64I-NEXT:    j .LBB28_3
+; RV64I-NEXT:  .LBB28_2:
 ; RV64I-NEXT:    slti a0, s0, 0
 ; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    and a2, a0, s1
-; RV64I-NEXT:  .LBB28_2: # %start
-; RV64I-NEXT:    and a0, a2, a1
+; RV64I-NEXT:    and a0, a0, s1
+; RV64I-NEXT:  .LBB28_3: # %start
+; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i16 @llvm.fptoui.sat.i16.f64(double %a)

 ; RV32I-LABEL: fcvt_w_s_sat_i8:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1
 ; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lui a3, 263676
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lui a3, 787968
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gedf2@plt
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __fixdfsi@plt
-; RV32I-NEXT:    li a1, -128
-; RV32I-NEXT:    bltz s3, .LBB30_2
+; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    bgez s4, .LBB30_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv a1, a0
+; RV32I-NEXT:    li s3, -128
 ; RV32I-NEXT:  .LBB30_2: # %start
-; RV32I-NEXT:    li s3, 127
-; RV32I-NEXT:    bgtz s2, .LBB30_4
+; RV32I-NEXT:    blez s2, .LBB30_4
 ; RV32I-NEXT:  # %bb.3: # %start
-; RV32I-NEXT:    mv s3, a1
+; RV32I-NEXT:    li s3, 127
 ; RV32I-NEXT:  .LBB30_4: # %start
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    mv a2, s1
 ; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:    call __unorddf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
 ; RV32I-NEXT:    and a0, a0, s3
 ; RV32I-NEXT:    slli a0, a0, 24
 ; RV32I-NEXT:    srai a0, a0, 24
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_w_s_sat_i8:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -32
 ; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    li a0, -509
 ; RV64I-NEXT:    slli a1, a0, 53
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gedf2@plt
-; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __fixdfdi@plt
-; RV64I-NEXT:    li s2, -128
-; RV64I-NEXT:    bltz s1, .LBB30_2
+; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    bgez s2, .LBB30_2
 ; RV64I-NEXT:  # %bb.1: # %start
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    li s1, -128
 ; RV64I-NEXT:  .LBB30_2: # %start
 ; RV64I-NEXT:    lui a0, 65919
 ; RV64I-NEXT:    slli a1, a0, 34
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gtdf2@plt
-; RV64I-NEXT:    li s1, 127
-; RV64I-NEXT:    bgtz a0, .LBB30_4
+; RV64I-NEXT:    blez a0, .LBB30_4
 ; RV64I-NEXT:  # %bb.3: # %start
-; RV64I-NEXT:    mv s1, s2
+; RV64I-NEXT:    li s1, 127
 ; RV64I-NEXT:  .LBB30_4: # %start
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    call __unorddf2@plt
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:    slli a0, a0, 56

 ; RV32I-NEXT:    mv a1, s1
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    li a3, 0
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s1
 ; RV32I-NEXT:    call __fixunsdfsi@plt
-; RV32I-NEXT:    li a1, 255
-; RV32I-NEXT:    bgtz s3, .LBB32_2
+; RV32I-NEXT:    blez s3, .LBB32_2
 ; RV32I-NEXT:  # %bb.1: # %start
+; RV32I-NEXT:    li a0, 255
+; RV32I-NEXT:    j .LBB32_3
+; RV32I-NEXT:  .LBB32_2:
 ; RV32I-NEXT:    slti a1, s0, 0
 ; RV32I-NEXT:    addi a1, a1, -1
-; RV32I-NEXT:    and a1, a1, a0
-; RV32I-NEXT:  .LBB32_2: # %start
-; RV32I-NEXT:    andi a0, a1, 255
+; RV32I-NEXT:    and a0, a1, a0
+; RV32I-NEXT:  .LBB32_3: # %start
+; RV32I-NEXT:    andi a0, a0, 255
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;

 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __fixunsdfdi@plt
 ; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lui a0, 131967
 ; RV64I-NEXT:    slli a1, a0, 33
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __gtdf2@plt
-; RV64I-NEXT:    li a1, 255
-; RV64I-NEXT:    bgtz a0, .LBB32_2
+; RV64I-NEXT:    blez a0, .LBB32_2
 ; RV64I-NEXT:  # %bb.1: # %start
+; RV64I-NEXT:    li a0, 255
+; RV64I-NEXT:    j .LBB32_3
+; RV64I-NEXT:  .LBB32_2:
 ; RV64I-NEXT:    slti a0, s0, 0
 ; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    and a1, a0, s1
-; RV64I-NEXT:  .LBB32_2: # %start
-; RV64I-NEXT:    andi a0, a1, 255
+; RV64I-NEXT:    and a0, a0, s1
+; RV64I-NEXT:  .LBB32_3: # %start
+; RV64I-NEXT:    andi a0, a0, 255
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i8 @llvm.fptoui.sat.i8.f64(double %a)

 ; RV64I-NEXT:    call __fixunsdfdi@plt
 ; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    li a0, 1055
 ; RV64I-NEXT:    slli a0, a0, 31
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    slli a1, a0, 21
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __gtdf2@plt
-; RV64I-NEXT:    bgtz a0, .LBB33_2
+; RV64I-NEXT:    blez a0, .LBB33_2
 ; RV64I-NEXT:  # %bb.1: # %start
+; RV64I-NEXT:    li a0, -1
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    j .LBB33_3
+; RV64I-NEXT:  .LBB33_2:
 ; RV64I-NEXT:    slti a0, s0, 0
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    and a0, a0, s1
-; RV64I-NEXT:    j .LBB33_3
-; RV64I-NEXT:  .LBB33_2:
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:  .LBB33_3: # %start
 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32

 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lui a3, 794112
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gedf2@plt
-; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __fixdfsi@plt
-; RV32I-NEXT:    lui a1, 524288
-; RV32I-NEXT:    lui s4, 524288
-; RV32I-NEXT:    bltz s3, .LBB34_2
+; RV32I-NEXT:    mv s3, a0
+; RV32I-NEXT:    lui a0, 524288
+; RV32I-NEXT:    bgez s4, .LBB34_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv s4, a0
+; RV32I-NEXT:    lui s3, 524288
 ; RV32I-NEXT:  .LBB34_2: # %start
 ; RV32I-NEXT:    blez s2, .LBB34_4
-; RV32I-NEXT:  # %bb.3:
-; RV32I-NEXT:    addi s4, a1, -1
+; RV32I-NEXT:  # %bb.3: # %start
+; RV32I-NEXT:    addi s3, a0, -1
 ; RV32I-NEXT:  .LBB34_4: # %start
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    mv a2, s1
 ; RV32I-NEXT:    mv a3, s0
 ; RV32I-NEXT:    call __unorddf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a0, a0, s4
+; RV32I-NEXT:    and a0, a0, s3
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_w_d_sat_sext:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s3, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    li a0, -497
 ; RV64I-NEXT:    slli a1, a0, 53
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gedf2@plt
-; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __fixdfdi@plt
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lui s3, 524288
-; RV64I-NEXT:    lui s2, 524288
-; RV64I-NEXT:    bltz s1, .LBB34_2
+; RV64I-NEXT:    bgez s2, .LBB34_2
 ; RV64I-NEXT:  # %bb.1: # %start
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    lui s1, 524288
 ; RV64I-NEXT:  .LBB34_2: # %start
 ; RV64I-NEXT:    li a0, 527
 ; RV64I-NEXT:    slli a0, a0, 31
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    slli a1, a0, 22
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gtdf2@plt
 ; RV64I-NEXT:    blez a0, .LBB34_4
-; RV64I-NEXT:  # %bb.3:
-; RV64I-NEXT:    addiw s2, s3, -1
+; RV64I-NEXT:  # %bb.3: # %start
+; RV64I-NEXT:    addiw s1, s3, -1
 ; RV64I-NEXT:  .LBB34_4: # %start
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    call __unorddf2@plt
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    and a0, a0, s2
+; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptosi.sat.i32.f64(double %a)
   ret i32 %0
 }

llvm/test/CodeGen/RISCV/float-convert-strict.ll

 }
 declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata)
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind {
 ; CHECKIF-LABEL: fcvt_wu_s_multiple_use:
 ; CHECKIF:       # %bb.0:
-; CHECKIF-NEXT:    fcvt.wu.s a1, fa0, rtz
-; CHECKIF-NEXT:    li a0, 1
-; CHECKIF-NEXT:    beqz a1, .LBB2_2
+; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rtz
+; CHECKIF-NEXT:    bnez a0, .LBB2_2
 ; CHECKIF-NEXT:  # %bb.1:
-; CHECKIF-NEXT:    mv a0, a1
+; CHECKIF-NEXT:    li a0, 1
 ; CHECKIF-NEXT:  .LBB2_2:
 ; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s_multiple_use:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfsi@plt
-; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    li a0, 1
-; RV32I-NEXT:    beqz a1, .LBB2_2
+; RV32I-NEXT:    bnez a0, .LBB2_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:    li a0, 1
 ; RV32I-NEXT:  .LBB2_2:
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_wu_s_multiple_use:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __fixunssfsi@plt
-; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    li a0, 1
-; RV64I-NEXT:    beqz a1, .LBB2_2
+; RV64I-NEXT:    bnez a0, .LBB2_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    mv a0, a1
+; RV64I-NEXT:    li a0, 1
 ; RV64I-NEXT:  .LBB2_2:
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %a = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %x, metadata !"fpexcept.strict") strictfp
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c

llvm/test/CodeGen/RISCV/float-convert.ll

 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    lui a1, 847872
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __fixsfsi@plt
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lui s3, 524288
-; RV32I-NEXT:    lui s2, 524288
-; RV32I-NEXT:    bltz s1, .LBB1_2
+; RV32I-NEXT:    bgez s2, .LBB1_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    lui s1, 524288
 ; RV32I-NEXT:  .LBB1_2: # %start
 ; RV32I-NEXT:    lui a0, 323584
 ; RV32I-NEXT:    addi a1, a0, -1
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    blez a0, .LBB1_4
-; RV32I-NEXT:  # %bb.3:
-; RV32I-NEXT:    addi s2, s3, -1
+; RV32I-NEXT:  # %bb.3: # %start
+; RV32I-NEXT:    addi s1, s3, -1
 ; RV32I-NEXT:  .LBB1_4: # %start
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a0, a0, s2
+; RV32I-NEXT:    and a0, a0, s1
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_w_s_sat:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s3, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    lui a1, 847872
 ; RV64I-NEXT:    call __gesf2@plt
-; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __fixsfdi@plt
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lui s3, 524288
-; RV64I-NEXT:    lui s2, 524288
-; RV64I-NEXT:    bltz s1, .LBB1_2
+; RV64I-NEXT:    bgez s2, .LBB1_2
 ; RV64I-NEXT:  # %bb.1: # %start
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    lui s1, 524288
 ; RV64I-NEXT:  .LBB1_2: # %start
 ; RV64I-NEXT:    lui a0, 323584
 ; RV64I-NEXT:    addiw a1, a0, -1
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gtsf2@plt
 ; RV64I-NEXT:    blez a0, .LBB1_4
-; RV64I-NEXT:  # %bb.3:
-; RV64I-NEXT:    addiw s2, s3, -1
+; RV64I-NEXT:  # %bb.3: # %start
+; RV64I-NEXT:    addiw s1, s3, -1
 ; RV64I-NEXT:  .LBB1_4: # %start
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    call __unordsf2@plt
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    and a0, a0, s2
+; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 start:
; RV64I-NEXT:    ret
   ret i32 %1
 }
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) nounwind {
 ; CHECKIF-LABEL: fcvt_wu_s_multiple_use:
 ; CHECKIF:       # %bb.0:
-; CHECKIF-NEXT:    fcvt.wu.s a1, fa0, rtz
-; CHECKIF-NEXT:    li a0, 1
-; CHECKIF-NEXT:    beqz a1, .LBB3_2
+; CHECKIF-NEXT:    fcvt.wu.s a0, fa0, rtz
+; CHECKIF-NEXT:    bnez a0, .LBB3_2
 ; CHECKIF-NEXT:  # %bb.1:
-; CHECKIF-NEXT:    mv a0, a1
+; CHECKIF-NEXT:    li a0, 1
 ; CHECKIF-NEXT:  .LBB3_2:
 ; CHECKIF-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_s_multiple_use:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __fixunssfsi@plt
-; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    li a0, 1
-; RV32I-NEXT:    beqz a1, .LBB3_2
+; RV32I-NEXT:    bnez a0, .LBB3_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:    li a0, 1
 ; RV32I-NEXT:  .LBB3_2:
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_wu_s_multiple_use:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    call __fixunssfsi@plt
-; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    li a0, 1
-; RV64I-NEXT:    beqz a1, .LBB3_2
+; RV64I-NEXT:    bnez a0, .LBB3_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    mv a0, a1
+; RV64I-NEXT:    li a0, 1
 ; RV64I-NEXT:  .LBB3_2:
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %a = fptoui float %x to i32
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c

 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __fixunssfdi@plt
 ; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lui a0, 325632
 ; RV64I-NEXT:    addiw a1, a0, -1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __gtsf2@plt
-; RV64I-NEXT:    bgtz a0, .LBB4_2
+; RV64I-NEXT:    blez a0, .LBB4_2
 ; RV64I-NEXT:  # %bb.1: # %start
+; RV64I-NEXT:    li a0, -1
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    j .LBB4_3
+; RV64I-NEXT:  .LBB4_2:
 ; RV64I-NEXT:    slti a0, s0, 0
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    and a0, a0, s1
-; RV64I-NEXT:    j .LBB4_3
-; RV64I-NEXT:  .LBB4_2:
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:  .LBB4_3: # %start
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
 start:

 ; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    lui a1, 913408
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __fixsfdi@plt
 ; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    mv s3, a1
 ; RV32I-NEXT:    lui s4, 524288
-; RV32I-NEXT:    lui s3, 524288
-; RV32I-NEXT:    bltz s2, .LBB12_2
+; RV32I-NEXT:    bgez s2, .LBB12_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv s3, a1
+; RV32I-NEXT:    lui s3, 524288
 ; RV32I-NEXT:  .LBB12_2: # %start
 ; RV32I-NEXT:    lui a0, 389120
 ; RV32I-NEXT:    addi s2, a0, -1
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    blez a0, .LBB12_4
-; RV32I-NEXT:  # %bb.3:
+; RV32I-NEXT:  # %bb.3: # %start
 ; RV32I-NEXT:    addi s3, s4, -1
 ; RV32I-NEXT:  .LBB12_4: # %start
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
 ; RV32I-NEXT:    and s3, a0, s3

 ; RV64I-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s3, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    lui a1, 913408
 ; RV64I-NEXT:    call __gesf2@plt
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __fixsfdi@plt
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    li s3, -1
-; RV64I-NEXT:    bltz s2, .LBB12_2
+; RV64I-NEXT:    bgez s2, .LBB12_2
 ; RV64I-NEXT:  # %bb.1: # %start
-; RV64I-NEXT:    mv s1, a0
-; RV64I-NEXT:    j .LBB12_3
-; RV64I-NEXT:  .LBB12_2:
 ; RV64I-NEXT:    slli s1, s3, 63
-; RV64I-NEXT:  .LBB12_3: # %start
+; RV64I-NEXT:  .LBB12_2: # %start
 ; RV64I-NEXT:    lui a0, 389120
 ; RV64I-NEXT:    addiw a1, a0, -1
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gtsf2@plt
-; RV64I-NEXT:    blez a0, .LBB12_5
-; RV64I-NEXT:  # %bb.4:
+; RV64I-NEXT:    blez a0, .LBB12_4
+; RV64I-NEXT:  # %bb.3: # %start
 ; RV64I-NEXT:    srli s1, s3, 1
-; RV64I-NEXT:  .LBB12_5: # %start
+; RV64I-NEXT:  .LBB12_4: # %start
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    call __unordsf2@plt
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload

 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    lui a1, 815104
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __fixsfsi@plt
-; RV32I-NEXT:    lui s2, 1048568
-; RV32I-NEXT:    bltz s1, .LBB24_2
+; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    bgez s2, .LBB24_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    lui s1, 1048568
 ; RV32I-NEXT:  .LBB24_2: # %start
 ; RV32I-NEXT:    lui a0, 290816
 ; RV32I-NEXT:    addi a1, a0, -512
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    blez a0, .LBB24_4
-; RV32I-NEXT:  # %bb.3:
+; RV32I-NEXT:  # %bb.3: # %start
 ; RV32I-NEXT:    lui a0, 8
-; RV32I-NEXT:    addi s2, a0, -1
+; RV32I-NEXT:    addi s1, a0, -1
 ; RV32I-NEXT:  .LBB24_4: # %start
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a0, a0, s2
+; RV32I-NEXT:    and a0, a0, s1
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srai a0, a0, 16
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_w_s_sat_i16:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -32
 ; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    lui a1, 815104
 ; RV64I-NEXT:    call __gesf2@plt
-; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __fixsfdi@plt
-; RV64I-NEXT:    lui s2, 1048568
-; RV64I-NEXT:    bltz s1, .LBB24_2
+; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    bgez s2, .LBB24_2
 ; RV64I-NEXT:  # %bb.1: # %start
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    lui s1, 1048568
 ; RV64I-NEXT:  .LBB24_2: # %start
 ; RV64I-NEXT:    lui a0, 290816
 ; RV64I-NEXT:    addiw a1, a0, -512
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gtsf2@plt
 ; RV64I-NEXT:    blez a0, .LBB24_4
-; RV64I-NEXT:  # %bb.3:
+; RV64I-NEXT:  # %bb.3: # %start
 ; RV64I-NEXT:    lui a0, 8
-; RV64I-NEXT:    addiw s2, a0, -1
+; RV64I-NEXT:    addiw s1, a0, -1
 ; RV64I-NEXT:  .LBB24_4: # %start
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    call __unordsf2@plt
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    and a0, a0, s2
+; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srai a0, a0, 48
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret

 ; RV32I-NEXT:    call __fixunssfsi@plt
 ; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lui a0, 292864
 ; RV32I-NEXT:    addi a1, a0, -256
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    lui a1, 16
 ; RV32I-NEXT:    addi a1, a1, -1
-; RV32I-NEXT:    mv a2, a1
-; RV32I-NEXT:    bgtz a0, .LBB26_2
+; RV32I-NEXT:    blez a0, .LBB26_2
 ; RV32I-NEXT:  # %bb.1: # %start
+; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:    j .LBB26_3
+; RV32I-NEXT:  .LBB26_2:
 ; RV32I-NEXT:    slti a0, s0, 0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a2, a0, s1
-; RV32I-NEXT:  .LBB26_2: # %start
-; RV32I-NEXT:    and a0, a2, a1
+; RV32I-NEXT:    and a0, a0, s1
+; RV32I-NEXT:  .LBB26_3: # %start
+; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_wu_s_sat_i16:

 ; RV64I-NEXT:    call __fixunssfdi@plt
 ; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lui a0, 292864
 ; RV64I-NEXT:    addiw a1, a0, -256
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __gtsf2@plt
 ; RV64I-NEXT:    lui a1, 16
 ; RV64I-NEXT:    addiw a1, a1, -1
-; RV64I-NEXT:    mv a2, a1
-; RV64I-NEXT:    bgtz a0, .LBB26_2
+; RV64I-NEXT:    blez a0, .LBB26_2
 ; RV64I-NEXT:  # %bb.1: # %start
+; RV64I-NEXT:    mv a0, a1
+; RV64I-NEXT:    j .LBB26_3
+; RV64I-NEXT:  .LBB26_2:
 ; RV64I-NEXT:    slti a0, s0, 0
 ; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    and a2, a0, s1
-; RV64I-NEXT:  .LBB26_2: # %start
-; RV64I-NEXT:    and a0, a2, a1
+; RV64I-NEXT:    and a0, a0, s1
+; RV64I-NEXT:  .LBB26_3: # %start
+; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i16 @llvm.fptoui.sat.i16.f32(float %a)

 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    lui a1, 798720
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __fixsfsi@plt
-; RV32I-NEXT:    li s2, -128
-; RV32I-NEXT:    bltz s1, .LBB28_2
+; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    bgez s2, .LBB28_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    li s1, -128
 ; RV32I-NEXT:  .LBB28_2: # %start
 ; RV32I-NEXT:    lui a1, 274400
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    li s1, 127
-; RV32I-NEXT:    bgtz a0, .LBB28_4
+; RV32I-NEXT:    blez a0, .LBB28_4
 ; RV32I-NEXT:  # %bb.3: # %start
-; RV32I-NEXT:    mv s1, s2
+; RV32I-NEXT:    li s1, 127
 ; RV32I-NEXT:  .LBB28_4: # %start
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
 ; RV32I-NEXT:    and a0, a0, s1
 ; RV32I-NEXT:    slli a0, a0, 24

 ; RV64I-NEXT:    addi sp, sp, -32
 ; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    lui a1, 798720
 ; RV64I-NEXT:    call __gesf2@plt
-; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __fixsfdi@plt
-; RV64I-NEXT:    li s2, -128
-; RV64I-NEXT:    bltz s1, .LBB28_2
+; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    bgez s2, .LBB28_2
 ; RV64I-NEXT:  # %bb.1: # %start
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    li s1, -128
 ; RV64I-NEXT:  .LBB28_2: # %start
 ; RV64I-NEXT:    lui a1, 274400
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gtsf2@plt
-; RV64I-NEXT:    li s1, 127
-; RV64I-NEXT:    bgtz a0, .LBB28_4
+; RV64I-NEXT:    blez a0, .LBB28_4
 ; RV64I-NEXT:  # %bb.3: # %start
-; RV64I-NEXT:    mv s1, s2
+; RV64I-NEXT:    li s1, 127
 ; RV64I-NEXT:  .LBB28_4: # %start
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    call __unordsf2@plt
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:    slli a0, a0, 56

 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    call __fixunssfsi@plt
 ; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lui a1, 276464
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    li a1, 255
-; RV32I-NEXT:    bgtz a0, .LBB30_2
+; RV32I-NEXT:    blez a0, .LBB30_2
 ; RV32I-NEXT:  # %bb.1: # %start
+; RV32I-NEXT:    li a0, 255
+; RV32I-NEXT:    j .LBB30_3
+; RV32I-NEXT:  .LBB30_2:
 ; RV32I-NEXT:    slti a0, s0, 0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a1, a0, s1
-; RV32I-NEXT:  .LBB30_2: # %start
-; RV32I-NEXT:    andi a0, a1, 255
+; RV32I-NEXT:    and a0, a0, s1
+; RV32I-NEXT:  .LBB30_3: # %start
+; RV32I-NEXT:    andi a0, a0, 255
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_wu_s_sat_i8:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -32
 ; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    li a1, 0
 ; RV64I-NEXT:    call __gesf2@plt
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __fixunssfdi@plt
 ; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lui a1, 276464
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __gtsf2@plt
-; RV64I-NEXT:    li a1, 255
-; RV64I-NEXT:    bgtz a0, .LBB30_2
+; RV64I-NEXT:    blez a0, .LBB30_2
 ; RV64I-NEXT:  # %bb.1: # %start
+; RV64I-NEXT:    li a0, 255
+; RV64I-NEXT:    j .LBB30_3
+; RV64I-NEXT:  .LBB30_2:
 ; RV64I-NEXT:    slti a0, s0, 0
 ; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    and a1, a0, s1
-; RV64I-NEXT:  .LBB30_2: # %start
-; RV64I-NEXT:    andi a0, a1, 255
+; RV64I-NEXT:    and a0, a0, s1
+; RV64I-NEXT:  .LBB30_3: # %start
+; RV64I-NEXT:    andi a0, a0, 255
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i8 @llvm.fptoui.sat.i8.f32(float %a)

 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __fixunssfdi@plt
 ; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lui a0, 325632
 ; RV64I-NEXT:    addiw a1, a0, -1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __gtsf2@plt
-; RV64I-NEXT:    bgtz a0, .LBB31_2
+; RV64I-NEXT:    blez a0, .LBB31_2
 ; RV64I-NEXT:  # %bb.1: # %start
+; RV64I-NEXT:    li a0, -1
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    j .LBB31_3
+; RV64I-NEXT:  .LBB31_2:
 ; RV64I-NEXT:    slti a0, s0, 0
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    and a0, a0, s1
-; RV64I-NEXT:    j .LBB31_3
-; RV64I-NEXT:  .LBB31_2:
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:  .LBB31_3: # %start
 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32

 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    lui a1, 847872
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __fixsfsi@plt
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lui s3, 524288
-; RV32I-NEXT:    lui s2, 524288
-; RV32I-NEXT:    bltz s1, .LBB32_2
+; RV32I-NEXT:    bgez s2, .LBB32_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    lui s1, 524288
 ; RV32I-NEXT:  .LBB32_2: # %start
 ; RV32I-NEXT:    lui a0, 323584
 ; RV32I-NEXT:    addi a1, a0, -1
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    blez a0, .LBB32_4
-; RV32I-NEXT:  # %bb.3:
-; RV32I-NEXT:    addi s2, s3, -1
+; RV32I-NEXT:  # %bb.3: # %start
+; RV32I-NEXT:    addi s1, s3, -1
 ; RV32I-NEXT:  .LBB32_4: # %start
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a0, a0, s2
+; RV32I-NEXT:    and a0, a0, s1
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_w_s_sat_sext:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s3, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    lui a1, 847872
 ; RV64I-NEXT:    call __gesf2@plt
-; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __fixsfdi@plt
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lui s3, 524288
-; RV64I-NEXT:    lui s2, 524288
-; RV64I-NEXT:    bltz s1, .LBB32_2
+; RV64I-NEXT:    bgez s2, .LBB32_2
 ; RV64I-NEXT:  # %bb.1: # %start
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    lui s1, 524288
 ; RV64I-NEXT:  .LBB32_2: # %start
 ; RV64I-NEXT:    lui a0, 323584
 ; RV64I-NEXT:    addiw a1, a0, -1
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gtsf2@plt
 ; RV64I-NEXT:    blez a0, .LBB32_4
-; RV64I-NEXT:  # %bb.3:
-; RV64I-NEXT:    addiw s2, s3, -1
+; RV64I-NEXT:  # %bb.3: # %start
+; RV64I-NEXT:    addiw s1, s3, -1
 ; RV64I-NEXT:  .LBB32_4: # %start
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    call __unordsf2@plt
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    and a0, a0, s2
+; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptosi.sat.i32.f32(float %a)
   ret i32 %0
 }

llvm/test/CodeGen/RISCV/half-convert-strict.ll

 declare i32 @llvm.experimental.constrained.fptoui.i32.f16(half, metadata)
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 ; FIXME: We should not have an fcvt.wu.h and an fcvt.lu.h.
 define i32 @fcvt_wu_h_multiple_use(half %x, i32* %y) {
 ; CHECKIZFH-LABEL: fcvt_wu_h_multiple_use:
 ; CHECKIZFH:       # %bb.0:
-; CHECKIZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
-; CHECKIZFH-NEXT:    li a0, 1
-; CHECKIZFH-NEXT:    beqz a1, .LBB4_2
+; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
+; CHECKIZFH-NEXT:    bnez a0, .LBB4_2
 ; CHECKIZFH-NEXT:  # %bb.1:
-; CHECKIZFH-NEXT:    mv a0, a1
+; CHECKIZFH-NEXT:    li a0, 1
 ; CHECKIZFH-NEXT:  .LBB4_2:
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_wu_h_multiple_use:
 ; RV32IDZFH:       # %bb.0:
-; RV32IDZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
-; RV32IDZFH-NEXT:    li a0, 1
-; RV32IDZFH-NEXT:    beqz a1, .LBB4_2
+; RV32IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
+; RV32IDZFH-NEXT:    bnez a0, .LBB4_2
 ; RV32IDZFH-NEXT:  # %bb.1:
-; RV32IDZFH-NEXT:    mv a0, a1
+; RV32IDZFH-NEXT:    li a0, 1
 ; RV32IDZFH-NEXT:  .LBB4_2:
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_wu_h_multiple_use:
 ; RV64IDZFH:       # %bb.0:
-; RV64IDZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
-; RV64IDZFH-NEXT:    li a0, 1
-; RV64IDZFH-NEXT:    beqz a1, .LBB4_2
+; RV64IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
+; RV64IDZFH-NEXT:    bnez a0, .LBB4_2
 ; RV64IDZFH-NEXT:  # %bb.1:
-; RV64IDZFH-NEXT:    mv a0, a1
+; RV64IDZFH-NEXT:    li a0, 1
 ; RV64IDZFH-NEXT:  .LBB4_2:
 ; RV64IDZFH-NEXT:    ret
   %a = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %x, metadata !"fpexcept.strict") strictfp
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 

llvm/test/CodeGen/RISCV/half-convert.ll

 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    lui a1, 815104
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __fixsfsi@plt
-; RV32I-NEXT:    lui s2, 1048568
-; RV32I-NEXT:    bltz s1, .LBB1_2
+; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    bgez s2, .LBB1_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    lui s1, 1048568
 ; RV32I-NEXT:  .LBB1_2: # %start
 ; RV32I-NEXT:    lui a0, 290816
 ; RV32I-NEXT:    addi a1, a0, -512
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    blez a0, .LBB1_4
-; RV32I-NEXT:  # %bb.3:
+; RV32I-NEXT:  # %bb.3: # %start
 ; RV32I-NEXT:    lui a0, 8
-; RV32I-NEXT:    addi s2, a0, -1
+; RV32I-NEXT:    addi s1, a0, -1
 ; RV32I-NEXT:  .LBB1_4: # %start
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a0, a0, s2
+; RV32I-NEXT:    and a0, a0, s1
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_si_h_sat:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -32
 ; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    lui a1, 815104
 ; RV64I-NEXT:    call __gesf2@plt
-; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __fixsfdi@plt
-; RV64I-NEXT:    lui s2, 1048568
-; RV64I-NEXT:    bltz s1, .LBB1_2
+; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    bgez s2, .LBB1_2
 ; RV64I-NEXT:  # %bb.1: # %start
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    lui s1, 1048568
 ; RV64I-NEXT:  .LBB1_2: # %start
 ; RV64I-NEXT:    lui a0, 290816
 ; RV64I-NEXT:    addiw a1, a0, -512
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gtsf2@plt
 ; RV64I-NEXT:    blez a0, .LBB1_4
-; RV64I-NEXT:  # %bb.3:
+; RV64I-NEXT:  # %bb.3: # %start
 ; RV64I-NEXT:    lui a0, 8
-; RV64I-NEXT:    addiw s2, a0, -1
+; RV64I-NEXT:    addiw s1, a0, -1
 ; RV64I-NEXT:  .LBB1_4: # %start
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    call __unordsf2@plt
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    and a0, a0, s2
+; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i16 @llvm.fptosi.sat.i16.f16(half %a)

 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    lui a0, 292864
 ; RV32I-NEXT:    addi a1, a0, -256
 ; RV32I-NEXT:    mv a0, s3
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    bgtz a0, .LBB3_2
-; RV32I-NEXT:  # %bb.1: # %start
+; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    slti a0, s2, 0
 ; RV32I-NEXT:    addi a0, a0, -1
 ; RV32I-NEXT:    and s0, a0, s1
 ; RV32I-NEXT:  .LBB3_2: # %start
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload

 ; RV64I-NEXT:    li a1, 0
 ; RV64I-NEXT:    call __gesf2@plt
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    lui a0, 292864
 ; RV64I-NEXT:    addiw a1, a0, -256
 ; RV64I-NEXT:    mv a0, s3
 ; RV64I-NEXT:    call __gtsf2@plt
 ; RV64I-NEXT:    bgtz a0, .LBB3_2
-; RV64I-NEXT:  # %bb.1: # %start
+; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    slti a0, s2, 0
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    and s0, a0, s1
 ; RV64I-NEXT:  .LBB3_2: # %start
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload

 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    lui a1, 847872
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __fixsfsi@plt
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lui s3, 524288
-; RV32I-NEXT:    lui s2, 524288
-; RV32I-NEXT:    bltz s1, .LBB5_2
+; RV32I-NEXT:    bgez s2, .LBB5_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    lui s1, 524288
 ; RV32I-NEXT:  .LBB5_2: # %start
 ; RV32I-NEXT:    lui a0, 323584
 ; RV32I-NEXT:    addi a1, a0, -1
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    blez a0, .LBB5_4
-; RV32I-NEXT:  # %bb.3:
-; RV32I-NEXT:    addi s2, s3, -1
+; RV32I-NEXT:  # %bb.3: # %start
+; RV32I-NEXT:    addi s1, s3, -1
 ; RV32I-NEXT:  .LBB5_4: # %start
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a0, a0, s2
+; RV32I-NEXT:    and a0, a0, s1
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_w_h_sat:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s3, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    lui a1, 847872
 ; RV64I-NEXT:    call __gesf2@plt
-; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __fixsfdi@plt
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lui s3, 524288
-; RV64I-NEXT:    lui s2, 524288
-; RV64I-NEXT:    bltz s1, .LBB5_2
+; RV64I-NEXT:    bgez s2, .LBB5_2
 ; RV64I-NEXT:  # %bb.1: # %start
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    lui s1, 524288
 ; RV64I-NEXT:  .LBB5_2: # %start
 ; RV64I-NEXT:    lui a0, 323584
 ; RV64I-NEXT:    addiw a1, a0, -1
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gtsf2@plt
 ; RV64I-NEXT:    blez a0, .LBB5_4
-; RV64I-NEXT:  # %bb.3:
-; RV64I-NEXT:    addiw s2, s3, -1
+; RV64I-NEXT:  # %bb.3: # %start
+; RV64I-NEXT:    addiw s1, s3, -1
 ; RV64I-NEXT:  .LBB5_4: # %start
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    call __unordsf2@plt
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    and a0, a0, s2
+; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 start:
; RV64I-NEXT:    ret
   ret i32 %1
 }
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 define i32 @fcvt_wu_h_multiple_use(half %x, i32* %y) nounwind {
 ; CHECKIZFH-LABEL: fcvt_wu_h_multiple_use:
 ; CHECKIZFH:       # %bb.0:
-; CHECKIZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
-; CHECKIZFH-NEXT:    li a0, 1
-; CHECKIZFH-NEXT:    beqz a1, .LBB7_2
+; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
+; CHECKIZFH-NEXT:    bnez a0, .LBB7_2
 ; CHECKIZFH-NEXT:  # %bb.1:
-; CHECKIZFH-NEXT:    mv a0, a1
+; CHECKIZFH-NEXT:    li a0, 1
 ; CHECKIZFH-NEXT:  .LBB7_2:
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_wu_h_multiple_use:
 ; RV32IDZFH:       # %bb.0:
-; RV32IDZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
-; RV32IDZFH-NEXT:    li a0, 1
-; RV32IDZFH-NEXT:    beqz a1, .LBB7_2
+; RV32IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
+; RV32IDZFH-NEXT:    bnez a0, .LBB7_2
 ; RV32IDZFH-NEXT:  # %bb.1:
-; RV32IDZFH-NEXT:    mv a0, a1
+; RV32IDZFH-NEXT:    li a0, 1
 ; RV32IDZFH-NEXT:  .LBB7_2:
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_wu_h_multiple_use:
 ; RV64IDZFH:       # %bb.0:
-; RV64IDZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
-; RV64IDZFH-NEXT:    li a0, 1
-; RV64IDZFH-NEXT:    beqz a1, .LBB7_2
+; RV64IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
+; RV64IDZFH-NEXT:    bnez a0, .LBB7_2
 ; RV64IDZFH-NEXT:  # %bb.1:
-; RV64IDZFH-NEXT:    mv a0, a1
+; RV64IDZFH-NEXT:    li a0, 1
 ; RV64IDZFH-NEXT:  .LBB7_2:
 ; RV64IDZFH-NEXT:    ret
 ;
 ; RV32I-LABEL: fcvt_wu_h_multiple_use:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call __fixunssfsi@plt
-; RV32I-NEXT:    mv a1, a0
-; RV32I-NEXT:    li a0, 1
-; RV32I-NEXT:    beqz a1, .LBB7_2
+; RV32I-NEXT:    bnez a0, .LBB7_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:    li a0, 1
 ; RV32I-NEXT:  .LBB7_2:
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_wu_h_multiple_use:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    call __fixunssfdi@plt
-; RV64I-NEXT:    mv a1, a0
-; RV64I-NEXT:    li a0, 1
-; RV64I-NEXT:    beqz a1, .LBB7_2
+; RV64I-NEXT:    bnez a0, .LBB7_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    mv a0, a1
+; RV64I-NEXT:    li a0, 1
 ; RV64I-NEXT:  .LBB7_2:
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
   %a = fptoui half %x to i32
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c

 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __fixunssfdi@plt
 ; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lui a0, 325632
 ; RV64I-NEXT:    addiw a1, a0, -1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __gtsf2@plt
-; RV64I-NEXT:    bgtz a0, .LBB8_2
+; RV64I-NEXT:    blez a0, .LBB8_2
 ; RV64I-NEXT:  # %bb.1: # %start
+; RV64I-NEXT:    li a0, -1
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    j .LBB8_3
+; RV64I-NEXT:  .LBB8_2:
 ; RV64I-NEXT:    slti a0, s0, 0
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    and a0, a0, s1
-; RV64I-NEXT:    j .LBB8_3
-; RV64I-NEXT:  .LBB8_2:
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:  .LBB8_3: # %start
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
 start:

 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    lui a1, 913408
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    mv s3, a0
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __fixsfdi@plt
 ; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    mv s2, a1
 ; RV32I-NEXT:    lui s4, 524288
-; RV32I-NEXT:    lui s3, 524288
-; RV32I-NEXT:    bltz s2, .LBB10_2
+; RV32I-NEXT:    bgez s3, .LBB10_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv s3, a1
+; RV32I-NEXT:    lui s2, 524288
 ; RV32I-NEXT:  .LBB10_2: # %start
 ; RV32I-NEXT:    lui a0, 389120
-; RV32I-NEXT:    addi s2, a0, -1
+; RV32I-NEXT:    addi s3, a0, -1
 ; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s2
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    blez a0, .LBB10_4
-; RV32I-NEXT:  # %bb.3:
-; RV32I-NEXT:    addi s3, s4, -1
+; RV32I-NEXT:  # %bb.3: # %start
+; RV32I-NEXT:    addi s2, s4, -1
 ; RV32I-NEXT:  .LBB10_4: # %start
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and s3, a0, s3
+; RV32I-NEXT:    and s2, a0, s2
 ; RV32I-NEXT:    mv a0, s0
-; RV32I-NEXT:    mv a1, s2
+; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
-; RV32I-NEXT:    neg s2, a0
+; RV32I-NEXT:    neg s3, a0
 ; RV32I-NEXT:    lui a1, 913408
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
 ; RV32I-NEXT:    addi a0, a0, -1
 ; RV32I-NEXT:    and a0, a0, s1
-; RV32I-NEXT:    or s1, s2, a0
+; RV32I-NEXT:    or s1, s3, a0
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
 ; RV32I-NEXT:    and a0, a0, s1
-; RV32I-NEXT:    mv a1, s3
+; RV32I-NEXT:    mv a1, s2
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret

 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    lui a1, 913408
 ; RV64I-NEXT:    call __gesf2@plt
 ; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __fixsfdi@plt
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    li s3, -1
-; RV64I-NEXT:    bltz s2, .LBB10_2
+; RV64I-NEXT:    bgez s2, .LBB10_2
 ; RV64I-NEXT:  # %bb.1: # %start
-; RV64I-NEXT:    mv s1, a0
-; RV64I-NEXT:    j .LBB10_3
-; RV64I-NEXT:  .LBB10_2:
 ; RV64I-NEXT:    slli s1, s3, 63
-; RV64I-NEXT:  .LBB10_3: # %start
+; RV64I-NEXT:  .LBB10_2: # %start
 ; RV64I-NEXT:    lui a0, 389120
 ; RV64I-NEXT:    addiw a1, a0, -1
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gtsf2@plt
-; RV64I-NEXT:    blez a0, .LBB10_5
-; RV64I-NEXT:  # %bb.4:
+; RV64I-NEXT:    blez a0, .LBB10_4
+; RV64I-NEXT:  # %bb.3: # %start
 ; RV64I-NEXT:    srli s1, s3, 1
-; RV64I-NEXT:  .LBB10_5: # %start
+; RV64I-NEXT:  .LBB10_4: # %start
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    call __unordsf2@plt
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload

 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    lui a1, 815104
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __fixsfsi@plt
-; RV32I-NEXT:    lui s2, 1048568
-; RV32I-NEXT:    bltz s1, .LBB32_2
+; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    bgez s2, .LBB32_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    lui s1, 1048568
 ; RV32I-NEXT:  .LBB32_2: # %start
 ; RV32I-NEXT:    lui a0, 290816
 ; RV32I-NEXT:    addi a1, a0, -512
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    blez a0, .LBB32_4
-; RV32I-NEXT:  # %bb.3:
+; RV32I-NEXT:  # %bb.3: # %start
 ; RV32I-NEXT:    lui a0, 8
-; RV32I-NEXT:    addi s2, a0, -1
+; RV32I-NEXT:    addi s1, a0, -1
 ; RV32I-NEXT:  .LBB32_4: # %start
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a0, a0, s2
+; RV32I-NEXT:    and a0, a0, s1
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srai a0, a0, 16
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_w_s_sat_i16:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -32
 ; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    lui a1, 815104
 ; RV64I-NEXT:    call __gesf2@plt
-; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __fixsfdi@plt
-; RV64I-NEXT:    lui s2, 1048568
-; RV64I-NEXT:    bltz s1, .LBB32_2
+; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    bgez s2, .LBB32_2
 ; RV64I-NEXT:  # %bb.1: # %start
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    lui s1, 1048568
 ; RV64I-NEXT:  .LBB32_2: # %start
 ; RV64I-NEXT:    lui a0, 290816
 ; RV64I-NEXT:    addiw a1, a0, -512
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gtsf2@plt
 ; RV64I-NEXT:    blez a0, .LBB32_4
-; RV64I-NEXT:  # %bb.3:
+; RV64I-NEXT:  # %bb.3: # %start
 ; RV64I-NEXT:    lui a0, 8
-; RV64I-NEXT:    addiw s2, a0, -1
+; RV64I-NEXT:    addiw s1, a0, -1
 ; RV64I-NEXT:  .LBB32_4: # %start
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    call __unordsf2@plt
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    and a0, a0, s2
+; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srai a0, a0, 48
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret

 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lui a0, 292864
 ; RV32I-NEXT:    addi a1, a0, -256
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    mv a1, s3
-; RV32I-NEXT:    bgtz a0, .LBB34_2
+; RV32I-NEXT:    blez a0, .LBB34_2
 ; RV32I-NEXT:  # %bb.1: # %start
+; RV32I-NEXT:    mv a0, s3
+; RV32I-NEXT:    j .LBB34_3
+; RV32I-NEXT:  .LBB34_2:
 ; RV32I-NEXT:    slti a0, s1, 0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a1, a0, s0
-; RV32I-NEXT:  .LBB34_2: # %start
-; RV32I-NEXT:    and a0, a1, s3
+; RV32I-NEXT:    and a0, a0, s0
+; RV32I-NEXT:  .LBB34_3: # %start
+; RV32I-NEXT:    and a0, a0, s3
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;

 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    li a1, 0
 ; RV64I-NEXT:    call __gesf2@plt
 ; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lui a0, 292864
 ; RV64I-NEXT:    addiw a1, a0, -256
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __gtsf2@plt
-; RV64I-NEXT:    mv a1, s3
-; RV64I-NEXT:    bgtz a0, .LBB34_2
+; RV64I-NEXT:    blez a0, .LBB34_2
 ; RV64I-NEXT:  # %bb.1: # %start
+; RV64I-NEXT:    mv a0, s3
+; RV64I-NEXT:    j .LBB34_3
+; RV64I-NEXT:  .LBB34_2:
 ; RV64I-NEXT:    slti a0, s1, 0
 ; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    and a1, a0, s0
-; RV64I-NEXT:  .LBB34_2: # %start
-; RV64I-NEXT:    and a0, a1, s3
+; RV64I-NEXT:    and a0, a0, s0
+; RV64I-NEXT:  .LBB34_3: # %start
+; RV64I-NEXT:    and a0, a0, s3
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 start:

 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    lui a1, 798720
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __fixsfsi@plt
-; RV32I-NEXT:    li s2, -128
-; RV32I-NEXT:    bltz s1, .LBB36_2
+; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    bgez s2, .LBB36_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    li s1, -128
 ; RV32I-NEXT:  .LBB36_2: # %start
 ; RV32I-NEXT:    lui a1, 274400
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    li s1, 127
-; RV32I-NEXT:    bgtz a0, .LBB36_4
+; RV32I-NEXT:    blez a0, .LBB36_4
 ; RV32I-NEXT:  # %bb.3: # %start
-; RV32I-NEXT:    mv s1, s2
+; RV32I-NEXT:    li s1, 127
 ; RV32I-NEXT:  .LBB36_4: # %start
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
 ; RV32I-NEXT:    and a0, a0, s1
 ; RV32I-NEXT:    slli a0, a0, 24

 ; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s2, 0(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    lui a1, 798720
 ; RV64I-NEXT:    call __gesf2@plt
-; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __fixsfdi@plt
-; RV64I-NEXT:    li s2, -128
-; RV64I-NEXT:    bltz s1, .LBB36_2
+; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    bgez s2, .LBB36_2
 ; RV64I-NEXT:  # %bb.1: # %start
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    li s1, -128
 ; RV64I-NEXT:  .LBB36_2: # %start
 ; RV64I-NEXT:    lui a1, 274400
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gtsf2@plt
-; RV64I-NEXT:    li s1, 127
-; RV64I-NEXT:    bgtz a0, .LBB36_4
+; RV64I-NEXT:    blez a0, .LBB36_4
 ; RV64I-NEXT:  # %bb.3: # %start
-; RV64I-NEXT:    mv s1, s2
+; RV64I-NEXT:    li s1, 127
 ; RV64I-NEXT:  .LBB36_4: # %start
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    call __unordsf2@plt
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:    slli a0, a0, 56

 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    call __fixunssfsi@plt
 ; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lui a1, 276464
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    call __gtsf2@plt
-; RV32I-NEXT:    li a1, 255
-; RV32I-NEXT:    bgtz a0, .LBB38_2
+; RV32I-NEXT:    blez a0, .LBB38_2
 ; RV32I-NEXT:  # %bb.1: # %start
+; RV32I-NEXT:    li a0, 255
+; RV32I-NEXT:    j .LBB38_3
+; RV32I-NEXT:  .LBB38_2:
 ; RV32I-NEXT:    slti a0, s0, 0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a1, a0, s1
-; RV32I-NEXT:  .LBB38_2: # %start
-; RV32I-NEXT:    andi a0, a1, 255
+; RV32I-NEXT:    and a0, a0, s1
+; RV32I-NEXT:  .LBB38_3: # %start
+; RV32I-NEXT:    andi a0, a0, 255
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_wu_s_sat_i8:

 ; RV64I-NEXT:    call __gesf2@plt
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __fixunssfdi@plt
 ; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lui a1, 276464
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __gtsf2@plt
-; RV64I-NEXT:    li a1, 255
-; RV64I-NEXT:    bgtz a0, .LBB38_2
+; RV64I-NEXT:    blez a0, .LBB38_2
 ; RV64I-NEXT:  # %bb.1: # %start
+; RV64I-NEXT:    li a0, 255
+; RV64I-NEXT:    j .LBB38_3
+; RV64I-NEXT:  .LBB38_2:
 ; RV64I-NEXT:    slti a0, s0, 0
 ; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    and a1, a0, s1
-; RV64I-NEXT:  .LBB38_2: # %start
-; RV64I-NEXT:    andi a0, a1, 255
+; RV64I-NEXT:    and a0, a0, s1
+; RV64I-NEXT:  .LBB38_3: # %start
+; RV64I-NEXT:    andi a0, a0, 255
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32
 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i8 @llvm.fptoui.sat.i8.f16(half %a)

 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __fixunssfdi@plt
 ; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lui a0, 325632
 ; RV64I-NEXT:    addiw a1, a0, -1
 ; RV64I-NEXT:    mv a0, s2
 ; RV64I-NEXT:    call __gtsf2@plt
-; RV64I-NEXT:    bgtz a0, .LBB39_2
+; RV64I-NEXT:    blez a0, .LBB39_2
 ; RV64I-NEXT:  # %bb.1: # %start
+; RV64I-NEXT:    li a0, -1
+; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    j .LBB39_3
+; RV64I-NEXT:  .LBB39_2:
 ; RV64I-NEXT:    slti a0, s0, 0
 ; RV64I-NEXT:    addi a0, a0, -1
 ; RV64I-NEXT:    and a0, a0, s1
-; RV64I-NEXT:    j .LBB39_3
-; RV64I-NEXT:  .LBB39_2:
-; RV64I-NEXT:    li a0, -1
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:  .LBB39_3: # %start
 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 32

 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    lui a1, 847872
 ; RV32I-NEXT:    call __gesf2@plt
-; RV32I-NEXT:    mv s1, a0
+; RV32I-NEXT:    mv s2, a0
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __fixsfsi@plt
+; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lui s3, 524288
-; RV32I-NEXT:    lui s2, 524288
-; RV32I-NEXT:    bltz s1, .LBB40_2
+; RV32I-NEXT:    bgez s2, .LBB40_2
 ; RV32I-NEXT:  # %bb.1: # %start
-; RV32I-NEXT:    mv s2, a0
+; RV32I-NEXT:    lui s1, 524288
 ; RV32I-NEXT:  .LBB40_2: # %start
 ; RV32I-NEXT:    lui a0, 323584
 ; RV32I-NEXT:    addi a1, a0, -1
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    blez a0, .LBB40_4
-; RV32I-NEXT:  # %bb.3:
-; RV32I-NEXT:    addi s2, s3, -1
+; RV32I-NEXT:  # %bb.3: # %start
+; RV32I-NEXT:    addi s1, s3, -1
 ; RV32I-NEXT:  .LBB40_4: # %start
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __unordsf2@plt
 ; RV32I-NEXT:    snez a0, a0
 ; RV32I-NEXT:    addi a0, a0, -1
-; RV32I-NEXT:    and a0, a0, s2
+; RV32I-NEXT:    and a0, a0, s1
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 32
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcvt_w_h_sat_sext:
 ; RV64I:       # %bb.0: # %start
 ; RV64I-NEXT:    addi sp, sp, -48
 ; RV64I-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s3, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
 ; RV64I-NEXT:    mv s0, a0
 ; RV64I-NEXT:    lui a1, 847872
 ; RV64I-NEXT:    call __gesf2@plt
-; RV64I-NEXT:    mv s1, a0
+; RV64I-NEXT:    mv s2, a0
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __fixsfdi@plt
+; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    lui s3, 524288
-; RV64I-NEXT:    lui s2, 524288
-; RV64I-NEXT:    bltz s1, .LBB40_2
+; RV64I-NEXT:    bgez s2, .LBB40_2
 ; RV64I-NEXT:  # %bb.1: # %start
-; RV64I-NEXT:    mv s2, a0
+; RV64I-NEXT:    lui s1, 524288
 ; RV64I-NEXT:  .LBB40_2: # %start
 ; RV64I-NEXT:    lui a0, 323584
 ; RV64I-NEXT:    addiw a1, a0, -1
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __gtsf2@plt
 ; RV64I-NEXT:    blez a0, .LBB40_4
-; RV64I-NEXT:  # %bb.3:
-; RV64I-NEXT:    addiw s2, s3, -1
+; RV64I-NEXT:  # %bb.3: # %start
+; RV64I-NEXT:    addiw s1, s3, -1
 ; RV64I-NEXT:  .LBB40_4: # %start
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    mv a1, s0
 ; RV64I-NEXT:    call __unordsf2@plt
 ; RV64I-NEXT:    snez a0, a0
 ; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    and a0, a0, s2
+; RV64I-NEXT:    and a0, a0, s1
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 48
 ; RV64I-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %0
 }

llvm/test/CodeGen/RISCV/rv32zbb.ll

 ; RV32I-NEXT:    call __mulsi3@plt
 ; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    lui a0, %hi(.LCPI3_0)
 ; RV32I-NEXT:    addi s4, a0, %lo(.LCPI3_0)
 ; RV32I-NEXT:    neg a0, s2
 ; RV32I-NEXT:    and a0, s2, a0
 ; RV32I-NEXT:    mv a1, s3
 ; RV32I-NEXT:    call __mulsi3@plt
-; RV32I-NEXT:    li a1, 32
-; RV32I-NEXT:    beqz s2, .LBB3_2
+; RV32I-NEXT:    bnez s2, .LBB3_3
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    srli a0, a0, 27
-; RV32I-NEXT:    add a0, s4, a0
-; RV32I-NEXT:    lbu a1, 0(a0)
+; RV32I-NEXT:    li a0, 32
+; RV32I-NEXT:    beqz s0, .LBB3_4
 ; RV32I-NEXT:  .LBB3_2:
-; RV32I-NEXT:    bnez s0, .LBB3_4
-; RV32I-NEXT:  # %bb.3:
-; RV32I-NEXT:    addi a0, a1, 32
-; RV32I-NEXT:    j .LBB3_5
-; RV32I-NEXT:  .LBB3_4:
 ; RV32I-NEXT:    srli a0, s1, 27
 ; RV32I-NEXT:    add a0, s4, a0
 ; RV32I-NEXT:    lbu a0, 0(a0)
+; RV32I-NEXT:    j .LBB3_5
+; RV32I-NEXT:  .LBB3_3:
+; RV32I-NEXT:    srli a0, a0, 27
+; RV32I-NEXT:    add a0, s4, a0
+; RV32I-NEXT:    lbu a0, 0(a0)
+; RV32I-NEXT:    bnez s0, .LBB3_2
+; RV32I-NEXT:  .LBB3_4:
+; RV32I-NEXT:    addi a0, a0, 32
 ; RV32I-NEXT:  .LBB3_5:
 ; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload