[RISCV] Don't emit fractional VIDs with negative steps

[frasercrmck]

Summary

We can't shift-right negative numbers to divide them, so avoid emitting
such sequences. Use negative numerators as a proxy for this situation, since
the indices are always non-negative.

An alternative strategy could be to add a compiler flag to emit division
instructions, which would at least allow us to test the VID sequence
matching itself.

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

642

This code seemed to do the right thing if I did the math correctly

-5 - (vid / 4)

[frasercrmck]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

642

Yes I think you're right, thanks. The issue is that I got the wrong check for positivity, as there's a case where we make the effective numerator positive and StepNumerator is left in the old negative state. I think we should be checking SplatStepVal instead.

[frasercrmck]

fix check for positivity

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (auto SimpleVID = isSimpleVIDSequence(Op)) {
     }
 
     // Only emit VIDs with suitably-small steps/addends. We use imm5 is a
     // threshold since it's the immediate value many RVV instructions accept.
     // There is no vmul.vi instruction so ensure multiply constant can fit in
     // a single addi instruction.
     if (((StepOpcode == ISD::MUL && isInt<12>(SplatStepVal)) ||
          (StepOpcode == ISD::SHL && isUInt<5>(SplatStepVal))) &&
-        isPowerOf2_32(StepDenominator) && isInt<5>(Addend)) {
+        isPowerOf2_32(StepDenominator) &&
+        (SplatStepVal >= 0 || StepDenominator == 1) && isInt<5>(Addend)) {
       SDValue VID = DAG.getNode(RISCVISD::VID_VL, DL, ContainerVT, Mask, VL);
       // Convert right out of the scalable type so we can use standard ISD
       // nodes for the rest of the computation. If we used scalable types with
       // these, we'd lose the fixed-length vector info and generate worse
       // vsetvli code.
       VID = convertFromScalableVector(VT, VID, DAG, Subtarget);
       if ((StepOpcode == ISD::MUL && SplatStepVal != 1) ||
           (StepOpcode == ISD::SHL && SplatStepVal != 0)) {

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

; CHECK-NEXT:    ret
   ret void
 }
 
 define void @buildvec_vid_stepn1o4_addn5_v8i8(<8 x i8>* %z0) {
 ; CHECK-LABEL: buildvec_vid_stepn1o4_addn5_v8i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
 ; CHECK-NEXT:    vid.v v8
 ; CHECK-NEXT:    vsrl.vi v8, v8, 2
 ; CHECK-NEXT:    vrsub.vi v8, v8, -5
 ; CHECK-NEXT:    vse8.v v8, (a0)
 ; CHECK-NEXT:    ret
   store <8 x i8> <i8 -5, i8 -5, i8 -5, i8 -5, i8 -6, i8 -6, i8 -6, i8 -6>, <8 x i8>* %z0
   ret void
 }
 
 define void @buildvec_vid_mpy_imm_v8i16(<8 x i16>* %x) {

 ; CHECK-NEXT:    lui a0, %hi(.LCPI38_0)
 ; CHECK-NEXT:    addi a0, a0, %lo(.LCPI38_0)
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
 ; CHECK-NEXT:    vle8.v v8, (a0)
 ; CHECK-NEXT:    ret
   ret <4 x i8> <i8 3, i8 3, i8 1, i8 0>
 }
 
-; FIXME: This is not a valid way to emit this vid sequence: shift-right for
-; division only works for non-negative numbers!
+; We match this as a VID sequence (-3 / 8) + 5 but choose not to introduce
+; division to compute it.
 define <16 x i8> @buildvec_not_vid_v16i8() {
 ; CHECK-LABEL: buildvec_not_vid_v16i8:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 3
 ; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
-; CHECK-NEXT:    vid.v v8
-; CHECK-NEXT:    li a0, -3
-; CHECK-NEXT:    vmul.vx v8, v8, a0
-; CHECK-NEXT:    vsrl.vi v8, v8, 3
-; CHECK-NEXT:    vadd.vi v8, v8, 5
+; CHECK-NEXT:    vmv.s.x v9, a0
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vsetivli zero, 7, e8, m1, tu, mu
+; CHECK-NEXT:    vslideup.vi v8, v9, 6
 ; CHECK-NEXT:    ret
   ret <16 x i8> <i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 3, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 0, i8 0>
 }