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Differential D120228

[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR intrinsics.
ClosedPublic

Authored by khchen on Feb 20 2022, 7:43 PM.

Details

Reviewers
craig.topper
rogfer01
frasercrmck
kito-cheng
arcbbb
monkchiang
eopXD
Commits
rG10fd2822b77e: [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR
Summary

Those operations are updated under a tail agnostic policy, but they
could have mask agnostic or undisturbed.

Diff Detail

Event Timeline

khchen created this revision.Feb 20 2022, 7:43 PM
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence and 24 others. · View Herald TranscriptFeb 20 2022, 7:43 PM
khchen requested review of this revision.Feb 20 2022, 7:43 PM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptFeb 20 2022, 7:43 PM
Herald added subscribers: llvm-commits, cfe-commits, • pcwang-thead, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B150631: Diff 410210.Feb 20 2022, 7:43 PM
khchen added a parent revision: D120227: [RISCV] Add policy operand for masked vid and viota IR intrinsics..Feb 20 2022, 7:43 PM
craig.topper added inline comments.Feb 20 2022, 8:50 PM
llvm/test/CodeGen/RISCV/rvv/vmsif.ll
34

Should vmsif, vmsof, and vmsbf have ForceTailAgnostic like vmand, vmxor, etc.?

craig.topper added inline comments.Feb 20 2022, 8:59 PM
llvm/test/CodeGen/RISCV/rvv/vmsif.ll
34

Nevermind. Ignore this comment.

rogfer01 accepted this revision.Feb 24 2022, 12:26 AM

LGTM. Thanks @khchen !

This revision is now accepted and ready to land.Feb 24 2022, 12:26 AM
khchen added a child revision: D120870: [RISCV][NFC] Refine and refactor RISCVVEmitter and riscv_vector.td..Mar 2 2022, 10:39 PM
lhtin added a subscriber: lhtin.Mar 6 2022, 1:06 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 6 2022, 1:06 AM
khchen updated this revision to Diff 416057.Mar 16 2022, 8:34 PM

rebase on main.

Herald added subscribers: • s, arichardson. · View Herald TranscriptMar 16 2022, 8:34 PM
Harbormaster completed remote builds in B154760: Diff 416057.Mar 16 2022, 8:35 PM
This revision was landed with ongoing or failed builds.Mar 22 2022, 7:53 AM
Closed by commit rG10fd2822b77e: [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR (authored by khchen). · Explain Why
This revision was automatically updated to reflect the committed changes.
khchen added a commit: rG10fd2822b77e: [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR.
Herald added a subscriber: StephenFan. · View Herald TranscriptMar 22 2022, 7:53 AM
khchen added a reverting change: D122455: Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR".Mar 24 2022, 9:00 PM
khchen added a reverting change: rG10b2760da0fd: Revert "[RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR".Mar 29 2022, 6:21 PM

Revision Contents

PathSize
clang/
include/
clang/
Basic/
6 lines
test/
CodeGen/
RISCV/
rvv-intrinsics-overloaded/
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rvv-intrinsics/
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llvm/
include/
llvm/
IR/
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lib/
Target/
RISCV/
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test/
CodeGen/
RISCV/
rvv/
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Diff 416057

clang/include/clang/Basic/riscv_vector.td

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defm vnsrl : RVVUnsignedNShiftBuiltinSet; defm vnsrl : RVVUnsignedNShiftBuiltinSet;
defm vnsra : RVVSignedNShiftBuiltinSet; defm vnsra : RVVSignedNShiftBuiltinSet;
} }
defm vncvt_x_x_w : RVVPseudoVNCVTBuiltin<"vnsrl", "vncvt_x", "csi", defm vncvt_x_x_w : RVVPseudoVNCVTBuiltin<"vnsrl", "vncvt_x", "csi",
[["v", "vw"], [["v", "vw"],
["Uv", "UvUw"]]>; ["Uv", "UvUw"]]>;
// 12.8. Vector Integer Comparison Instructions // 12.8. Vector Integer Comparison Instructions
let HasPolicy = false in {
defm vmseq : RVVIntMaskOutBuiltinSet; defm vmseq : RVVIntMaskOutBuiltinSet;
defm vmsne : RVVIntMaskOutBuiltinSet; defm vmsne : RVVIntMaskOutBuiltinSet;
defm vmsltu : RVVUnsignedMaskOutBuiltinSet; defm vmsltu : RVVUnsignedMaskOutBuiltinSet;
defm vmslt : RVVSignedMaskOutBuiltinSet; defm vmslt : RVVSignedMaskOutBuiltinSet;
defm vmsleu : RVVUnsignedMaskOutBuiltinSet; defm vmsleu : RVVUnsignedMaskOutBuiltinSet;
defm vmsle : RVVSignedMaskOutBuiltinSet; defm vmsle : RVVSignedMaskOutBuiltinSet;
defm vmsgtu : RVVUnsignedMaskOutBuiltinSet; defm vmsgtu : RVVUnsignedMaskOutBuiltinSet;
defm vmsgt : RVVSignedMaskOutBuiltinSet; defm vmsgt : RVVSignedMaskOutBuiltinSet;
defm vmsgeu : RVVUnsignedMaskOutBuiltinSet; defm vmsgeu : RVVUnsignedMaskOutBuiltinSet;
defm vmsge : RVVSignedMaskOutBuiltinSet; defm vmsge : RVVSignedMaskOutBuiltinSet;
}
// 12.9. Vector Integer Min/Max Instructions // 12.9. Vector Integer Min/Max Instructions
let NoMaskPolicy = HasPassthruOperand in { let NoMaskPolicy = HasPassthruOperand in {
defm vminu : RVVUnsignedBinBuiltinSet; defm vminu : RVVUnsignedBinBuiltinSet;
defm vmin : RVVSignedBinBuiltinSet; defm vmin : RVVSignedBinBuiltinSet;
defm vmaxu : RVVUnsignedBinBuiltinSet; defm vmaxu : RVVUnsignedBinBuiltinSet;
defm vmax : RVVSignedBinBuiltinSet; defm vmax : RVVSignedBinBuiltinSet;
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defm vfsgnj : RVVFloatingBinBuiltinSet; defm vfsgnj : RVVFloatingBinBuiltinSet;
defm vfsgnjn : RVVFloatingBinBuiltinSet; defm vfsgnjn : RVVFloatingBinBuiltinSet;
defm vfsgnjx : RVVFloatingBinBuiltinSet; defm vfsgnjx : RVVFloatingBinBuiltinSet;
} }
defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "xfd">; defm vfneg_v : RVVPseudoVFUnaryBuiltin<"vfsgnjn", "xfd">;
defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "xfd">; defm vfabs_v : RVVPseudoVFUnaryBuiltin<"vfsgnjx", "xfd">;
// 14.13. Vector Floating-Point Compare Instructions // 14.13. Vector Floating-Point Compare Instructions
let HasPolicy = false in {
defm vmfeq : RVVFloatingMaskOutBuiltinSet; defm vmfeq : RVVFloatingMaskOutBuiltinSet;
defm vmfne : RVVFloatingMaskOutBuiltinSet; defm vmfne : RVVFloatingMaskOutBuiltinSet;
defm vmflt : RVVFloatingMaskOutBuiltinSet; defm vmflt : RVVFloatingMaskOutBuiltinSet;
defm vmfle : RVVFloatingMaskOutBuiltinSet; defm vmfle : RVVFloatingMaskOutBuiltinSet;
defm vmfgt : RVVFloatingMaskOutBuiltinSet; defm vmfgt : RVVFloatingMaskOutBuiltinSet;
defm vmfge : RVVFloatingMaskOutBuiltinSet; defm vmfge : RVVFloatingMaskOutBuiltinSet;
}
// 14.14. Vector Floating-Point Classify Instruction // 14.14. Vector Floating-Point Classify Instruction
let Name = "vfclass_v", NoMaskPolicy = HasPassthruOperand in let Name = "vfclass_v", NoMaskPolicy = HasPassthruOperand in
def vfclass : RVVOp0Builtin<"Uv", "Uvv", "xfd">; def vfclass : RVVOp0Builtin<"Uv", "Uvv", "xfd">;
// 14.15. Vector Floating-Point Merge Instructio // 14.15. Vector Floating-Point Merge Instructio
// C/C++ Operand: (mask, op1, op2, vl), Builtin: (op1, op2, mask, vl) // C/C++ Operand: (mask, op1, op2, vl), Builtin: (op1, op2, mask, vl)
let HasMask = false, HasPolicy = false, let HasMask = false, HasPolicy = false,
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defm vmnot_m : RVVPseudoMaskBuiltin<"vmnand", "c">; defm vmnot_m : RVVPseudoMaskBuiltin<"vmnand", "c">;
let HasPolicy = false in { let HasPolicy = false in {
// 16.2. Vector count population in mask vcpop.m // 16.2. Vector count population in mask vcpop.m
def vcpop : RVVMaskOp0Builtin<"um">; def vcpop : RVVMaskOp0Builtin<"um">;
// 16.3. vfirst find-first-set mask bit // 16.3. vfirst find-first-set mask bit
def vfirst : RVVMaskOp0Builtin<"lm">; def vfirst : RVVMaskOp0Builtin<"lm">;
}
// 16.4. vmsbf.m set-before-first mask bit // 16.4. vmsbf.m set-before-first mask bit
def vmsbf : RVVMaskUnaryBuiltin; def vmsbf : RVVMaskUnaryBuiltin;
// 16.5. vmsif.m set-including-first mask bit // 16.5. vmsif.m set-including-first mask bit
def vmsif : RVVMaskUnaryBuiltin; def vmsif : RVVMaskUnaryBuiltin;
// 16.6. vmsof.m set-only-first mask bit // 16.6. vmsof.m set-only-first mask bit
def vmsof : RVVMaskUnaryBuiltin; def vmsof : RVVMaskUnaryBuiltin;
}
let NoMaskPolicy = HasPassthruOperand, HasNoMaskedOverloaded = false in { let NoMaskPolicy = HasPassthruOperand, HasNoMaskedOverloaded = false in {
// 16.8. Vector Iota Instruction // 16.8. Vector Iota Instruction
defm viota : RVVOutBuiltinSet<"viota", "csil", [["m", "Uv", "Uvm"]]>; defm viota : RVVOutBuiltinSet<"viota", "csil", [["m", "Uv", "Uvm"]]>;
// 16.9. Vector Element Index Instruction // 16.9. Vector Element Index Instruction
defm vid : RVVOutBuiltinSet<"vid", "csil", [["v", "v", "v"], defm vid : RVVOutBuiltinSet<"vid", "csil", [["v", "v", "v"],
["v", "Uv", "Uv"]]>; ["v", "Uv", "Uv"]]>;
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clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsbf.c

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// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
// //
vbool64_t test_vmsbf_m_b64(vbool64_t op1, size_t vl) { return vmsbf(op1, vl); } vbool64_t test_vmsbf_m_b64(vbool64_t op1, size_t vl) { return vmsbf(op1, vl); }
// CHECK-RV64-LABEL: @test_vmsbf_m_b1_m( // CHECK-RV64-LABEL: @test_vmsbf_m_b1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
// //
vbool1_t test_vmsbf_m_b1_m(vbool1_t mask, vbool1_t maskedoff, vbool1_t op1, vbool1_t test_vmsbf_m_b1_m(vbool1_t mask, vbool1_t maskedoff, vbool1_t op1,
size_t vl) { size_t vl) {
return vmsbf(mask, maskedoff, op1, vl); return vmsbf(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsbf_m_b2_m( // CHECK-RV64-LABEL: @test_vmsbf_m_b2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
// //
vbool2_t test_vmsbf_m_b2_m(vbool2_t mask, vbool2_t maskedoff, vbool2_t op1, vbool2_t test_vmsbf_m_b2_m(vbool2_t mask, vbool2_t maskedoff, vbool2_t op1,
size_t vl) { size_t vl) {
return vmsbf(mask, maskedoff, op1, vl); return vmsbf(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsbf_m_b4_m( // CHECK-RV64-LABEL: @test_vmsbf_m_b4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
// //
vbool4_t test_vmsbf_m_b4_m(vbool4_t mask, vbool4_t maskedoff, vbool4_t op1, vbool4_t test_vmsbf_m_b4_m(vbool4_t mask, vbool4_t maskedoff, vbool4_t op1,
size_t vl) { size_t vl) {
return vmsbf(mask, maskedoff, op1, vl); return vmsbf(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsbf_m_b8_m( // CHECK-RV64-LABEL: @test_vmsbf_m_b8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
// //
vbool8_t test_vmsbf_m_b8_m(vbool8_t mask, vbool8_t maskedoff, vbool8_t op1, vbool8_t test_vmsbf_m_b8_m(vbool8_t mask, vbool8_t maskedoff, vbool8_t op1,
size_t vl) { size_t vl) {
return vmsbf(mask, maskedoff, op1, vl); return vmsbf(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsbf_m_b16_m( // CHECK-RV64-LABEL: @test_vmsbf_m_b16_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
// //
vbool16_t test_vmsbf_m_b16_m(vbool16_t mask, vbool16_t maskedoff, vbool16_t op1, vbool16_t test_vmsbf_m_b16_m(vbool16_t mask, vbool16_t maskedoff, vbool16_t op1,
size_t vl) { size_t vl) {
return vmsbf(mask, maskedoff, op1, vl); return vmsbf(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsbf_m_b32_m( // CHECK-RV64-LABEL: @test_vmsbf_m_b32_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
// //
vbool32_t test_vmsbf_m_b32_m(vbool32_t mask, vbool32_t maskedoff, vbool32_t op1, vbool32_t test_vmsbf_m_b32_m(vbool32_t mask, vbool32_t maskedoff, vbool32_t op1,
size_t vl) { size_t vl) {
return vmsbf(mask, maskedoff, op1, vl); return vmsbf(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsbf_m_b64_m( // CHECK-RV64-LABEL: @test_vmsbf_m_b64_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
// //
vbool64_t test_vmsbf_m_b64_m(vbool64_t mask, vbool64_t maskedoff, vbool64_t op1, vbool64_t test_vmsbf_m_b64_m(vbool64_t mask, vbool64_t maskedoff, vbool64_t op1,
size_t vl) { size_t vl) {
return vmsbf(mask, maskedoff, op1, vl); return vmsbf(mask, maskedoff, op1, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsif.c

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
// //
vbool64_t test_vmsif_m_b64(vbool64_t op1, size_t vl) { return vmsif(op1, vl); } vbool64_t test_vmsif_m_b64(vbool64_t op1, size_t vl) { return vmsif(op1, vl); }
// CHECK-RV64-LABEL: @test_vmsif_m_b1_m( // CHECK-RV64-LABEL: @test_vmsif_m_b1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
// //
vbool1_t test_vmsif_m_b1_m(vbool1_t mask, vbool1_t maskedoff, vbool1_t op1, vbool1_t test_vmsif_m_b1_m(vbool1_t mask, vbool1_t maskedoff, vbool1_t op1,
size_t vl) { size_t vl) {
return vmsif(mask, maskedoff, op1, vl); return vmsif(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsif_m_b2_m( // CHECK-RV64-LABEL: @test_vmsif_m_b2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
// //
vbool2_t test_vmsif_m_b2_m(vbool2_t mask, vbool2_t maskedoff, vbool2_t op1, vbool2_t test_vmsif_m_b2_m(vbool2_t mask, vbool2_t maskedoff, vbool2_t op1,
size_t vl) { size_t vl) {
return vmsif(mask, maskedoff, op1, vl); return vmsif(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsif_m_b4_m( // CHECK-RV64-LABEL: @test_vmsif_m_b4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
// //
vbool4_t test_vmsif_m_b4_m(vbool4_t mask, vbool4_t maskedoff, vbool4_t op1, vbool4_t test_vmsif_m_b4_m(vbool4_t mask, vbool4_t maskedoff, vbool4_t op1,
size_t vl) { size_t vl) {
return vmsif(mask, maskedoff, op1, vl); return vmsif(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsif_m_b8_m( // CHECK-RV64-LABEL: @test_vmsif_m_b8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
// //
vbool8_t test_vmsif_m_b8_m(vbool8_t mask, vbool8_t maskedoff, vbool8_t op1, vbool8_t test_vmsif_m_b8_m(vbool8_t mask, vbool8_t maskedoff, vbool8_t op1,
size_t vl) { size_t vl) {
return vmsif(mask, maskedoff, op1, vl); return vmsif(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsif_m_b16_m( // CHECK-RV64-LABEL: @test_vmsif_m_b16_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
// //
vbool16_t test_vmsif_m_b16_m(vbool16_t mask, vbool16_t maskedoff, vbool16_t op1, vbool16_t test_vmsif_m_b16_m(vbool16_t mask, vbool16_t maskedoff, vbool16_t op1,
size_t vl) { size_t vl) {
return vmsif(mask, maskedoff, op1, vl); return vmsif(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsif_m_b32_m( // CHECK-RV64-LABEL: @test_vmsif_m_b32_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
// //
vbool32_t test_vmsif_m_b32_m(vbool32_t mask, vbool32_t maskedoff, vbool32_t op1, vbool32_t test_vmsif_m_b32_m(vbool32_t mask, vbool32_t maskedoff, vbool32_t op1,
size_t vl) { size_t vl) {
return vmsif(mask, maskedoff, op1, vl); return vmsif(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsif_m_b64_m( // CHECK-RV64-LABEL: @test_vmsif_m_b64_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
// //
vbool64_t test_vmsif_m_b64_m(vbool64_t mask, vbool64_t maskedoff, vbool64_t op1, vbool64_t test_vmsif_m_b64_m(vbool64_t mask, vbool64_t maskedoff, vbool64_t op1,
size_t vl) { size_t vl) {
return vmsif(mask, maskedoff, op1, vl); return vmsif(mask, maskedoff, op1, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmsof.c

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
// //
vbool64_t test_vmsof_m_b64(vbool64_t op1, size_t vl) { return vmsof(op1, vl); } vbool64_t test_vmsof_m_b64(vbool64_t op1, size_t vl) { return vmsof(op1, vl); }
// CHECK-RV64-LABEL: @test_vmsof_m_b1_m( // CHECK-RV64-LABEL: @test_vmsof_m_b1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
// //
vbool1_t test_vmsof_m_b1_m(vbool1_t mask, vbool1_t maskedoff, vbool1_t op1, vbool1_t test_vmsof_m_b1_m(vbool1_t mask, vbool1_t maskedoff, vbool1_t op1,
size_t vl) { size_t vl) {
return vmsof(mask, maskedoff, op1, vl); return vmsof(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsof_m_b2_m( // CHECK-RV64-LABEL: @test_vmsof_m_b2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
// //
vbool2_t test_vmsof_m_b2_m(vbool2_t mask, vbool2_t maskedoff, vbool2_t op1, vbool2_t test_vmsof_m_b2_m(vbool2_t mask, vbool2_t maskedoff, vbool2_t op1,
size_t vl) { size_t vl) {
return vmsof(mask, maskedoff, op1, vl); return vmsof(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsof_m_b4_m( // CHECK-RV64-LABEL: @test_vmsof_m_b4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
// //
vbool4_t test_vmsof_m_b4_m(vbool4_t mask, vbool4_t maskedoff, vbool4_t op1, vbool4_t test_vmsof_m_b4_m(vbool4_t mask, vbool4_t maskedoff, vbool4_t op1,
size_t vl) { size_t vl) {
return vmsof(mask, maskedoff, op1, vl); return vmsof(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsof_m_b8_m( // CHECK-RV64-LABEL: @test_vmsof_m_b8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
// //
vbool8_t test_vmsof_m_b8_m(vbool8_t mask, vbool8_t maskedoff, vbool8_t op1, vbool8_t test_vmsof_m_b8_m(vbool8_t mask, vbool8_t maskedoff, vbool8_t op1,
size_t vl) { size_t vl) {
return vmsof(mask, maskedoff, op1, vl); return vmsof(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsof_m_b16_m( // CHECK-RV64-LABEL: @test_vmsof_m_b16_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
// //
vbool16_t test_vmsof_m_b16_m(vbool16_t mask, vbool16_t maskedoff, vbool16_t op1, vbool16_t test_vmsof_m_b16_m(vbool16_t mask, vbool16_t maskedoff, vbool16_t op1,
size_t vl) { size_t vl) {
return vmsof(mask, maskedoff, op1, vl); return vmsof(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsof_m_b32_m( // CHECK-RV64-LABEL: @test_vmsof_m_b32_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
// //
vbool32_t test_vmsof_m_b32_m(vbool32_t mask, vbool32_t maskedoff, vbool32_t op1, vbool32_t test_vmsof_m_b32_m(vbool32_t mask, vbool32_t maskedoff, vbool32_t op1,
size_t vl) { size_t vl) {
return vmsof(mask, maskedoff, op1, vl); return vmsof(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsof_m_b64_m( // CHECK-RV64-LABEL: @test_vmsof_m_b64_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
// //
vbool64_t test_vmsof_m_b64_m(vbool64_t mask, vbool64_t maskedoff, vbool64_t op1, vbool64_t test_vmsof_m_b64_m(vbool64_t mask, vbool64_t maskedoff, vbool64_t op1,
size_t vl) { size_t vl) {
return vmsof(mask, maskedoff, op1, vl); return vmsof(mask, maskedoff, op1, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vmsbf.c

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
// //
vbool64_t test_vmsbf_m_b64(vbool64_t op1, size_t vl) { vbool64_t test_vmsbf_m_b64(vbool64_t op1, size_t vl) {
return vmsbf_m_b64(op1, vl); return vmsbf_m_b64(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsbf_m_b1_m( // CHECK-RV64-LABEL: @test_vmsbf_m_b1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1.i64(<vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
// //
vbool1_t test_vmsbf_m_b1_m(vbool1_t mask, vbool1_t maskedoff, vbool1_t op1, vbool1_t test_vmsbf_m_b1_m(vbool1_t mask, vbool1_t maskedoff, vbool1_t op1,
size_t vl) { size_t vl) {
return vmsbf_m_b1_m(mask, maskedoff, op1, vl); return vmsbf_m_b1_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsbf_m_b2_m( // CHECK-RV64-LABEL: @test_vmsbf_m_b2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
// //
vbool2_t test_vmsbf_m_b2_m(vbool2_t mask, vbool2_t maskedoff, vbool2_t op1, vbool2_t test_vmsbf_m_b2_m(vbool2_t mask, vbool2_t maskedoff, vbool2_t op1,
size_t vl) { size_t vl) {
return vmsbf_m_b2_m(mask, maskedoff, op1, vl); return vmsbf_m_b2_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsbf_m_b4_m( // CHECK-RV64-LABEL: @test_vmsbf_m_b4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
// //
vbool4_t test_vmsbf_m_b4_m(vbool4_t mask, vbool4_t maskedoff, vbool4_t op1, vbool4_t test_vmsbf_m_b4_m(vbool4_t mask, vbool4_t maskedoff, vbool4_t op1,
size_t vl) { size_t vl) {
return vmsbf_m_b4_m(mask, maskedoff, op1, vl); return vmsbf_m_b4_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsbf_m_b8_m( // CHECK-RV64-LABEL: @test_vmsbf_m_b8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
// //
vbool8_t test_vmsbf_m_b8_m(vbool8_t mask, vbool8_t maskedoff, vbool8_t op1, vbool8_t test_vmsbf_m_b8_m(vbool8_t mask, vbool8_t maskedoff, vbool8_t op1,
size_t vl) { size_t vl) {
return vmsbf_m_b8_m(mask, maskedoff, op1, vl); return vmsbf_m_b8_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsbf_m_b16_m( // CHECK-RV64-LABEL: @test_vmsbf_m_b16_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
// //
vbool16_t test_vmsbf_m_b16_m(vbool16_t mask, vbool16_t maskedoff, vbool16_t op1, vbool16_t test_vmsbf_m_b16_m(vbool16_t mask, vbool16_t maskedoff, vbool16_t op1,
size_t vl) { size_t vl) {
return vmsbf_m_b16_m(mask, maskedoff, op1, vl); return vmsbf_m_b16_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsbf_m_b32_m( // CHECK-RV64-LABEL: @test_vmsbf_m_b32_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
// //
vbool32_t test_vmsbf_m_b32_m(vbool32_t mask, vbool32_t maskedoff, vbool32_t op1, vbool32_t test_vmsbf_m_b32_m(vbool32_t mask, vbool32_t maskedoff, vbool32_t op1,
size_t vl) { size_t vl) {
return vmsbf_m_b32_m(mask, maskedoff, op1, vl); return vmsbf_m_b32_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsbf_m_b64_m( // CHECK-RV64-LABEL: @test_vmsbf_m_b64_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
// //
vbool64_t test_vmsbf_m_b64_m(vbool64_t mask, vbool64_t maskedoff, vbool64_t op1, vbool64_t test_vmsbf_m_b64_m(vbool64_t mask, vbool64_t maskedoff, vbool64_t op1,
size_t vl) { size_t vl) {
return vmsbf_m_b64_m(mask, maskedoff, op1, vl); return vmsbf_m_b64_m(mask, maskedoff, op1, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vmsif.c

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
// //
vbool64_t test_vmsif_m_b64(vbool64_t op1, size_t vl) { vbool64_t test_vmsif_m_b64(vbool64_t op1, size_t vl) {
return vmsif_m_b64(op1, vl); return vmsif_m_b64(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsif_m_b1_m( // CHECK-RV64-LABEL: @test_vmsif_m_b1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1.i64(<vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
// //
vbool1_t test_vmsif_m_b1_m(vbool1_t mask, vbool1_t maskedoff, vbool1_t op1, vbool1_t test_vmsif_m_b1_m(vbool1_t mask, vbool1_t maskedoff, vbool1_t op1,
size_t vl) { size_t vl) {
return vmsif_m_b1_m(mask, maskedoff, op1, vl); return vmsif_m_b1_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsif_m_b2_m( // CHECK-RV64-LABEL: @test_vmsif_m_b2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
// //
vbool2_t test_vmsif_m_b2_m(vbool2_t mask, vbool2_t maskedoff, vbool2_t op1, vbool2_t test_vmsif_m_b2_m(vbool2_t mask, vbool2_t maskedoff, vbool2_t op1,
size_t vl) { size_t vl) {
return vmsif_m_b2_m(mask, maskedoff, op1, vl); return vmsif_m_b2_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsif_m_b4_m( // CHECK-RV64-LABEL: @test_vmsif_m_b4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
// //
vbool4_t test_vmsif_m_b4_m(vbool4_t mask, vbool4_t maskedoff, vbool4_t op1, vbool4_t test_vmsif_m_b4_m(vbool4_t mask, vbool4_t maskedoff, vbool4_t op1,
size_t vl) { size_t vl) {
return vmsif_m_b4_m(mask, maskedoff, op1, vl); return vmsif_m_b4_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsif_m_b8_m( // CHECK-RV64-LABEL: @test_vmsif_m_b8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
// //
vbool8_t test_vmsif_m_b8_m(vbool8_t mask, vbool8_t maskedoff, vbool8_t op1, vbool8_t test_vmsif_m_b8_m(vbool8_t mask, vbool8_t maskedoff, vbool8_t op1,
size_t vl) { size_t vl) {
return vmsif_m_b8_m(mask, maskedoff, op1, vl); return vmsif_m_b8_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsif_m_b16_m( // CHECK-RV64-LABEL: @test_vmsif_m_b16_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
// //
vbool16_t test_vmsif_m_b16_m(vbool16_t mask, vbool16_t maskedoff, vbool16_t op1, vbool16_t test_vmsif_m_b16_m(vbool16_t mask, vbool16_t maskedoff, vbool16_t op1,
size_t vl) { size_t vl) {
return vmsif_m_b16_m(mask, maskedoff, op1, vl); return vmsif_m_b16_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsif_m_b32_m( // CHECK-RV64-LABEL: @test_vmsif_m_b32_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
// //
vbool32_t test_vmsif_m_b32_m(vbool32_t mask, vbool32_t maskedoff, vbool32_t op1, vbool32_t test_vmsif_m_b32_m(vbool32_t mask, vbool32_t maskedoff, vbool32_t op1,
size_t vl) { size_t vl) {
return vmsif_m_b32_m(mask, maskedoff, op1, vl); return vmsif_m_b32_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsif_m_b64_m( // CHECK-RV64-LABEL: @test_vmsif_m_b64_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
// //
vbool64_t test_vmsif_m_b64_m(vbool64_t mask, vbool64_t maskedoff, vbool64_t op1, vbool64_t test_vmsif_m_b64_m(vbool64_t mask, vbool64_t maskedoff, vbool64_t op1,
size_t vl) { size_t vl) {
return vmsif_m_b64_m(mask, maskedoff, op1, vl); return vmsif_m_b64_m(mask, maskedoff, op1, vl);
} }

clang/test/CodeGen/RISCV/rvv-intrinsics/vmsof.c

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
// //
vbool64_t test_vmsof_m_b64(vbool64_t op1, size_t vl) { vbool64_t test_vmsof_m_b64(vbool64_t op1, size_t vl) {
return vmsof_m_b64(op1, vl); return vmsof_m_b64(op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsof_m_b1_m( // CHECK-RV64-LABEL: @test_vmsof_m_b1_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1.i64(<vscale x 64 x i1> [[MASKEDOFF:%.*]], <vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]]
// //
vbool1_t test_vmsof_m_b1_m(vbool1_t mask, vbool1_t maskedoff, vbool1_t op1, vbool1_t test_vmsof_m_b1_m(vbool1_t mask, vbool1_t maskedoff, vbool1_t op1,
size_t vl) { size_t vl) {
return vmsof_m_b1_m(mask, maskedoff, op1, vl); return vmsof_m_b1_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsof_m_b2_m( // CHECK-RV64-LABEL: @test_vmsof_m_b2_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1.i64(<vscale x 32 x i1> [[MASKEDOFF:%.*]], <vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]]
// //
vbool2_t test_vmsof_m_b2_m(vbool2_t mask, vbool2_t maskedoff, vbool2_t op1, vbool2_t test_vmsof_m_b2_m(vbool2_t mask, vbool2_t maskedoff, vbool2_t op1,
size_t vl) { size_t vl) {
return vmsof_m_b2_m(mask, maskedoff, op1, vl); return vmsof_m_b2_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsof_m_b4_m( // CHECK-RV64-LABEL: @test_vmsof_m_b4_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1.i64(<vscale x 16 x i1> [[MASKEDOFF:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]]
// //
vbool4_t test_vmsof_m_b4_m(vbool4_t mask, vbool4_t maskedoff, vbool4_t op1, vbool4_t test_vmsof_m_b4_m(vbool4_t mask, vbool4_t maskedoff, vbool4_t op1,
size_t vl) { size_t vl) {
return vmsof_m_b4_m(mask, maskedoff, op1, vl); return vmsof_m_b4_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsof_m_b8_m( // CHECK-RV64-LABEL: @test_vmsof_m_b8_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1.i64(<vscale x 8 x i1> [[MASKEDOFF:%.*]], <vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]]
// //
vbool8_t test_vmsof_m_b8_m(vbool8_t mask, vbool8_t maskedoff, vbool8_t op1, vbool8_t test_vmsof_m_b8_m(vbool8_t mask, vbool8_t maskedoff, vbool8_t op1,
size_t vl) { size_t vl) {
return vmsof_m_b8_m(mask, maskedoff, op1, vl); return vmsof_m_b8_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsof_m_b16_m( // CHECK-RV64-LABEL: @test_vmsof_m_b16_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1.i64(<vscale x 4 x i1> [[MASKEDOFF:%.*]], <vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]]
// //
vbool16_t test_vmsof_m_b16_m(vbool16_t mask, vbool16_t maskedoff, vbool16_t op1, vbool16_t test_vmsof_m_b16_m(vbool16_t mask, vbool16_t maskedoff, vbool16_t op1,
size_t vl) { size_t vl) {
return vmsof_m_b16_m(mask, maskedoff, op1, vl); return vmsof_m_b16_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsof_m_b32_m( // CHECK-RV64-LABEL: @test_vmsof_m_b32_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1.i64(<vscale x 2 x i1> [[MASKEDOFF:%.*]], <vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]]
// //
vbool32_t test_vmsof_m_b32_m(vbool32_t mask, vbool32_t maskedoff, vbool32_t op1, vbool32_t test_vmsof_m_b32_m(vbool32_t mask, vbool32_t maskedoff, vbool32_t op1,
size_t vl) { size_t vl) {
return vmsof_m_b32_m(mask, maskedoff, op1, vl); return vmsof_m_b32_m(mask, maskedoff, op1, vl);
} }
// CHECK-RV64-LABEL: @test_vmsof_m_b64_m( // CHECK-RV64-LABEL: @test_vmsof_m_b64_m(
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1.i64(<vscale x 1 x i1> [[MASKEDOFF:%.*]], <vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]]
// //
vbool64_t test_vmsof_m_b64_m(vbool64_t mask, vbool64_t maskedoff, vbool64_t op1, vbool64_t test_vmsof_m_b64_m(vbool64_t mask, vbool64_t maskedoff, vbool64_t op1,
size_t vl) { size_t vl) {
return vmsof_m_b64_m(mask, maskedoff, op1, vl); return vmsof_m_b64_m(mask, maskedoff, op1, vl);
} }

llvm/include/llvm/IR/IntrinsicsRISCV.td

Show First 20 Lines • Show All 566 Lines • ▼ Show 20 Lines class RISCVCompareNoMask
: Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], : Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
[llvm_anyvector_ty, llvm_any_ty, llvm_anyint_ty], [llvm_anyvector_ty, llvm_any_ty, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let ScalarOperand = 1; let ScalarOperand = 1;
let VLOperand = 2; let VLOperand = 2;
} }
// For binary operations with mask type output with mask. // For binary operations with mask type output with mask.
// Output: (mask type output) // Output: (mask type output)
// Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl) // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl, policy)
class RISCVCompareMask class RISCVCompareMask
: Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], : Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyvector_ty, llvm_any_ty, llvm_anyvector_ty, llvm_any_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
[IntrNoMem]>, RISCVVIntrinsic { llvm_anyint_ty, LLVMMatchType<2>],
[IntrNoMem, ImmArg<ArgIndex<5>>]>, RISCVVIntrinsic {
let ScalarOperand = 2; let ScalarOperand = 2;
let VLOperand = 4; let VLOperand = 4;
} }
// For FP classify operations. // For FP classify operations.
// Output: (bit mask type output) // Output: (bit mask type output)
// Input: (passthru, vector_in, vl) // Input: (passthru, vector_in, vl)
class RISCVClassifyNoMask class RISCVClassifyNoMask
: Intrinsic<[LLVMVectorOfBitcastsToInt<0>], : Intrinsic<[LLVMVectorOfBitcastsToInt<0>],
[LLVMVectorOfBitcastsToInt<0>, llvm_anyvector_ty, [LLVMVectorOfBitcastsToInt<0>, llvm_anyvector_ty,
llvm_anyint_ty], llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 1; let VLOperand = 1;
} }
// For FP classify operations with mask. // For FP classify operations with mask.
// Output: (bit mask type output) // Output: (bit mask type output)
// Input: (maskedoff, vector_in, mask, vl, policy) // Input: (maskedoff, vector_in, mask, vl, policy)
class RISCVClassifyMask class RISCVClassifyMask
: Intrinsic<[LLVMVectorOfBitcastsToInt<0>], : Intrinsic<[LLVMVectorOfBitcastsToInt<0>],
[LLVMVectorOfBitcastsToInt<0>, llvm_anyvector_ty, [LLVMVectorOfBitcastsToInt<0>, llvm_anyvector_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty, LLVMMatchType<1>], llvm_anyint_ty, LLVMMatchType<1>],
[IntrNoMem, ImmArg<ArgIndex<4>>]>, RISCVVIntrinsic { [IntrNoMem, ImmArg<ArgIndex<4>>]>, RISCVVIntrinsic {
let VLOperand = 3; let VLOperand = 3;
} }
// For Saturating binary operations. // For Saturating binary operations.
// The destination vector type is the same as first source vector. // The destination vector type is the same as first source vector.
// Input: (passthru, vector_in, vector_in/scalar_in, vl) // Input: (passthru, vector_in, vector_in/scalar_in, vl)
class RISCVSaturatingBinaryAAXNoMask class RISCVSaturatingBinaryAAXNoMask
▲ Show 20 Lines • Show All 184 Lines • ▼ Show 20 Lineslet TargetPrefix = "riscv" in {
class RISCVUnaryNoMask class RISCVUnaryNoMask
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_anyint_ty], [LLVMMatchType<0>, llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic { [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 1; let VLOperand = 1;
} }
// For mask unary operations with mask type in/out with mask // For mask unary operations with mask type in/out with mask
// Output: (mask type output) // Output: (mask type output)
// Input: (mask type maskedoff, mask type vector_in, mask, vl) // Input: (mask type maskedoff, mask type vector_in, mask, vl, policy)
class RISCVMaskUnaryMOutMask class RISCVMaskUnaryMOutMask
: Intrinsic<[llvm_anyint_ty], : Intrinsic<[llvm_anyint_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, [LLVMMatchType<0>, LLVMMatchType<0>,
LLVMMatchType<0>, llvm_anyint_ty], LLVMMatchType<0>, llvm_anyint_ty, LLVMMatchType<1>],
[IntrNoMem]>, RISCVVIntrinsic { [ImmArg<ArgIndex<4>>, IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 3; let VLOperand = 3;
} }
// Output: (vector) // Output: (vector)
// Input: (vl) // Input: (vl)
class RISCVNullaryIntrinsic class RISCVNullaryIntrinsic
: Intrinsic<[llvm_anyvector_ty], : Intrinsic<[llvm_anyvector_ty],
[llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic { [llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 1; let VLOperand = 1;
▲ Show 20 Lines • Show All 793 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Show First 20 Lines • Show All 1,103 Lines • ▼ Show 20 Lines#undef CASE_VMXOR_VMANDN_VMOR_OPCODES
// Mask needs to be copied to V0. // Mask needs to be copied to V0.
SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL,
RISCV::V0, Mask, SDValue()); RISCV::V0, Mask, SDValue());
SDValue Glue = Chain.getValue(1); SDValue Glue = Chain.getValue(1);
SDValue V0 = CurDAG->getRegister(RISCV::V0, VT); SDValue V0 = CurDAG->getRegister(RISCV::V0, VT);
// Otherwise use // Otherwise use
// vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0 // vmslt{u}.vx vd, va, x, v0.t; vmxor.mm vd, vd, v0
SDValue Cmp = SDValue( SDValue Policy = Node->getOperand(6);
CurDAG->getMachineNode(VMSLTMaskOpcode, DL, VT, SDValue Cmp = SDValue(CurDAG->getMachineNode(VMSLTMaskOpcode, DL, VT,
{MaskedOff, Src1, Src2, V0, VL, SEW, Glue}), {MaskedOff, Src1, Src2, V0,
VL, SEW, Policy, Glue}),
0); 0);
ReplaceNode(Node, CurDAG->getMachineNode(VMXOROpcode, DL, VT, ReplaceNode(Node, CurDAG->getMachineNode(VMXOROpcode, DL, VT,
{Cmp, Mask, VL, MaskSEW})); {Cmp, Mask, VL, MaskSEW}));
return; return;
} }
case Intrinsic::riscv_vsetvli_opt: case Intrinsic::riscv_vsetvli_opt:
case Intrinsic::riscv_vsetvlimax_opt: case Intrinsic::riscv_vsetvlimax_opt:
return selectVSETVLI(Node); return selectVSETVLI(Node);
} }
▲ Show 20 Lines • Show All 1,173 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 961 Lines • ▼ Show 20 Linesclass VPseudoUnaryNoMaskTU<DAGOperand RetClass, VReg OpClass, string Constraint = ""> :
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret; let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1; let HasVLOp = 1;
let HasSEWOp = 1; let HasSEWOp = 1;
let HasDummyMask = 1; let HasDummyMask = 1;
let HasMergeOp = 1; let HasMergeOp = 1;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
} }
class VPseudoUnaryMask<VReg RetClass, VReg OpClass, string Constraint = ""> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
let UsesMaskPolicy = 1;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
}
class VPseudoUnaryMaskTA<VReg RetClass, VReg OpClass, string Constraint = ""> : class VPseudoUnaryMaskTA<VReg RetClass, VReg OpClass, string Constraint = ""> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd), Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2, (ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
RISCVVPseudo { RISCVVPseudo {
let mayLoad = 0; let mayLoad = 0;
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
▲ Show 20 Lines • Show All 185 Lines • ▼ Show 20 Lines
// Like VPseudoBinaryMask, but output can be V0. // Like VPseudoBinaryMask, but output can be V0.
class VPseudoBinaryMOutMask<VReg RetClass, class VPseudoBinaryMOutMask<VReg RetClass,
RegisterClass Op1Class, RegisterClass Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
string Constraint> : string Constraint> :
Pseudo<(outs RetClass:$rd), Pseudo<(outs RetClass:$rd),
(ins RetClass:$merge, (ins RetClass:$merge,
Op1Class:$rs2, Op2Class:$rs1, Op1Class:$rs2, Op2Class:$rs1,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
RISCVVPseudo { RISCVVPseudo {
let mayLoad = 0; let mayLoad = 0;
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret; let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1; let HasVLOp = 1;
let HasSEWOp = 1; let HasSEWOp = 1;
let HasMergeOp = 1; let HasMergeOp = 1;
// FIXME: In current design, we would not change the mask policy, so let HasVecPolicyOp = 1;
// UsesMaskPolicy is false. We could fix after add the policy operand.
let UsesMaskPolicy = 0; let UsesMaskPolicy = 0;
let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst); let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
} }
// Special version of VPseudoBinaryMask where we pretend the first source is // Special version of VPseudoBinaryMask where we pretend the first source is
// tied to the destination so we can workaround the earlyclobber constraint. // tied to the destination so we can workaround the earlyclobber constraint.
// This allows maskedoff and rs2 to be the same register. // This allows maskedoff and rs2 to be the same register.
class VPseudoTiedBinaryMask<VReg RetClass, class VPseudoTiedBinaryMask<VReg RetClass,
▲ Show 20 Lines • Show All 486 Lines • ▼ Show 20 Lines
multiclass VPseudoVSFS_M { multiclass VPseudoVSFS_M {
defvar constraint = "@earlyclobber $rd"; defvar constraint = "@earlyclobber $rd";
foreach mti = AllMasks in foreach mti = AllMasks in
{ {
let VLMul = mti.LMul.value in { let VLMul = mti.LMul.value in {
def "_M_" # mti.BX : VPseudoUnaryNoMask<VR, VR, constraint>, def "_M_" # mti.BX : VPseudoUnaryNoMask<VR, VR, constraint>,
Sched<[WriteVMSFSV, ReadVMSFSV, ReadVMask]>; Sched<[WriteVMSFSV, ReadVMSFSV, ReadVMask]>;
def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMask<VR, VR, constraint>, let ForceTailAgnostic = 1 in
def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMaskTA<VR, VR, constraint>,
Sched<[WriteVMSFSV, ReadVMSFSV, ReadVMask]>; Sched<[WriteVMSFSV, ReadVMSFSV, ReadVMask]>;
} }
} }
} }
multiclass VPseudoVID_V { multiclass VPseudoVID_V {
foreach m = MxList in { foreach m = MxList in {
let VLMul = m.value in { let VLMul = m.value in {
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
multiclass VPseudoBinaryM<VReg RetClass, multiclass VPseudoBinaryM<VReg RetClass,
VReg Op1Class, VReg Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = ""> { string Constraint = ""> {
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class, def "_" # MInfo.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class,
Constraint>; Constraint>;
let ForceTailAgnostic = true in
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class, def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class,
Op2Class, Constraint>; Op2Class, Constraint>;
} }
} }
multiclass VPseudoBinaryEmul<VReg RetClass, multiclass VPseudoBinaryEmul<VReg RetClass,
VReg Op1Class, VReg Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
▲ Show 20 Lines • Show All 696 Lines • ▼ Show 20 Linesmulticlass VPseudoTernaryNoMaskNoPolicy<VReg RetClass,
RegisterClass Op1Class, RegisterClass Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = ""> { string Constraint = ""> {
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoTernaryNoMask<RetClass, Op1Class, Op2Class, Constraint>; def "_" # MInfo.MX : VPseudoTernaryNoMask<RetClass, Op1Class, Op2Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
Constraint>; Constraint>;
} }
} }
multiclass VPseudoTernaryWithPolicy<VReg RetClass, multiclass VPseudoTernaryWithPolicy<VReg RetClass,
RegisterClass Op1Class, RegisterClass Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = "", string Constraint = "",
bit Commutable = 0> { bit Commutable = 0> {
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
let isCommutable = Commutable in let isCommutable = Commutable in
def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>; def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>; def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>;
} }
} }
multiclass VPseudoTernaryV_VV_AAXA<string Constraint = "", multiclass VPseudoTernaryV_VV_AAXA<string Constraint = "",
list<LMULInfo> mxlist = MxList> { list<LMULInfo> mxlist = MxList> {
foreach m = mxlist in { foreach m = mxlist in {
defm _VV : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, m.vrclass, m, defm _VV : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, m.vrclass, m,
Constraint, /*Commutable*/1>; Constraint, /*Commutable*/1>;
} }
▲ Show 20 Lines • Show All 383 Lines • ▼ Show 20 Lines Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
(result_type result_reg_class:$merge), (result_type result_reg_class:$merge),
(op2_type op2_reg_class:$rs2), (op2_type op2_reg_class:$rs2),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_TU") (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_TU")
(result_type result_reg_class:$merge), (result_type result_reg_class:$merge),
(op2_type op2_reg_class:$rs2), (op2_type op2_reg_class:$rs2),
GPR:$vl, sew)>; GPR:$vl, sew)>;
class VPatUnaryMask<string intrinsic_name,
string inst,
string kind,
ValueType result_type,
ValueType op2_type,
ValueType mask_type,
int sew,
LMULInfo vlmul,
VReg result_reg_class,
VReg op2_reg_class> :
Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")
(result_type result_reg_class:$merge),
(op2_type op2_reg_class:$rs2),
(mask_type V0),
VLOpFrag)),
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX#"_MASK")
(result_type result_reg_class:$merge),
(op2_type op2_reg_class:$rs2),
(mask_type V0), GPR:$vl, sew)>;
class VPatUnaryMaskTA<string intrinsic_name, class VPatUnaryMaskTA<string intrinsic_name,
string inst, string inst,
string kind, string kind,
ValueType result_type, ValueType result_type,
ValueType op2_type, ValueType op2_type,
ValueType mask_type, ValueType mask_type,
int sew, int sew,
LMULInfo vlmul, LMULInfo vlmul,
Show All 21 Lines
class VPatMaskUnaryMask<string intrinsic_name, class VPatMaskUnaryMask<string intrinsic_name,
string inst, string inst,
MTypeInfo mti> : MTypeInfo mti> :
Pat<(mti.Mask (!cast<Intrinsic>(intrinsic_name#"_mask") Pat<(mti.Mask (!cast<Intrinsic>(intrinsic_name#"_mask")
(mti.Mask VR:$merge), (mti.Mask VR:$merge),
(mti.Mask VR:$rs2), (mti.Mask VR:$rs2),
(mti.Mask V0), (mti.Mask V0),
VLOpFrag)), VLOpFrag, (XLenVT timm:$policy))),
(!cast<Instruction>(inst#"_M_"#mti.BX#"_MASK") (!cast<Instruction>(inst#"_M_"#mti.BX#"_MASK")
(mti.Mask VR:$merge), (mti.Mask VR:$merge),
(mti.Mask VR:$rs2), (mti.Mask VR:$rs2),
(mti.Mask V0), GPR:$vl, mti.Log2SEW)>; (mti.Mask V0), GPR:$vl, mti.Log2SEW, (XLenVT timm:$policy))>;
class VPatUnaryAnyMask<string intrinsic, class VPatUnaryAnyMask<string intrinsic,
string inst, string inst,
string kind, string kind,
ValueType result_type, ValueType result_type,
ValueType op1_type, ValueType op1_type,
ValueType mask_type, ValueType mask_type,
int sew, int sew,
▲ Show 20 Lines • Show All 139 Lines • ▼ Show 20 Linesclass VPatBinaryMaskSwapped<string intrinsic_name,
VReg result_reg_class, VReg result_reg_class,
VReg op1_reg_class, VReg op1_reg_class,
DAGOperand op2_kind> : DAGOperand op2_kind> :
Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask") Pat<(result_type (!cast<Intrinsic>(intrinsic_name#"_mask")
(result_type result_reg_class:$merge), (result_type result_reg_class:$merge),
(op2_type op2_kind:$rs2), (op2_type op2_kind:$rs2),
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
(mask_type V0), (mask_type V0),
VLOpFrag)), VLOpFrag, (XLenVT timm:$policy))),
(!cast<Instruction>(inst#"_MASK") (!cast<Instruction>(inst#"_MASK")
(result_type result_reg_class:$merge), (result_type result_reg_class:$merge),
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2), (op2_type op2_kind:$rs2),
(mask_type V0), GPR:$vl, sew)>; (mask_type V0), GPR:$vl, sew, (XLenVT timm:$policy))>;
class VPatTiedBinaryNoMask<string intrinsic_name, class VPatTiedBinaryNoMask<string intrinsic_name,
string inst, string inst,
ValueType result_type, ValueType result_type,
ValueType op2_type, ValueType op2_type,
int sew, int sew,
VReg result_reg_class, VReg result_reg_class,
DAGOperand op2_kind> : DAGOperand op2_kind> :
▲ Show 20 Lines • Show All 255 Lines • ▼ Show 20 Linesmulticlass VPatBinaryM<string intrinsic,
ValueType mask_type, ValueType mask_type,
int sew, int sew,
VReg result_reg_class, VReg result_reg_class,
VReg op1_reg_class, VReg op1_reg_class,
DAGOperand op2_kind> DAGOperand op2_kind>
{ {
def : VPatBinaryM<intrinsic, inst, result_type, op1_type, op2_type, def : VPatBinaryM<intrinsic, inst, result_type, op1_type, op2_type,
sew, op1_reg_class, op2_kind>; sew, op1_reg_class, op2_kind>;
def : VPatBinaryMask<intrinsic, inst, result_type, op1_type, op2_type, def : VPatBinaryMaskTA<intrinsic, inst, result_type, op1_type, op2_type,
mask_type, sew, result_reg_class, op1_reg_class, mask_type, sew, result_reg_class, op1_reg_class,
op2_kind>; op2_kind>;
} }
multiclass VPatBinaryTA<string intrinsic, multiclass VPatBinaryTA<string intrinsic,
string inst, string inst,
ValueType result_type, ValueType result_type,
ValueType op1_type, ValueType op1_type,
ValueType op2_type, ValueType op2_type,
ValueType mask_type, ValueType mask_type,
▲ Show 20 Lines • Show All 795 Lines • ▼ Show 20 Lines def : Pat<(vti.Mask (Intr (vti.Vector vti.RegClass:$rs1),
(Pseudo vti.RegClass:$rs1, (DecImm ImmType:$rs2), (Pseudo vti.RegClass:$rs1, (DecImm ImmType:$rs2),
GPR:$vl, vti.Log2SEW)>; GPR:$vl, vti.Log2SEW)>;
defvar IntrMask = !cast<Intrinsic>(intrinsic # "_mask"); defvar IntrMask = !cast<Intrinsic>(intrinsic # "_mask");
defvar PseudoMask = !cast<Instruction>(inst#"_VI_"#vti.LMul.MX#"_MASK"); defvar PseudoMask = !cast<Instruction>(inst#"_VI_"#vti.LMul.MX#"_MASK");
def : Pat<(vti.Mask (IntrMask (vti.Mask VR:$merge), def : Pat<(vti.Mask (IntrMask (vti.Mask VR:$merge),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
(vti.Scalar ImmType:$rs2), (vti.Scalar ImmType:$rs2),
(vti.Mask V0), (vti.Mask V0),
VLOpFrag)), VLOpFrag, (XLenVT timm:$policy))),
(PseudoMask VR:$merge, vti.RegClass:$rs1, (DecImm ImmType:$rs2), (PseudoMask VR:$merge, vti.RegClass:$rs1, (DecImm ImmType:$rs2),
(vti.Mask V0), GPR:$vl, vti.Log2SEW)>; (vti.Mask V0), GPR:$vl, vti.Log2SEW, timm:$policy)>;
} }
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Pseudo instructions // Pseudo instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasVInstructions] in { let Predicates = [HasVInstructions] in {
▲ Show 20 Lines • Show All 1,269 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/masked-tama.ll

Show First 20 Lines • Show All 1,633 Lines • ▼ Show 20 Linesentry:
%a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
<vscale x 1 x i8> undef, <vscale x 1 x i8> undef,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
iXLen %2, iXLen 3) iXLen %2, iXLen 3)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
<vscale x 1 x i1>,
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vmseq_mask_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32-NEXT: vmseq.vv v0, v8, v9, v0.t
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vmseq_mask_nxv1i64_i64:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; RV64-NEXT: vmseq.vx v0, v8, a0, v0.t
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
<vscale x 1 x i1> undef,
<vscale x 1 x i64> %0,
i64 %1,
<vscale x 1 x i1> %2,
iXLen %3, iXLen 3)
ret <vscale x 1 x i1> %a
}
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1>,
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i8_i8(<vscale x 1 x i8> %0, i8 %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; RV32-NEXT: vmslt.vx v8, v8, a0, v0.t
; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV32-NEXT: vmxor.mm v0, v8, v0
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
; RV64-NEXT: vmslt.vx v8, v8, a0, v0.t
; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV64-NEXT: vmxor.mm v0, v8, v0
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1> undef,
<vscale x 1 x i8> %0,
i8 %1,
<vscale x 1 x i1> %2,
iXLen %3, iXLen 3)
ret <vscale x 1 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
<vscale x 64 x i1>,
iXLen, iXLen);
define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
; RV32-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vmv1r.v v9, v0
; RV32-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v8
; RV32-NEXT: vmsbf.m v8, v9, v0.t
; RV32-NEXT: vmv1r.v v0, v8
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vmv1r.v v9, v0
; RV64-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: vmsbf.m v8, v9, v0.t
; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
<vscale x 64 x i1> undef,
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
iXLen %2, iXLen 3)
ret <vscale x 64 x i1> %a
}

llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll

Show First 20 Lines • Show All 1,590 Lines • ▼ Show 20 Linesentry:
%a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
iXLen %2, iXLen 1) iXLen %2, iXLen 1)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
<vscale x 1 x i1>,
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmseq_mask_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v11, (a0), zero
; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: vmv1r.v v0, v9
; RV32-NEXT: vmseq.vv v10, v8, v11, v0.t
; RV32-NEXT: vmv.v.v v0, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vmseq_mask_nxv1i64_i64:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vmv1r.v v10, v0
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; RV64-NEXT: vmv1r.v v0, v9
; RV64-NEXT: vmseq.vx v10, v8, a0, v0.t
; RV64-NEXT: vmv.v.v v0, v10
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
<vscale x 1 x i1> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a
}
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1>,
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; RV32-NEXT: vmv1r.v v0, v9
; RV32-NEXT: vmslt.vx v10, v8, a0, v0.t
; RV32-NEXT: vmxor.mm v0, v10, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vmv1r.v v10, v0
; RV64-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; RV64-NEXT: vmv1r.v v0, v9
; RV64-NEXT: vmslt.vx v10, v8, a0, v0.t
; RV64-NEXT: vmxor.mm v0, v10, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1> %0,
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
<vscale x 64 x i1>,
iXLen, iXLen);
define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; RV32-NEXT: vmv1r.v v0, v9
; RV32-NEXT: vmsbf.m v10, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v10
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vmv1r.v v10, v0
; RV64-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; RV64-NEXT: vmv1r.v v0, v9
; RV64-NEXT: vmsbf.m v10, v8, v0.t
; RV64-NEXT: vmv1r.v v0, v10
; RV64-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
<vscale x 64 x i1> %2,
iXLen %3, iXLen 1)
ret <vscale x 64 x i1> %a
}

llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll

Show First 20 Lines • Show All 1,590 Lines • ▼ Show 20 Linesentry:
%a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
iXLen %2, iXLen 2) iXLen %2, iXLen 2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
<vscale x 1 x i1>,
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmseq_mask_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v11, (a0), zero
; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, ma
; RV32-NEXT: vmv1r.v v0, v9
; RV32-NEXT: vmseq.vv v10, v8, v11, v0.t
; RV32-NEXT: vmv1r.v v0, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vmseq_mask_nxv1i64_i64:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vmv1r.v v10, v0
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, ma
; RV64-NEXT: vmv1r.v v0, v9
; RV64-NEXT: vmseq.vx v10, v8, a0, v0.t
; RV64-NEXT: vmv1r.v v0, v10
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
<vscale x 1 x i1> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 2)
ret <vscale x 1 x i1> %a
}
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1>,
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: vsetvli zero, a1, e8, mf8, tu, ma
; RV32-NEXT: vmv1r.v v0, v9
; RV32-NEXT: vmslt.vx v10, v8, a0, v0.t
; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV32-NEXT: vmxor.mm v0, v10, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vmv1r.v v10, v0
; RV64-NEXT: vsetvli zero, a1, e8, mf8, tu, ma
; RV64-NEXT: vmv1r.v v0, v9
; RV64-NEXT: vmslt.vx v10, v8, a0, v0.t
; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV64-NEXT: vmxor.mm v0, v10, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1> %0,
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 2)
ret <vscale x 1 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
<vscale x 64 x i1>,
iXLen, iXLen);
define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: vsetvli zero, a0, e8, m8, tu, ma
; RV32-NEXT: vmv1r.v v0, v9
; RV32-NEXT: vmsbf.m v10, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v10
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vmv1r.v v10, v0
; RV64-NEXT: vsetvli zero, a0, e8, m8, tu, ma
; RV64-NEXT: vmv1r.v v0, v9
; RV64-NEXT: vmsbf.m v10, v8, v0.t
; RV64-NEXT: vmv1r.v v0, v10
; RV64-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
<vscale x 64 x i1> %2,
iXLen %3, iXLen 2)
ret <vscale x 64 x i1> %a
}

llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll

Show First 20 Lines • Show All 1,590 Lines • ▼ Show 20 Linesentry:
%a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8( %a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
<vscale x 1 x i8> %0, <vscale x 1 x i8> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
iXLen %2, iXLen 0) iXLen %2, iXLen 0)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
<vscale x 1 x i1>,
<vscale x 1 x i64>,
i64,
<vscale x 1 x i1>,
iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmseq_mask_nxv1i64_i64:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vlse64.v v11, (a0), zero
; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: vsetvli zero, zero, e64, m1, tu, mu
; RV32-NEXT: vmv1r.v v0, v9
; RV32-NEXT: vmseq.vv v10, v8, v11, v0.t
; RV32-NEXT: vmv1r.v v0, v10
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vmseq_mask_nxv1i64_i64:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vmv1r.v v10, v0
; RV64-NEXT: vsetvli zero, a1, e64, m1, tu, mu
; RV64-NEXT: vmv1r.v v0, v9
; RV64-NEXT: vmseq.vx v10, v8, a0, v0.t
; RV64-NEXT: vmv1r.v v0, v10
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
<vscale x 1 x i1> %0,
<vscale x 1 x i64> %1,
i64 %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 0)
ret <vscale x 1 x i1> %a
}
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1>,
<vscale x 1 x i8>,
i8,
<vscale x 1 x i1>,
iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; RV32-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; RV32-NEXT: vmv1r.v v0, v9
; RV32-NEXT: vmslt.vx v10, v8, a0, v0.t
; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV32-NEXT: vmxor.mm v0, v10, v9
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vmv1r.v v10, v0
; RV64-NEXT: vsetvli zero, a1, e8, mf8, tu, mu
; RV64-NEXT: vmv1r.v v0, v9
; RV64-NEXT: vmslt.vx v10, v8, a0, v0.t
; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, mu
; RV64-NEXT: vmxor.mm v0, v10, v9
; RV64-NEXT: ret
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1> %0,
<vscale x 1 x i8> %1,
i8 %2,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 0)
ret <vscale x 1 x i1> %a
}
declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
<vscale x 64 x i1>,
iXLen, iXLen);
define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {
; RV32-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1:
; RV32: # %bb.0: # %entry
; RV32-NEXT: vmv1r.v v10, v0
; RV32-NEXT: vsetvli zero, a0, e8, m8, tu, mu
; RV32-NEXT: vmv1r.v v0, v9
; RV32-NEXT: vmsbf.m v10, v8, v0.t
; RV32-NEXT: vmv1r.v v0, v10
; RV32-NEXT: ret
;
; RV64-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1:
; RV64: # %bb.0: # %entry
; RV64-NEXT: vmv1r.v v10, v0
; RV64-NEXT: vsetvli zero, a0, e8, m8, tu, mu
; RV64-NEXT: vmv1r.v v0, v9
; RV64-NEXT: vmsbf.m v10, v8, v0.t
; RV64-NEXT: vmv1r.v v0, v10
; RV64-NEXT: ret
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
<vscale x 64 x i1> %2,
iXLen %3, iXLen 0)
ret <vscale x 64 x i1> %a
}

llvm/test/CodeGen/RISCV/rvv/vmfeq.ll

Show All 22 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16( declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmfeq.vv v8, v8, v9 ; CHECK-NEXT: vmfeq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x half> %3, <vscale x 1 x half> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16( declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16( declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmfeq.vv v8, v8, v9 ; CHECK-NEXT: vmfeq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x half> %3, <vscale x 2 x half> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16( declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16( declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmfeq.vv v8, v8, v9 ; CHECK-NEXT: vmfeq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x half> %3, <vscale x 4 x half> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16( declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16( declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmfeq.vv v14, v8, v10 ; CHECK-NEXT: vmfeq.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmfeq.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmfeq.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x half> %3, <vscale x 8 x half> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16( declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16( declare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmfeq.vv v20, v8, v12 ; CHECK-NEXT: vmfeq.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmfeq.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmfeq.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x half> %3, <vscale x 16 x half> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32( declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32( declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmfeq.vv v8, v8, v9 ; CHECK-NEXT: vmfeq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x float> %3, <vscale x 1 x float> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32( declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32( declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmfeq.vv v8, v8, v9 ; CHECK-NEXT: vmfeq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x float> %3, <vscale x 2 x float> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32( declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32( declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmfeq.vv v14, v8, v10 ; CHECK-NEXT: vmfeq.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmfeq.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmfeq.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x float> %3, <vscale x 4 x float> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32( declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32( declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmfeq.vv v20, v8, v12 ; CHECK-NEXT: vmfeq.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmfeq.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmfeq.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x float> %3, <vscale x 8 x float> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64( declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64( declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmfeq.vv v8, v8, v9 ; CHECK-NEXT: vmfeq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x double> %3, <vscale x 1 x double> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64( declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64( declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmfeq.vv v14, v8, v10 ; CHECK-NEXT: vmfeq.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmfeq.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmfeq.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x double> %3, <vscale x 2 x double> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64( declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64( declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmfeq.vv v20, v8, v12 ; CHECK-NEXT: vmfeq.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmfeq.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmfeq.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x double> %3, <vscale x 4 x double> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16( declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16( declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f16.f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
half %2, half %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16( declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16( declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f16_f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f16.f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
half %2, half %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16( declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16( declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f16_f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f16.f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
half %2, half %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16( declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16( declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f16_f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfeq.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmfeq.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f16.f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
half %2, half %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16( declare <vscale x 16 x i1> @llvm.riscv.vmfeq.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16( declare <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfeq_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv16f16_f16: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfeq.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmfeq.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfeq.mask.nxv16f16.f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
half %2, half %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32.f32( declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32( declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f32_f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f32.f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
float %2, float %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32.f32( declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32( declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f32_f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f32.f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
float %2, float %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32.f32( declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32( declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f32_f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfeq.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmfeq.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f32.f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
float %2, float %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32.f32( declare <vscale x 8 x i1> @llvm.riscv.vmfeq.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32( declare <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfeq_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f32_f32: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfeq.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmfeq.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfeq.mask.nxv8f32.f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
float %2, float %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64.f64( declare <vscale x 1 x i1> @llvm.riscv.vmfeq.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64.f64( declare <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64.f64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfeq_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f64_f64: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfeq.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64.f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfeq.mask.nxv1f64.f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
double %2, double %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64.f64( declare <vscale x 2 x i1> @llvm.riscv.vmfeq.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64.f64( declare <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64.f64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfeq_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f64_f64: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfeq.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmfeq.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64.f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfeq.mask.nxv2f64.f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
double %2, double %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64.f64( declare <vscale x 4 x i1> @llvm.riscv.vmfeq.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64.f64( declare <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64.f64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfeq_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f64_f64: ; CHECK-LABEL: intrinsic_vmfeq_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfeq.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmfeq.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64.f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfeq.mask.nxv4f64.f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
double %2, double %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmfge.ll

Show All 22 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16( declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmfle.vv v8, v9, v8 ; CHECK-NEXT: vmfle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x half> %3, <vscale x 1 x half> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16( declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16( declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmfle.vv v8, v9, v8 ; CHECK-NEXT: vmfle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x half> %3, <vscale x 2 x half> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16( declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16( declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmfle.vv v8, v9, v8 ; CHECK-NEXT: vmfle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x half> %3, <vscale x 4 x half> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16( declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16( declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmfle.vv v14, v10, v8 ; CHECK-NEXT: vmfle.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmfle.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmfle.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x half> %3, <vscale x 8 x half> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16( declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16( declare <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x i1> @intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmfle.vv v20, v12, v8 ; CHECK-NEXT: vmfle.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmfle.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmfle.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x half> %3, <vscale x 16 x half> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32( declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32( declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmfle.vv v8, v9, v8 ; CHECK-NEXT: vmfle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x float> %3, <vscale x 1 x float> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32( declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32( declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmfle.vv v8, v9, v8 ; CHECK-NEXT: vmfle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x float> %3, <vscale x 2 x float> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32( declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32( declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmfle.vv v14, v10, v8 ; CHECK-NEXT: vmfle.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmfle.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmfle.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x float> %3, <vscale x 4 x float> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32( declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32( declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmfle.vv v20, v12, v8 ; CHECK-NEXT: vmfle.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmfle.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmfle.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x float> %3, <vscale x 8 x float> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64( declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64( declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmfle.vv v8, v9, v8 ; CHECK-NEXT: vmfle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x double> %3, <vscale x 1 x double> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64( declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64( declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmfle.vv v14, v10, v8 ; CHECK-NEXT: vmfle.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmfle.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmfle.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x double> %3, <vscale x 2 x double> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64( declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64( declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmfle.vv v20, v12, v8 ; CHECK-NEXT: vmfle.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmfle.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmfle.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x double> %3, <vscale x 4 x double> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16( declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16( declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f16.f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
half %2, half %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16( declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16( declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f16_f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f16.f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
half %2, half %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16( declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16( declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f16_f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f16.f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
half %2, half %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16( declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16( declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f16_f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfge.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f16.f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
half %2, half %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16( declare <vscale x 16 x i1> @llvm.riscv.vmfge.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16( declare <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x i1> @intrinsic_vmfge_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfge_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv16f16_f16: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfge.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfge.mask.nxv16f16.f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
half %2, half %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32.f32( declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32( declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f32_f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f32.f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
float %2, float %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32.f32( declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32( declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f32_f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f32.f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
float %2, float %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32.f32( declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32( declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f32_f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfge.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f32.f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
float %2, float %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32.f32( declare <vscale x 8 x i1> @llvm.riscv.vmfge.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32( declare <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfge_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f32_f32: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfge.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfge.mask.nxv8f32.f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
float %2, float %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64.f64( declare <vscale x 1 x i1> @llvm.riscv.vmfge.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64.f64( declare <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64.f64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfge_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f64_f64: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64.f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfge.mask.nxv1f64.f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
double %2, double %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64.f64( declare <vscale x 2 x i1> @llvm.riscv.vmfge.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64.f64( declare <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64.f64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfge_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f64_f64: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfge.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64.f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfge.mask.nxv2f64.f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
double %2, double %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64.f64( declare <vscale x 4 x i1> @llvm.riscv.vmfge.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64.f64( declare <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64.f64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfge_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f64_f64: ; CHECK-LABEL: intrinsic_vmfge_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfge.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmfge.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64.f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfge.mask.nxv4f64.f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
double %2, double %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmfgt.ll

Show All 22 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16( declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmflt.vv v8, v9, v8 ; CHECK-NEXT: vmflt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x half> %3, <vscale x 1 x half> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16( declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16( declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmflt.vv v8, v9, v8 ; CHECK-NEXT: vmflt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x half> %3, <vscale x 2 x half> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16( declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16( declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmflt.vv v8, v9, v8 ; CHECK-NEXT: vmflt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x half> %3, <vscale x 4 x half> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16( declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16( declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmflt.vv v14, v10, v8 ; CHECK-NEXT: vmflt.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmflt.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmflt.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x half> %3, <vscale x 8 x half> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16( declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16( declare <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmflt.vv v20, v12, v8 ; CHECK-NEXT: vmflt.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmflt.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmflt.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x half> %3, <vscale x 16 x half> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32( declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32( declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vv v8, v9, v8 ; CHECK-NEXT: vmflt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x float> %3, <vscale x 1 x float> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32( declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32( declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vv v8, v9, v8 ; CHECK-NEXT: vmflt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x float> %3, <vscale x 2 x float> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32( declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32( declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmflt.vv v14, v10, v8 ; CHECK-NEXT: vmflt.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmflt.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmflt.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x float> %3, <vscale x 4 x float> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32( declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32( declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmflt.vv v20, v12, v8 ; CHECK-NEXT: vmflt.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmflt.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmflt.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x float> %3, <vscale x 8 x float> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64( declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64( declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmflt.vv v8, v9, v8 ; CHECK-NEXT: vmflt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x double> %3, <vscale x 1 x double> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64( declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64( declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vv v14, v10, v8 ; CHECK-NEXT: vmflt.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmflt.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmflt.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x double> %3, <vscale x 2 x double> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64( declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64( declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vv v20, v12, v8 ; CHECK-NEXT: vmflt.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmflt.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmflt.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x double> %3, <vscale x 4 x double> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16( declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16( declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f16.f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
half %2, half %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16( declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16( declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f16_f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f16.f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
half %2, half %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16( declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16( declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f16_f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f16.f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
half %2, half %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16( declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16( declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f16_f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f16.f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
half %2, half %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16( declare <vscale x 16 x i1> @llvm.riscv.vmfgt.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16( declare <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfgt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv16f16_f16: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfgt.mask.nxv16f16.f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
half %2, half %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32.f32( declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32( declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f32_f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f32.f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
float %2, float %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32.f32( declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32( declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f32_f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f32.f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
float %2, float %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32.f32( declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32( declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f32_f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f32.f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
float %2, float %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32.f32( declare <vscale x 8 x i1> @llvm.riscv.vmfgt.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32( declare <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfgt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f32_f32: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfgt.mask.nxv8f32.f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
float %2, float %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64.f64( declare <vscale x 1 x i1> @llvm.riscv.vmfgt.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64.f64( declare <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64.f64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfgt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f64_f64: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64.f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfgt.mask.nxv1f64.f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
double %2, double %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64.f64( declare <vscale x 2 x i1> @llvm.riscv.vmfgt.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64.f64( declare <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64.f64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfgt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f64_f64: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64.f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfgt.mask.nxv2f64.f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
double %2, double %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64.f64( declare <vscale x 4 x i1> @llvm.riscv.vmfgt.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64.f64( declare <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64.f64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfgt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f64_f64: ; CHECK-LABEL: intrinsic_vmfgt_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmfgt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64.f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfgt.mask.nxv4f64.f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
double %2, double %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmfle.ll

Show All 22 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16( declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmfle.vv v8, v8, v9 ; CHECK-NEXT: vmfle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x half> %3, <vscale x 1 x half> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16( declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16( declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmfle.vv v8, v8, v9 ; CHECK-NEXT: vmfle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x half> %3, <vscale x 2 x half> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16( declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16( declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmfle.vv v8, v8, v9 ; CHECK-NEXT: vmfle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x half> %3, <vscale x 4 x half> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16( declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16( declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmfle.vv v14, v8, v10 ; CHECK-NEXT: vmfle.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x half> %3, <vscale x 8 x half> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16( declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16( declare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x i1> @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmfle.vv v20, v8, v12 ; CHECK-NEXT: vmfle.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x half> %3, <vscale x 16 x half> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32( declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32( declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmfle.vv v8, v8, v9 ; CHECK-NEXT: vmfle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x float> %3, <vscale x 1 x float> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32( declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32( declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmfle.vv v8, v8, v9 ; CHECK-NEXT: vmfle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x float> %3, <vscale x 2 x float> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32( declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32( declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmfle.vv v14, v8, v10 ; CHECK-NEXT: vmfle.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x float> %3, <vscale x 4 x float> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32( declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32( declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmfle.vv v20, v8, v12 ; CHECK-NEXT: vmfle.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x float> %3, <vscale x 8 x float> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64( declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64( declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmfle.vv v8, v8, v9 ; CHECK-NEXT: vmfle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x double> %3, <vscale x 1 x double> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64( declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64( declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmfle.vv v14, v8, v10 ; CHECK-NEXT: vmfle.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x double> %3, <vscale x 2 x double> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64( declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64( declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmfle.vv v20, v8, v12 ; CHECK-NEXT: vmfle.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x double> %3, <vscale x 4 x double> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16( declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16( declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16.f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
half %2, half %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16( declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16( declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16.f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
half %2, half %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16( declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16( declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16.f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
half %2, half %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16( declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16( declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16.f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
half %2, half %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16( declare <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16( declare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x i1> @intrinsic_vmfle_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfle_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16.f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
half %2, half %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.f32( declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32( declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32.f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
float %2, float %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32.f32( declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32( declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32.f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
float %2, float %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32.f32( declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32( declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32.f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
float %2, float %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32.f32( declare <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32( declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32.f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
float %2, float %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64.f64( declare <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64( declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f64_f64: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64.f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
double %2, double %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64.f64( declare <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64( declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f64_f64: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64.f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
double %2, double %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64.f64( declare <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64( declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f64_f64: ; CHECK-LABEL: intrinsic_vmfle_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmfle.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64.f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
double %2, double %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmflt.ll

Show All 22 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16( declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmflt.vv v8, v8, v9 ; CHECK-NEXT: vmflt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x half> %3, <vscale x 1 x half> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16( declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16( declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmflt.vv v8, v8, v9 ; CHECK-NEXT: vmflt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x half> %3, <vscale x 2 x half> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16( declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16( declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmflt.vv v8, v8, v9 ; CHECK-NEXT: vmflt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x half> %3, <vscale x 4 x half> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16( declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16( declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmflt.vv v14, v8, v10 ; CHECK-NEXT: vmflt.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmflt.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmflt.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x half> %3, <vscale x 8 x half> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16( declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16( declare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x i1> @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmflt.vv v20, v8, v12 ; CHECK-NEXT: vmflt.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmflt.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmflt.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x half> %3, <vscale x 16 x half> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32( declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32( declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmflt.vv v8, v8, v9 ; CHECK-NEXT: vmflt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x float> %3, <vscale x 1 x float> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32( declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32( declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmflt.vv v8, v8, v9 ; CHECK-NEXT: vmflt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x float> %3, <vscale x 2 x float> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32( declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32( declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmflt.vv v14, v8, v10 ; CHECK-NEXT: vmflt.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmflt.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmflt.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x float> %3, <vscale x 4 x float> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32( declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32( declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmflt.vv v20, v8, v12 ; CHECK-NEXT: vmflt.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmflt.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmflt.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x float> %3, <vscale x 8 x float> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64( declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64( declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmflt.vv v8, v8, v9 ; CHECK-NEXT: vmflt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x double> %3, <vscale x 1 x double> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64( declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64( declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmflt.vv v14, v8, v10 ; CHECK-NEXT: vmflt.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmflt.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmflt.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x double> %3, <vscale x 2 x double> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64( declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64( declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmflt.vv v20, v8, v12 ; CHECK-NEXT: vmflt.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmflt.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmflt.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x double> %3, <vscale x 4 x double> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16( declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16( declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16.f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
half %2, half %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16( declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16( declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16.f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
half %2, half %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16( declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16( declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16.f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
half %2, half %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16( declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16( declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16.f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
half %2, half %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16( declare <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16( declare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x i1> @intrinsic_vmflt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmflt_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16.f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
half %2, half %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32.f32( declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32( declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32.f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
float %2, float %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32.f32( declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32( declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32.f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
float %2, float %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32.f32( declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32( declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32.f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
float %2, float %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32.f32( declare <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32( declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32.f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
float %2, float %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64.f64( declare <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64.f64( declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64.f64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f64_f64: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64.f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64.f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
double %2, double %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64.f64( declare <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64.f64( declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64.f64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f64_f64: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64.f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64.f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
double %2, double %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64.f64( declare <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64.f64( declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64.f64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f64_f64: ; CHECK-LABEL: intrinsic_vmflt_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmflt.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64.f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64.f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
double %2, double %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmfne.ll

Show All 22 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16( declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmfne.vv v8, v8, v9 ; CHECK-NEXT: vmfne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x half> %3, <vscale x 1 x half> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16( declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16( declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmfne.vv v8, v8, v9 ; CHECK-NEXT: vmfne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x half> %3, <vscale x 2 x half> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16( declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16( declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmfne.vv v8, v8, v9 ; CHECK-NEXT: vmfne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x half> %3, <vscale x 4 x half> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16( declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16( declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmfne.vv v14, v8, v10 ; CHECK-NEXT: vmfne.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmfne.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmfne.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x half> %3, <vscale x 8 x half> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16( declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16( declare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x i1> @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmfne.vv v20, v8, v12 ; CHECK-NEXT: vmfne.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmfne.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmfne.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x half> %3, <vscale x 16 x half> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32( declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32( declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmfne.vv v8, v8, v9 ; CHECK-NEXT: vmfne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x float> %3, <vscale x 1 x float> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32( declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32( declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmfne.vv v8, v8, v9 ; CHECK-NEXT: vmfne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x float> %3, <vscale x 2 x float> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32( declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32( declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmfne.vv v14, v8, v10 ; CHECK-NEXT: vmfne.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmfne.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmfne.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x float> %3, <vscale x 4 x float> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32( declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32( declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmfne.vv v20, v8, v12 ; CHECK-NEXT: vmfne.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmfne.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmfne.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x float> %3, <vscale x 8 x float> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64( declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64( declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmfne.vv v8, v8, v9 ; CHECK-NEXT: vmfne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64(
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x double> %3, <vscale x 1 x double> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64( declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64( declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmfne.vv v14, v8, v10 ; CHECK-NEXT: vmfne.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmfne.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmfne.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64(
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x double> %3, <vscale x 2 x double> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64( declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64( declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmfne.vv v20, v8, v12 ; CHECK-NEXT: vmfne.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmfne.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmfne.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64(
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %4) iXLen %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x double> %3, <vscale x 4 x double> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16( declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16( declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f16_f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, half %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16( %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16.f16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
half %2, half %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16( declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16( declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f16_f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, half %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16( %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16.f16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
half %2, half %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16( declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16( declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f16_f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, half %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16( %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16.f16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
half %2, half %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16( declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16( declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f16_f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, half %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmfne.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16( %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16.f16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
half %2, half %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16( declare <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16( declare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x i1> @intrinsic_vmfne_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmfne_mask_vf_nxv16f16_f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, half %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv16f16_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmfne.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16( %a = call <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16.f16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
half %2, half %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32.f32( declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32( declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f32_f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, float %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32( %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32.f32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
float %2, float %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32.f32( declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32( declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f32_f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, float %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32( %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32.f32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
float %2, float %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32.f32( declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32( declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f32_f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, float %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmfne.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32( %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32.f32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
float %2, float %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32.f32( declare <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32( declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f32_f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, float %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv8f32_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmfne.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32( %a = call <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32.f32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
float %2, float %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64.f64( declare <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64.f64( declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64.f64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f64_f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, double %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f64_f64: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv1f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t ; CHECK-NEXT: vmfne.vf v10, v8, fa0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64.f64( %a = call <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64.f64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
double %2, double %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64.f64( declare <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64.f64( declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64.f64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f64_f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, double %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f64_f64: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv2f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v11, v8, fa0, v0.t ; CHECK-NEXT: vmfne.vf v11, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64.f64( %a = call <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64.f64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
double %2, double %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64.f64( declare <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
iXLen); iXLen);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64.f64( declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64.f64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f64_f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, double %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f64_f64: ; CHECK-LABEL: intrinsic_vmfne_mask_vf_nxv4f64_f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v13, v8, fa0, v0.t ; CHECK-NEXT: vmfne.vf v13, v8, fa0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64.f64( %a = call <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64.f64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
double %2, double %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4) iXLen %4, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsbf.ll

Show All 12 Lines
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmsbf.m v8, v0 ; CHECK-NEXT: vmsbf.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1: ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsbf.m v10, v8, v0.t ; CHECK-NEXT: vmsbf.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen);
define <vscale x 2 x i1> @intrinsic_vmsbf_m_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsbf_m_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv2i1: ; CHECK-LABEL: intrinsic_vmsbf_m_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmsbf.m v8, v0 ; CHECK-NEXT: vmsbf.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1: ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsbf.m v10, v8, v0.t ; CHECK-NEXT: vmsbf.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen);
define <vscale x 4 x i1> @intrinsic_vmsbf_m_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsbf_m_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv4i1: ; CHECK-LABEL: intrinsic_vmsbf_m_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmsbf.m v8, v0 ; CHECK-NEXT: vmsbf.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1: ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsbf.m v10, v8, v0.t ; CHECK-NEXT: vmsbf.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen);
define <vscale x 8 x i1> @intrinsic_vmsbf_m_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsbf_m_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv8i1: ; CHECK-LABEL: intrinsic_vmsbf_m_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmsbf.m v8, v0 ; CHECK-NEXT: vmsbf.m v8, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1: ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsbf.m v10, v8, v0.t ; CHECK-NEXT: vmsbf.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen);
define <vscale x 16 x i1> @intrinsic_vmsbf_m_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsbf_m_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv16i1: ; CHECK-LABEL: intrinsic_vmsbf_m_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmsbf.m v8, v0 ; CHECK-NEXT: vmsbf.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x i1> @intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1: ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsbf.m v10, v8, v0.t ; CHECK-NEXT: vmsbf.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
iXLen); iXLen);
define <vscale x 32 x i1> @intrinsic_vmsbf_m_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsbf_m_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv32i1: ; CHECK-LABEL: intrinsic_vmsbf_m_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmsbf.m v8, v0 ; CHECK-NEXT: vmsbf.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 32 x i1> @intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1: ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsbf.m v10, v8, v0.t ; CHECK-NEXT: vmsbf.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
iXLen); iXLen);
define <vscale x 64 x i1> @intrinsic_vmsbf_m_nxv64i1(<vscale x 64 x i1> %0, iXLen %1) nounwind { define <vscale x 64 x i1> @intrinsic_vmsbf_m_nxv64i1(<vscale x 64 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv64i1: ; CHECK-LABEL: intrinsic_vmsbf_m_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmsbf.m v8, v0 ; CHECK-NEXT: vmsbf.m v8, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
iXLen %1) iXLen %1)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind { define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1: ; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsbf.m v10, v8, v0.t ; CHECK-NEXT: vmsbf.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmseq.vv v14, v8, v10 ; CHECK-NEXT: vmseq.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmseq.vv v20, v8, v12 ; CHECK-NEXT: vmseq.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmseq.vv v14, v8, v10 ; CHECK-NEXT: vmseq.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmseq.vv v20, v8, v12 ; CHECK-NEXT: vmseq.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmseq.vv v14, v8, v10 ; CHECK-NEXT: vmseq.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmseq.vv v20, v8, v12 ; CHECK-NEXT: vmseq.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmseq.vv v14, v8, v10 ; CHECK-NEXT: vmseq.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmseq.vv v20, v8, v12 ; CHECK-NEXT: vmseq.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmseq_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmseq_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vv v10, v8, v11, v0.t ; CHECK-NEXT: vmseq.vv v10, v8, v11, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vv v11, v8, v12, v0.t ; CHECK-NEXT: vmseq.vv v11, v8, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vv v13, v8, v16, v0.t ; CHECK-NEXT: vmseq.vv v13, v8, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i8 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i8 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i8 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmseq_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i8 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmseq_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i8 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmseq_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmseq_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i8 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i16 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i16 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i16 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmseq_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i16 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmseq_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i16 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmseq_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmseq.vv v14, v8, v10 ; CHECK-NEXT: vmseq.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmseq.vv v20, v8, v12 ; CHECK-NEXT: vmseq.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmseq.vv v14, v8, v10 ; CHECK-NEXT: vmseq.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmseq.vv v20, v8, v12 ; CHECK-NEXT: vmseq.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmseq.vv v14, v8, v10 ; CHECK-NEXT: vmseq.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmseq.vv v20, v8, v12 ; CHECK-NEXT: vmseq.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmseq.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmseq.vv v14, v8, v10 ; CHECK-NEXT: vmseq.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmseq.vv v20, v8, v12 ; CHECK-NEXT: vmseq.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmseq.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmseq_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmseq_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmseq.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmseq.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmseq.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmseq.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmseq.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmseq_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmseq.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i8 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i8 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i8 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmseq_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i8 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmseq_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i8 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmseq_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmseq_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmseq.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i8 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i16 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i16 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i16 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmseq_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i16 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmseq_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmseq_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmseq.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i16 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmseq_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmseq_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmseq.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmseq_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmseq.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmseq_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmseq.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmseq_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmseq_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmseq.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmsle.vv v14, v10, v8 ; CHECK-NEXT: vmsle.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmsle.vv v20, v12, v8 ; CHECK-NEXT: vmsle.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmsle.vv v14, v10, v8 ; CHECK-NEXT: vmsle.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmsle.vv v20, v12, v8 ; CHECK-NEXT: vmsle.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmsle.vv v14, v10, v8 ; CHECK-NEXT: vmsle.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmsle.vv v20, v12, v8 ; CHECK-NEXT: vmsle.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmsle.vv v14, v10, v8 ; CHECK-NEXT: vmsle.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmsle.vv v20, v12, v8 ; CHECK-NEXT: vmsle.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmsge_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsge_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vv v10, v11, v8, v0.t ; CHECK-NEXT: vmsle.vv v10, v11, v8, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vv v11, v12, v8, v0.t ; CHECK-NEXT: vmsle.vv v11, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vv v13, v16, v8, v0.t ; CHECK-NEXT: vmsle.vv v13, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 -14, i8 -14,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 -12, i8 -12,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 -10, i8 -10,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsge_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 -8, i8 -8,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsge_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 -6, i8 -6,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsge_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsge_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 -4, i8 -4,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 -2, i16 -2,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 0, i16 0,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 1, i16 1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsge_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 3, i16 3,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsge_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 5, i16 5,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 7, i32 7,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 11, i32 11,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsge_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 13, i32 13,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
; Test cases where the mask and maskedoff are the same value. ; Test cases where the mask and maskedoff are the same value.
define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmslt.vx v10, v8, a0 ; CHECK-NEXT: vmslt.vx v10, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v10 ; CHECK-NEXT: vmandn.mm v0, v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, i32 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmslt.vx v12, v8, a0 ; CHECK-NEXT: vmslt.vx v12, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v12 ; CHECK-NEXT: vmandn.mm v0, v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmslt.vx v10, v8, a0 ; CHECK-NEXT: vmslt.vx v10, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v10 ; CHECK-NEXT: vmandn.mm v0, v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmslt.vx v12, v8, a0 ; CHECK-NEXT: vmslt.vx v12, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v12 ; CHECK-NEXT: vmandn.mm v0, v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmslt.vx v10, v8, a0 ; CHECK-NEXT: vmslt.vx v10, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v10 ; CHECK-NEXT: vmandn.mm v0, v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmslt.vx v12, v8, a0 ; CHECK-NEXT: vmslt.vx v12, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v12 ; CHECK-NEXT: vmandn.mm v0, v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmsle.vv v0, v9, v8, v0.t ; CHECK-NEXT: vmsle.vv v0, v9, v8, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmsle.vv v10, v12, v8, v0.t ; CHECK-NEXT: vmsle.vv v10, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v12, v0 ; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vmsle.vv v12, v16, v8, v0.t ; CHECK-NEXT: vmsle.vv v12, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmsle.vv v14, v10, v8 ; CHECK-NEXT: vmsle.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmsle.vv v20, v12, v8 ; CHECK-NEXT: vmsle.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmsle.vv v14, v10, v8 ; CHECK-NEXT: vmsle.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmsle.vv v20, v12, v8 ; CHECK-NEXT: vmsle.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmsle.vv v14, v10, v8 ; CHECK-NEXT: vmsle.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmsle.vv v20, v12, v8 ; CHECK-NEXT: vmsle.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmsle.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmsle.vv v14, v10, v8 ; CHECK-NEXT: vmsle.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmsle.vv v20, v12, v8 ; CHECK-NEXT: vmsle.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsge.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmsge_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsge_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsge.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsge.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsge.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsge.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsge.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsge_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 -14, i8 -14,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 -12, i8 -12,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 -10, i8 -10,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsge_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 -8, i8 -8,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsge_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 -6, i8 -6,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsge_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsge_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 -4, i8 -4,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 -2, i16 -2,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 0, i16 0,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 1, i16 1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsge_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 3, i16 3,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsge_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 5, i16 5,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 7, i32 7,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 11, i32 11,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsge_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 13, i32 13,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 15, i64 15,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 -15, i64 -15,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsge_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 -13, i64 -13,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
; Test cases where the mask and maskedoff are the same value. ; Test cases where the mask and maskedoff are the same value.
define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmslt.vx v10, v8, a0 ; CHECK-NEXT: vmslt.vx v10, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v10 ; CHECK-NEXT: vmandn.mm v0, v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmslt.vx v12, v8, a0 ; CHECK-NEXT: vmslt.vx v12, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v12 ; CHECK-NEXT: vmandn.mm v0, v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsge.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmslt.vx v10, v8, a0 ; CHECK-NEXT: vmslt.vx v10, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v10 ; CHECK-NEXT: vmandn.mm v0, v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmslt.vx v12, v8, a0 ; CHECK-NEXT: vmslt.vx v12, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v12 ; CHECK-NEXT: vmandn.mm v0, v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsge.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmslt.vx v10, v8, a0 ; CHECK-NEXT: vmslt.vx v10, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v10 ; CHECK-NEXT: vmandn.mm v0, v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmslt.vx v12, v8, a0 ; CHECK-NEXT: vmslt.vx v12, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v12 ; CHECK-NEXT: vmandn.mm v0, v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsge.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmslt.vx v8, v8, a0 ; CHECK-NEXT: vmslt.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsge.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmslt.vx v10, v8, a0 ; CHECK-NEXT: vmslt.vx v10, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v10 ; CHECK-NEXT: vmandn.mm v0, v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsge.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsge_maskedoff_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmslt.vx v12, v8, a0 ; CHECK-NEXT: vmslt.vx v12, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v12 ; CHECK-NEXT: vmandn.mm v0, v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsge.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmsleu.vv v14, v10, v8 ; CHECK-NEXT: vmsleu.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmsleu.vv v20, v12, v8 ; CHECK-NEXT: vmsleu.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmsleu.vv v14, v10, v8 ; CHECK-NEXT: vmsleu.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmsleu.vv v20, v12, v8 ; CHECK-NEXT: vmsleu.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmsleu.vv v14, v10, v8 ; CHECK-NEXT: vmsleu.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmsleu.vv v20, v12, v8 ; CHECK-NEXT: vmsleu.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmsleu.vv v14, v10, v8 ; CHECK-NEXT: vmsleu.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmsleu.vv v20, v12, v8 ; CHECK-NEXT: vmsleu.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i32); i32);
Show All 14 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vv v10, v11, v8, v0.t ; CHECK-NEXT: vmsleu.vv v10, v11, v8, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vv v11, v12, v8, v0.t ; CHECK-NEXT: vmsleu.vv v11, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vv v13, v16, v8, v0.t ; CHECK-NEXT: vmsleu.vv v13, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 -14, i8 -14,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 -12, i8 -12,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 -10, i8 -10,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgeu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
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; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 -8, i8 -8,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgeu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 -6, i8 -6,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsgeu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgeu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 -4, i8 -4,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 -2, i16 -2,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
Show All 15 Lines
; CHECK-NEXT: vmor.mm v0, v9, v0 ; CHECK-NEXT: vmor.mm v0, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 0, i16 0,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i16_i16_same_mask_maskedoff(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i32 %2) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vi_nxv2i16_i16_same_mask_maskedoff(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16_same_mask_maskedoff: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv2i16_i16_same_mask_maskedoff:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 0, i16 0,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %2) i32 %2, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 1, i16 1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgeu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 3, i16 3,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgeu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 5, i16 5,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 7, i32 7,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 11, i32 11,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgeu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 13, i32 13,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
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; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 15, i64 15,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 -15, i64 -15,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 -13, i64 -13,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
; Test cases where the mask and maskedoff are the same value. ; Test cases where the mask and maskedoff are the same value.
define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmsltu.vx v10, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v10 ; CHECK-NEXT: vmandn.mm v0, v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, i32 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmsltu.vx v12, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v12 ; CHECK-NEXT: vmandn.mm v0, v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmsltu.vx v10, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v10 ; CHECK-NEXT: vmandn.mm v0, v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, i32 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmsltu.vx v12, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v12 ; CHECK-NEXT: vmandn.mm v0, v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmsltu.vx v10, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v10 ; CHECK-NEXT: vmandn.mm v0, v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, i32 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmsltu.vx v12, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v12 ; CHECK-NEXT: vmandn.mm v0, v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, i32 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v9, (a0), zero ; CHECK-NEXT: vlse64.v v9, (a0), zero
; CHECK-NEXT: vmsleu.vv v0, v9, v8, v0.t ; CHECK-NEXT: vmsleu.vv v0, v9, v8, v0.t
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, i32 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmsleu.vv v10, v12, v8, v0.t ; CHECK-NEXT: vmsleu.vv v10, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, i32 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v12, v0 ; CHECK-NEXT: vmv1r.v v12, v0
; CHECK-NEXT: vmsleu.vv v12, v16, v8, v0.t ; CHECK-NEXT: vmsleu.vv v12, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmsleu.vv v14, v10, v8 ; CHECK-NEXT: vmsleu.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmsleu.vv v20, v12, v8 ; CHECK-NEXT: vmsleu.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmsleu.vv v14, v10, v8 ; CHECK-NEXT: vmsleu.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmsleu.vv v20, v12, v8 ; CHECK-NEXT: vmsleu.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmsleu.vv v14, v10, v8 ; CHECK-NEXT: vmsleu.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmsleu.vv v20, v12, v8 ; CHECK-NEXT: vmsleu.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmsleu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmsleu.vv v14, v10, v8 ; CHECK-NEXT: vmsleu.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmsleu.vv v20, v12, v8 ; CHECK-NEXT: vmsleu.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgeu.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgeu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v10, v9 ; CHECK-NEXT: vmxor.mm v0, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v11, v10 ; CHECK-NEXT: vmxor.mm v0, v11, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i64); i64);
Show All 14 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmxor.mm v0, v13, v12 ; CHECK-NEXT: vmxor.mm v0, v13, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 -14, i8 -14,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 -12, i8 -12,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 -10, i8 -10,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgeu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 -8, i8 -8,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgeu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 -6, i8 -6,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsgeu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgeu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 -4, i8 -4,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 -2, i16 -2,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
Show All 15 Lines
; CHECK-NEXT: vmor.mm v0, v9, v0 ; CHECK-NEXT: vmor.mm v0, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 0, i16 0,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
Show All 13 Lines
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 0, i16 0,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %2) i64 %2, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_mask_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vi v10, v8, 0, v0.t ; CHECK-NEXT: vmsgtu.vi v10, v8, 0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 1, i16 1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgeu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 3, i16 3,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgeu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 5, i16 5,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 7, i32 7,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 11, i32 11,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgeu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 13, i32 13,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 15, i64 15,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 -15, i64 -15,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 -13, i64 -13,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
; Test cases where the mask and maskedoff are the same value. ; Test cases where the mask and maskedoff are the same value.
define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmsltu.vx v10, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v10 ; CHECK-NEXT: vmandn.mm v0, v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmsltu.vx v12, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v12 ; CHECK-NEXT: vmandn.mm v0, v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgeu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmsltu.vx v10, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v10 ; CHECK-NEXT: vmandn.mm v0, v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, i64 %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmsltu.vx v12, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v12 ; CHECK-NEXT: vmandn.mm v0, v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgeu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmsltu.vx v10, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v10 ; CHECK-NEXT: vmandn.mm v0, v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmsltu.vx v12, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v12 ; CHECK-NEXT: vmandn.mm v0, v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgeu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmsltu.vx v8, v8, a0 ; CHECK-NEXT: vmsltu.vx v8, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v8 ; CHECK-NEXT: vmandn.mm v0, v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgeu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmsltu.vx v10, v8, a0 ; CHECK-NEXT: vmsltu.vx v10, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v10 ; CHECK-NEXT: vmandn.mm v0, v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgeu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgeu_maskedoff_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmsltu.vx v12, v8, a0 ; CHECK-NEXT: vmsltu.vx v12, v8, a0
; CHECK-NEXT: vmandn.mm v0, v0, v12 ; CHECK-NEXT: vmandn.mm v0, v0, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgeu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmslt.vv v14, v10, v8 ; CHECK-NEXT: vmslt.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmslt.vv v20, v12, v8 ; CHECK-NEXT: vmslt.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmslt.vv v14, v10, v8 ; CHECK-NEXT: vmslt.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmslt.vv v20, v12, v8 ; CHECK-NEXT: vmslt.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmslt.vv v14, v10, v8 ; CHECK-NEXT: vmslt.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmslt.vv v20, v12, v8 ; CHECK-NEXT: vmslt.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmslt.vv v14, v10, v8 ; CHECK-NEXT: vmslt.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmslt.vv v20, v12, v8 ; CHECK-NEXT: vmslt.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vv v10, v11, v8, v0.t ; CHECK-NEXT: vmslt.vv v10, v11, v8, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vv v11, v12, v8, v0.t ; CHECK-NEXT: vmslt.vv v11, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vv v13, v16, v8, v0.t ; CHECK-NEXT: vmslt.vv v13, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i8 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i8 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i8 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgt_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i8 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgt_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i8 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsgt_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgt_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i8 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i16 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i16 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i16 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgt_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i16 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgt_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i16 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgt_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmslt.vv v14, v10, v8 ; CHECK-NEXT: vmslt.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmslt.vv v20, v12, v8 ; CHECK-NEXT: vmslt.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmslt.vv v14, v10, v8 ; CHECK-NEXT: vmslt.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmslt.vv v20, v12, v8 ; CHECK-NEXT: vmslt.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmslt.vv v14, v10, v8 ; CHECK-NEXT: vmslt.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmslt.vv v20, v12, v8 ; CHECK-NEXT: vmslt.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmslt.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmslt.vv v14, v10, v8 ; CHECK-NEXT: vmslt.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmslt.vv v20, v12, v8 ; CHECK-NEXT: vmslt.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgt.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgt.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsgt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i8 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i8 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i8 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgt_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i8 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgt_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i8 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsgt_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgt_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgt.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i8 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i16 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i16 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i16 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgt_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i16 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgt_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgt_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgt.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i16 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgt_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgt_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgt.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgt_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgt.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgt_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgt.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgt_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgt_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgt.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmsltu.vv v14, v10, v8 ; CHECK-NEXT: vmsltu.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmsltu.vv v20, v12, v8 ; CHECK-NEXT: vmsltu.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmsltu.vv v14, v10, v8 ; CHECK-NEXT: vmsltu.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmsltu.vv v20, v12, v8 ; CHECK-NEXT: vmsltu.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmsltu.vv v14, v10, v8 ; CHECK-NEXT: vmsltu.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmsltu.vv v20, v12, v8 ; CHECK-NEXT: vmsltu.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmsltu.vv v14, v10, v8 ; CHECK-NEXT: vmsltu.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmsltu.vv v20, v12, v8 ; CHECK-NEXT: vmsltu.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vv v10, v11, v8, v0.t ; CHECK-NEXT: vmsltu.vv v10, v11, v8, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vv v11, v12, v8, v0.t ; CHECK-NEXT: vmsltu.vv v11, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vv v13, v16, v8, v0.t ; CHECK-NEXT: vmsltu.vv v13, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i8 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i8 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i8 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
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; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i8 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgtu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i8 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsgtu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgtu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i8 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i16 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i16 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
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; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i16 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i16 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgtu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i16 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmsltu.vv v14, v10, v8 ; CHECK-NEXT: vmsltu.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmsltu.vv v20, v12, v8 ; CHECK-NEXT: vmsltu.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmsltu.vv v14, v10, v8 ; CHECK-NEXT: vmsltu.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmsltu.vv v20, v12, v8 ; CHECK-NEXT: vmsltu.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmsltu.vv v14, v10, v8 ; CHECK-NEXT: vmsltu.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmsltu.vv v20, v12, v8 ; CHECK-NEXT: vmsltu.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmsltu.vv v8, v9, v8
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmsltu.vv v14, v10, v8 ; CHECK-NEXT: vmsltu.vv v14, v10, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t ; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmsltu.vv v20, v12, v8 ; CHECK-NEXT: vmsltu.vv v20, v12, v8
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t ; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgtu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsgtu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i8 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i8 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i8 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i8 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgtu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i8 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsgtu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsgtu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsgtu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i8 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i16 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i16 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i16 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i16 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsgtu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsgtu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsgtu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i16 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsgtu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsgtu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsgtu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsgtu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsgtu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsgtu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsgtu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsgtu_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsgtu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsif.ll

Show All 19 Lines %a = call <vscale x 1 x i1> @llvm.riscv.vmsif.nxv1i1(
iXLen %1) iXLen %1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmsif_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsif_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv1i1_nxv1i1: ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
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Should vmsif, vmsof, and vmsbf have ForceTailAgnostic like vmand, vmxor, etc.?

craig.topper: Should vmsif, vmsof, and vmsbf have ForceTailAgnostic like vmand, vmxor, etc.?
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Nevermind. Ignore this comment.

craig.topper: Nevermind. Ignore this comment.
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsif.mask.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen);
define <vscale x 2 x i1> @intrinsic_vmsif_m_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsif_m_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {
Show All 9 Lines %a = call <vscale x 2 x i1> @llvm.riscv.vmsif.nxv2i1(
iXLen %1) iXLen %1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmsif_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsif_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv2i1_nxv2i1: ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsif.mask.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen);
define <vscale x 4 x i1> @intrinsic_vmsif_m_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsif_m_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {
Show All 9 Lines %a = call <vscale x 4 x i1> @llvm.riscv.vmsif.nxv4i1(
iXLen %1) iXLen %1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmsif_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsif_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv4i1_nxv4i1: ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsif.mask.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen);
define <vscale x 8 x i1> @intrinsic_vmsif_m_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsif_m_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {
Show All 9 Lines %a = call <vscale x 8 x i1> @llvm.riscv.vmsif.nxv8i1(
iXLen %1) iXLen %1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmsif_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsif_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv8i1_nxv8i1: ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen);
define <vscale x 16 x i1> @intrinsic_vmsif_m_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsif_m_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {
Show All 9 Lines %a = call <vscale x 16 x i1> @llvm.riscv.vmsif.nxv16i1(
iXLen %1) iXLen %1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x i1> @intrinsic_vmsif_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsif_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv16i1_nxv16i1: ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsif.mask.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
iXLen); iXLen);
define <vscale x 32 x i1> @intrinsic_vmsif_m_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsif_m_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind {
Show All 9 Lines %a = call <vscale x 32 x i1> @llvm.riscv.vmsif.nxv32i1(
iXLen %1) iXLen %1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 32 x i1> @intrinsic_vmsif_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsif_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv32i1_nxv32i1: ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsif.mask.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
iXLen); iXLen);
define <vscale x 64 x i1> @intrinsic_vmsif_m_nxv64i1(<vscale x 64 x i1> %0, iXLen %1) nounwind { define <vscale x 64 x i1> @intrinsic_vmsif_m_nxv64i1(<vscale x 64 x i1> %0, iXLen %1) nounwind {
Show All 9 Lines %a = call <vscale x 64 x i1> @llvm.riscv.vmsif.nxv64i1(
iXLen %1) iXLen %1)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 64 x i1> @intrinsic_vmsif_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind { define <vscale x 64 x i1> @intrinsic_vmsif_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv64i1_nxv64i1: ; CHECK-LABEL: intrinsic_vmsif_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsif.m v10, v8, v0.t ; CHECK-NEXT: vmsif.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsif.mask.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmsle.vv v14, v8, v10 ; CHECK-NEXT: vmsle.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmsle.vv v20, v8, v12 ; CHECK-NEXT: vmsle.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmsle.vv v14, v8, v10 ; CHECK-NEXT: vmsle.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmsle.vv v20, v8, v12 ; CHECK-NEXT: vmsle.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmsle.vv v14, v8, v10 ; CHECK-NEXT: vmsle.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmsle.vv v20, v8, v12 ; CHECK-NEXT: vmsle.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmsle.vv v14, v8, v10 ; CHECK-NEXT: vmsle.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmsle.vv v20, v8, v12 ; CHECK-NEXT: vmsle.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmsle_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsle_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vv v10, v8, v11, v0.t ; CHECK-NEXT: vmsle.vv v10, v8, v11, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vv v11, v8, v12, v0.t ; CHECK-NEXT: vmsle.vv v11, v8, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vv v13, v8, v16, v0.t ; CHECK-NEXT: vmsle.vv v13, v8, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i8 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i8 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i8 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsle_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i8 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsle_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i8 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsle_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsle_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i8 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i16 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i16 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i16 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsle_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i16 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsle_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i16 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsle_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmsle.vv v14, v8, v10 ; CHECK-NEXT: vmsle.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmsle.vv v20, v8, v12 ; CHECK-NEXT: vmsle.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmsle.vv v14, v8, v10 ; CHECK-NEXT: vmsle.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmsle.vv v20, v8, v12 ; CHECK-NEXT: vmsle.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmsle.vv v14, v8, v10 ; CHECK-NEXT: vmsle.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmsle.vv v20, v8, v12 ; CHECK-NEXT: vmsle.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmsle.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmsle.vv v14, v8, v10 ; CHECK-NEXT: vmsle.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmsle.vv v20, v8, v12 ; CHECK-NEXT: vmsle.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsle.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmsle_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsle_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsle.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsle.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsle.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsle.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsle.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsle_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsle.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i8 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i8 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i8 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsle_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i8 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsle_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i8 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsle_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsle_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsle.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i8 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i16 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i16 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i16 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsle_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i16 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsle_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsle_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsle.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i16 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsle_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsle_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsle.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsle_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsle.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsle_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsle.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsle_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsle_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsle.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmsleu.vv v14, v8, v10 ; CHECK-NEXT: vmsleu.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmsleu.vv v20, v8, v12 ; CHECK-NEXT: vmsleu.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmsleu.vv v14, v8, v10 ; CHECK-NEXT: vmsleu.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmsleu.vv v20, v8, v12 ; CHECK-NEXT: vmsleu.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmsleu.vv v14, v8, v10 ; CHECK-NEXT: vmsleu.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmsleu.vv v20, v8, v12 ; CHECK-NEXT: vmsleu.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmsleu.vv v14, v8, v10 ; CHECK-NEXT: vmsleu.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmsleu.vv v20, v8, v12 ; CHECK-NEXT: vmsleu.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vv v10, v8, v11, v0.t ; CHECK-NEXT: vmsleu.vv v10, v8, v11, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vv v11, v8, v12, v0.t ; CHECK-NEXT: vmsleu.vv v11, v8, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i32); i32);
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ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vv v13, v8, v16, v0.t ; CHECK-NEXT: vmsleu.vv v13, v8, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i8 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i8 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i8 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsleu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
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; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i8 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsleu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i8 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsleu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsleu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i8 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i16 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i16 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i16 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsleu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i16 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsleu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i16 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsleu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmsleu.vv v14, v8, v10 ; CHECK-NEXT: vmsleu.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmsleu.vv v20, v8, v12 ; CHECK-NEXT: vmsleu.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmsleu.vv v14, v8, v10 ; CHECK-NEXT: vmsleu.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmsleu.vv v20, v8, v12 ; CHECK-NEXT: vmsleu.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmsleu.vv v14, v8, v10 ; CHECK-NEXT: vmsleu.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmsleu.vv v20, v8, v12 ; CHECK-NEXT: vmsleu.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmsleu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmsleu.vv v14, v8, v10 ; CHECK-NEXT: vmsleu.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmsleu.vv v20, v8, v12 ; CHECK-NEXT: vmsleu.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsleu.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsleu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsleu.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsleu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i8 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i8 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i8 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsleu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i8 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsleu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i8 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsleu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsleu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsleu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i8 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i16 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i16 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i16 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsleu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i16 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsleu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsleu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsleu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i16 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsleu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsleu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsleu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsleu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsleu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsleu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsleu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsleu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsleu_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsleu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmslt.vv v14, v8, v10 ; CHECK-NEXT: vmslt.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmslt.vv v20, v8, v12 ; CHECK-NEXT: vmslt.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmslt.vv v14, v8, v10 ; CHECK-NEXT: vmslt.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmslt.vv v20, v8, v12 ; CHECK-NEXT: vmslt.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmslt.vv v14, v8, v10 ; CHECK-NEXT: vmslt.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmslt.vv v20, v8, v12 ; CHECK-NEXT: vmslt.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmslt.vv v14, v8, v10 ; CHECK-NEXT: vmslt.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmslt.vv v20, v8, v12 ; CHECK-NEXT: vmslt.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmslt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmslt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vv v10, v8, v11, v0.t ; CHECK-NEXT: vmslt.vv v10, v8, v11, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vv v11, v8, v12, v0.t ; CHECK-NEXT: vmslt.vv v11, v8, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vv v13, v8, v16, v0.t ; CHECK-NEXT: vmslt.vv v13, v8, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 -14, i8 -14,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 -12, i8 -12,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 -10, i8 -10,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmslt_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 -8, i8 -8,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmslt_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 -6, i8 -6,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmslt_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmslt_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 -4, i8 -4,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 -2, i16 -2,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 0, i16 0,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 1, i16 1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmslt_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 3, i16 3,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmslt_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 5, i16 5,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 7, i32 7,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 11, i32 11,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmslt_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 13, i32 13,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmslt.vv v14, v8, v10 ; CHECK-NEXT: vmslt.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmslt.vv v20, v8, v12 ; CHECK-NEXT: vmslt.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmslt.vv v14, v8, v10 ; CHECK-NEXT: vmslt.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmslt.vv v20, v8, v12 ; CHECK-NEXT: vmslt.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmslt.vv v14, v8, v10 ; CHECK-NEXT: vmslt.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmslt.vv v20, v8, v12 ; CHECK-NEXT: vmslt.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmslt.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmslt.vv v14, v8, v10 ; CHECK-NEXT: vmslt.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmslt.vv v20, v8, v12 ; CHECK-NEXT: vmslt.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmslt.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmslt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmslt_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmslt.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmslt.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmslt.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmslt.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmslt_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmslt.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 -14, i8 -14,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 -12, i8 -12,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 -10, i8 -10,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmslt_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 -8, i8 -8,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmslt_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 -6, i8 -6,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmslt_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmslt_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 -4, i8 -4,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 -2, i16 -2,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 0, i16 0,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 1, i16 1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmslt_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 3, i16 3,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmslt_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmslt_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 5, i16 5,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 7, i32 7,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 11, i32 11,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmslt_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmslt_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 13, i32 13,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmslt_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 15, i64 15,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmslt_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 -15, i64 -15,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 -13, i64 -13,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmsltu.vv v14, v8, v10 ; CHECK-NEXT: vmsltu.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmsltu.vv v20, v8, v12 ; CHECK-NEXT: vmsltu.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmsltu.vv v14, v8, v10 ; CHECK-NEXT: vmsltu.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmsltu.vv v20, v8, v12 ; CHECK-NEXT: vmsltu.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmsltu.vv v14, v8, v10 ; CHECK-NEXT: vmsltu.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmsltu.vv v20, v8, v12 ; CHECK-NEXT: vmsltu.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmsltu.vv v14, v8, v10 ; CHECK-NEXT: vmsltu.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmsltu.vv v20, v8, v12 ; CHECK-NEXT: vmsltu.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vv v10, v8, v11, v0.t ; CHECK-NEXT: vmsltu.vv v10, v8, v11, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vv v11, v8, v12, v0.t ; CHECK-NEXT: vmsltu.vv v11, v8, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vv v13, v8, v16, v0.t ; CHECK-NEXT: vmsltu.vv v13, v8, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsltu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 -14, i8 -14,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsltu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 -12, i8 -12,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsltu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 -10, i8 -10,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsltu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 -8, i8 -8,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsltu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 -6, i8 -6,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsltu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsltu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 -4, i8 -4,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsltu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 -2, i16 -2,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsltu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 0, i16 0,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsltu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 1, i16 1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsltu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 3, i16 3,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsltu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 5, i16 5,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsltu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 7, i32 7,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsltu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsltu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 11, i32 11,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsltu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 13, i32 13,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsltu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 15, i64 15,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsltu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 -15, i64 -15,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsltu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 -13, i64 -13,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmsltu.vv v14, v8, v10 ; CHECK-NEXT: vmsltu.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmsltu.vv v20, v8, v12 ; CHECK-NEXT: vmsltu.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmsltu.vv v14, v8, v10 ; CHECK-NEXT: vmsltu.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmsltu.vv v20, v8, v12 ; CHECK-NEXT: vmsltu.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmsltu.vv v14, v8, v10 ; CHECK-NEXT: vmsltu.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmsltu.vv v20, v8, v12 ; CHECK-NEXT: vmsltu.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmsltu.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmsltu.vv v14, v8, v10 ; CHECK-NEXT: vmsltu.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmsltu.vv v20, v8, v12 ; CHECK-NEXT: vmsltu.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsltu.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsltu_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsltu.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsltu.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsltu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 -14, i8 -14,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsltu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 -12, i8 -12,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsltu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 -10, i8 -10,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsltu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 -8, i8 -8,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsltu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 -6, i8 -6,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsltu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsltu_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsltu.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 -4, i8 -4,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsltu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 -2, i16 -2,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsltu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 0, i16 0,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsltu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 1, i16 1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsltu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 3, i16 3,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsltu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsltu_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsltu.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 5, i16 5,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsltu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 7, i32 7,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsltu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsltu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 11, i32 11,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsltu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsltu_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsltu.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 13, i32 13,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsltu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsltu_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsltu.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 15, i64 15,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsltu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsltu_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsltu.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 -15, i64 -15,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsltu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsltu_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsltu_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsltu.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 -13, i64 -13,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmsne.vv v14, v8, v10 ; CHECK-NEXT: vmsne.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmsne.vv v20, v8, v12 ; CHECK-NEXT: vmsne.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i32 %4) i32 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmsne.vv v14, v8, v10 ; CHECK-NEXT: vmsne.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmsne.vv v20, v8, v12 ; CHECK-NEXT: vmsne.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i32 %4) i32 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmsne.vv v14, v8, v10 ; CHECK-NEXT: vmsne.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmsne.vv v20, v8, v12 ; CHECK-NEXT: vmsne.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i32 %4) i32 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmsne.vv v14, v8, v10 ; CHECK-NEXT: vmsne.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmsne.vv v20, v8, v12 ; CHECK-NEXT: vmsne.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i32 %4) i32 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32, i32);
define <vscale x 32 x i1> @intrinsic_vmsne_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsne_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32, i32);
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i32); i32);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32, i32);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32, i32);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m1, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v11, (a0), zero ; CHECK-NEXT: vlse64.v v11, (a0), zero
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vv v10, v8, v11, v0.t ; CHECK-NEXT: vmsne.vv v10, v8, v11, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32, i32);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m2, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v12, (a0), zero ; CHECK-NEXT: vlse64.v v12, (a0), zero
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vv v11, v8, v12, v0.t ; CHECK-NEXT: vmsne.vv v11, v8, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i32); i32);
Show All 19 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32, i32);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sw a1, 12(sp) ; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a2, e64, m4, ta, mu
; CHECK-NEXT: addi a0, sp, 8 ; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vlse64.v v16, (a0), zero ; CHECK-NEXT: vlse64.v v16, (a0), zero
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vv v13, v8, v16, v0.t ; CHECK-NEXT: vmsne.vv v13, v8, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i8 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i8 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i8 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsne_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
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; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i8 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsne_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i8 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsne_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsne_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i8 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i16 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i16 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
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; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i16 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsne_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i16 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsne_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i16 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
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; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsne_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
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; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i32 %3) i32 %3, i32 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll

Show All 20 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8( declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8(
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %2, <vscale x 1 x i8> %2,
<vscale x 1 x i8> %3, <vscale x 1 x i8> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8( declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8(
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %2, <vscale x 2 x i8> %2,
<vscale x 2 x i8> %3, <vscale x 2 x i8> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8( declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8(
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %2, <vscale x 4 x i8> %2,
<vscale x 4 x i8> %3, <vscale x 4 x i8> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8( declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8(
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i8> %3, <vscale x 8 x i8> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8( declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2, <vscale x 16 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmsne.vv v14, v8, v10 ; CHECK-NEXT: vmsne.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8(
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %2, <vscale x 16 x i8> %2,
<vscale x 16 x i8> %3, <vscale x 16 x i8> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8( declare <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i8> %2, <vscale x 32 x i8> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmsne.vv v20, v8, v12 ; CHECK-NEXT: vmsne.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8( %mask = call <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8(
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
i64 %4) i64 %4)
%a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %2, <vscale x 32 x i8> %2,
<vscale x 32 x i8> %3, <vscale x 32 x i8> %3,
<vscale x 32 x i1> %mask, <vscale x 32 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16( declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i16> %2, <vscale x 1 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16(
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %2, <vscale x 1 x i16> %2,
<vscale x 1 x i16> %3, <vscale x 1 x i16> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16( declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i16> %2, <vscale x 2 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16(
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %2, <vscale x 2 x i16> %2,
<vscale x 2 x i16> %3, <vscale x 2 x i16> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16( declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16(
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i16> %3, <vscale x 4 x i16> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16( declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2, <vscale x 8 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
; CHECK-NEXT: vmsne.vv v14, v8, v10 ; CHECK-NEXT: vmsne.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16(
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %2, <vscale x 8 x i16> %2,
<vscale x 8 x i16> %3, <vscale x 8 x i16> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16( declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i16> %2, <vscale x 16 x i16> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmsne.vv v20, v8, v12 ; CHECK-NEXT: vmsne.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16( %mask = call <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16(
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
i64 %4) i64 %4)
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %2, <vscale x 16 x i16> %2,
<vscale x 16 x i16> %3, <vscale x 16 x i16> %3,
<vscale x 16 x i1> %mask, <vscale x 16 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32( declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i32> %2, <vscale x 1 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32(
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %2, <vscale x 1 x i32> %2,
<vscale x 1 x i32> %3, <vscale x 1 x i32> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32( declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32(
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i32> %3, <vscale x 2 x i32> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32( declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2, <vscale x 4 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
; CHECK-NEXT: vmsne.vv v14, v8, v10 ; CHECK-NEXT: vmsne.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32(
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %2, <vscale x 4 x i32> %2,
<vscale x 4 x i32> %3, <vscale x 4 x i32> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32( declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i32> %2, <vscale x 8 x i32> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
; CHECK-NEXT: vmsne.vv v20, v8, v12 ; CHECK-NEXT: vmsne.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32( %mask = call <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32(
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
i64 %4) i64 %4)
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %2, <vscale x 8 x i32> %2,
<vscale x 8 x i32> %3, <vscale x 8 x i32> %3,
<vscale x 8 x i1> %mask, <vscale x 8 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64( declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: vmv.v.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64( %mask = call <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64(
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i64> %3, <vscale x 1 x i64> %3,
<vscale x 1 x i1> %mask, <vscale x 1 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64( declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2, <vscale x 2 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
; CHECK-NEXT: vmsne.vv v14, v8, v10 ; CHECK-NEXT: vmsne.vv v14, v8, v10
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v14 ; CHECK-NEXT: vmv1r.v v0, v14
; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t ; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64( %mask = call <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64(
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %2, <vscale x 2 x i64> %2,
<vscale x 2 x i64> %3, <vscale x 2 x i64> %3,
<vscale x 2 x i1> %mask, <vscale x 2 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64( declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, <vscale x 4 x i64> %2, <vscale x 4 x i64> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
; CHECK-NEXT: vmsne.vv v20, v8, v12 ; CHECK-NEXT: vmsne.vv v20, v8, v12
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: vmv1r.v v0, v20 ; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t ; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64( %mask = call <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64(
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
i64 %4) i64 %4)
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %2, <vscale x 4 x i64> %2,
<vscale x 4 x i64> %3, <vscale x 4 x i64> %3,
<vscale x 4 x i1> %mask, <vscale x 4 x i1> %mask,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i8.i8(
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8( declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
i8, i8,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, i8 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 %2, i8 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i8.i8(
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8( declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
i8, i8,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, i8 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 %2, i8 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i8.i8(
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8( declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
i8, i8,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, i8 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 %2, i8 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i8.i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8( declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i8, i8,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, i8 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 %2, i8 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i8.i8(
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8( declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
i8, i8,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, i8 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 %2, i8 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsne.nxv32i8.i8(
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8( declare <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
i8, i8,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64, i64);
define <vscale x 32 x i1> @intrinsic_vmsne_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 32 x i1> @intrinsic_vmsne_mask_vx_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, i8 %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 %2, i8 %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i16.i16(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16( declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
i16, i16,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, i16 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 %2, i16 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i16.i16(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16( declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
i16, i16,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, i16 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 %2, i16 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i16.i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16( declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i16, i16,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, i16 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 %2, i16 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i16.i16(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16( declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
i16, i16,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, i16 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 %2, i16 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsne.nxv16i16.i16(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16( declare <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
i16, i16,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64, i64);
define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_mask_vx_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, i16 %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 %2, i16 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i32.i32(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32( declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
i32, i32,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, i32 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 %2, i32 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i32.i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32( declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32, i32,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, i32 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 %2, i32 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i32.i32(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32( declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
i32, i32,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, i32 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 %2, i32 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsne.nxv8i32.i32(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32( declare <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
i32, i32,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64, i64);
define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_mask_vx_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, i32 %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 %2, i32 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsne.nxv1i64.i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64( declare <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64, i64,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64, i64);
define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_mask_vx_nxv1i64_i64(<vscale x 1 x i1> %0, <vscale x 1 x i64> %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v10, v8, a0, v0.t
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 %2, i64 %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsne.nxv2i64.i64(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64( declare <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
i64, i64,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64, i64);
define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_mask_vx_nxv2i64_i64(<vscale x 2 x i1> %0, <vscale x 2 x i64> %1, i64 %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v11, v0 ; CHECK-NEXT: vmv1r.v v11, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v11, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 %2, i64 %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsne.nxv4i64.i64(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
i64); i64);
Show All 13 Linesentry:
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64( declare <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
i64, i64,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64, i64);
define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_mask_vx_nxv4i64_i64(<vscale x 4 x i1> %0, <vscale x 4 x i64> %1, i64 %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsne_mask_vx_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v13, v0 ; CHECK-NEXT: vmv1r.v v13, v0
; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t ; CHECK-NEXT: vmsne.vx v13, v8, a0, v0.t
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 %2, i64 %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i8_i8: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i8.i8(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
i8 9, i8 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i8_i8: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i8.i8(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
i8 9, i8 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i8_i8: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i8.i8(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
i8 9, i8 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsne_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_vi_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i8_i8: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i8.i8(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
i8 9, i8 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsne_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_vi_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i8_i8: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i8.i8(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
i8 9, i8 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 32 x i1> @intrinsic_vmsne_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsne_vi_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv32i8_i8: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv32i8_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8( %a = call <vscale x 32 x i1> @llvm.riscv.vmsne.mask.nxv32i8.i8(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
i8 9, i8 9,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i16_i16: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i16.i16(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
i16 9, i16 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i16_i16: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i16.i16(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
i16 9, i16 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i16_i16: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i16.i16(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
i16 9, i16 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsne_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_vi_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i16_i16: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i16.i16(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
i16 9, i16 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 16 x i1> @intrinsic_vmsne_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsne_vi_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i16_i16: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv16i16_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16( %a = call <vscale x 16 x i1> @llvm.riscv.vmsne.mask.nxv16i16.i16(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
i16 9, i16 9,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i32_i32: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i32.i32(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
i32 9, i32 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i32_i32: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i32.i32(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
i32 9, i32 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i32_i32: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i32.i32(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
i32 9, i32 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
define <vscale x 8 x i1> @intrinsic_vmsne_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsne_vi_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i32_i32: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv8i32_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32( %a = call <vscale x 8 x i1> @llvm.riscv.vmsne.mask.nxv8i32.i32(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
i32 9, i32 9,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind { define <vscale x 1 x i1> @intrinsic_vmsne_vi_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i64_i64: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv1i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv.v.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64( %a = call <vscale x 1 x i1> @llvm.riscv.vmsne.mask.nxv1i64.i64(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
i64 9, i64 9,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsne_vi_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i64_i64: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv2i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64( %a = call <vscale x 2 x i1> @llvm.riscv.vmsne.mask.nxv2i64.i64(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
i64 9, i64 9,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsne_vi_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i64_i64: ; CHECK-LABEL: intrinsic_vmsne_vi_nxv4i64_i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu
Show All 18 Lines
; CHECK-NEXT: vmv1r.v v0, v13 ; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64( %a = call <vscale x 4 x i1> @llvm.riscv.vmsne.mask.nxv4i64.i64(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
i64 9, i64 9,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
i64 %3) i64 %3, i64 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmsof.ll

Show All 19 Lines %a = call <vscale x 1 x i1> @llvm.riscv.vmsof.nxv1i1(
iXLen %1) iXLen %1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1( declare <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1(
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 1 x i1> @intrinsic_vmsof_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind { define <vscale x 1 x i1> @intrinsic_vmsof_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv1i1_nxv1i1: ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t ; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1( %a = call <vscale x 1 x i1> @llvm.riscv.vmsof.mask.nxv1i1(
<vscale x 1 x i1> %0, <vscale x 1 x i1> %0,
<vscale x 1 x i1> %1, <vscale x 1 x i1> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 1 x i1> %a ret <vscale x 1 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen);
define <vscale x 2 x i1> @intrinsic_vmsof_m_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind { define <vscale x 2 x i1> @intrinsic_vmsof_m_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {
Show All 9 Lines %a = call <vscale x 2 x i1> @llvm.riscv.vmsof.nxv2i1(
iXLen %1) iXLen %1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1( declare <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1(
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 2 x i1> @intrinsic_vmsof_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind { define <vscale x 2 x i1> @intrinsic_vmsof_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv2i1_nxv2i1: ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t ; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1( %a = call <vscale x 2 x i1> @llvm.riscv.vmsof.mask.nxv2i1(
<vscale x 2 x i1> %0, <vscale x 2 x i1> %0,
<vscale x 2 x i1> %1, <vscale x 2 x i1> %1,
<vscale x 2 x i1> %2, <vscale x 2 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 2 x i1> %a ret <vscale x 2 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen);
define <vscale x 4 x i1> @intrinsic_vmsof_m_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind { define <vscale x 4 x i1> @intrinsic_vmsof_m_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {
Show All 9 Lines %a = call <vscale x 4 x i1> @llvm.riscv.vmsof.nxv4i1(
iXLen %1) iXLen %1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1( declare <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1(
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 4 x i1> @intrinsic_vmsof_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind { define <vscale x 4 x i1> @intrinsic_vmsof_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv4i1_nxv4i1: ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t ; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1( %a = call <vscale x 4 x i1> @llvm.riscv.vmsof.mask.nxv4i1(
<vscale x 4 x i1> %0, <vscale x 4 x i1> %0,
<vscale x 4 x i1> %1, <vscale x 4 x i1> %1,
<vscale x 4 x i1> %2, <vscale x 4 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 4 x i1> %a ret <vscale x 4 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen);
define <vscale x 8 x i1> @intrinsic_vmsof_m_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind { define <vscale x 8 x i1> @intrinsic_vmsof_m_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {
Show All 9 Lines %a = call <vscale x 8 x i1> @llvm.riscv.vmsof.nxv8i1(
iXLen %1) iXLen %1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1( declare <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 8 x i1> @intrinsic_vmsof_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind { define <vscale x 8 x i1> @intrinsic_vmsof_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv8i1_nxv8i1: ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t ; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1( %a = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(
<vscale x 8 x i1> %0, <vscale x 8 x i1> %0,
<vscale x 8 x i1> %1, <vscale x 8 x i1> %1,
<vscale x 8 x i1> %2, <vscale x 8 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 8 x i1> %a ret <vscale x 8 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen);
define <vscale x 16 x i1> @intrinsic_vmsof_m_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind { define <vscale x 16 x i1> @intrinsic_vmsof_m_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {
Show All 9 Lines %a = call <vscale x 16 x i1> @llvm.riscv.vmsof.nxv16i1(
iXLen %1) iXLen %1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1( declare <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1(
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 16 x i1> @intrinsic_vmsof_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind { define <vscale x 16 x i1> @intrinsic_vmsof_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv16i1_nxv16i1: ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t ; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1( %a = call <vscale x 16 x i1> @llvm.riscv.vmsof.mask.nxv16i1(
<vscale x 16 x i1> %0, <vscale x 16 x i1> %0,
<vscale x 16 x i1> %1, <vscale x 16 x i1> %1,
<vscale x 16 x i1> %2, <vscale x 16 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 16 x i1> %a ret <vscale x 16 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
iXLen); iXLen);
define <vscale x 32 x i1> @intrinsic_vmsof_m_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind { define <vscale x 32 x i1> @intrinsic_vmsof_m_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind {
Show All 9 Lines %a = call <vscale x 32 x i1> @llvm.riscv.vmsof.nxv32i1(
iXLen %1) iXLen %1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1( declare <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1(
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 32 x i1> @intrinsic_vmsof_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind { define <vscale x 32 x i1> @intrinsic_vmsof_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv32i1_nxv32i1: ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t ; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1( %a = call <vscale x 32 x i1> @llvm.riscv.vmsof.mask.nxv32i1(
<vscale x 32 x i1> %0, <vscale x 32 x i1> %0,
<vscale x 32 x i1> %1, <vscale x 32 x i1> %1,
<vscale x 32 x i1> %2, <vscale x 32 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 32 x i1> %a ret <vscale x 32 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
iXLen); iXLen);
define <vscale x 64 x i1> @intrinsic_vmsof_m_nxv64i1(<vscale x 64 x i1> %0, iXLen %1) nounwind { define <vscale x 64 x i1> @intrinsic_vmsof_m_nxv64i1(<vscale x 64 x i1> %0, iXLen %1) nounwind {
Show All 9 Lines %a = call <vscale x 64 x i1> @llvm.riscv.vmsof.nxv64i1(
iXLen %1) iXLen %1)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }
declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1( declare <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1(
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
iXLen); iXLen, iXLen);
define <vscale x 64 x i1> @intrinsic_vmsof_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind { define <vscale x 64 x i1> @intrinsic_vmsof_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv64i1_nxv64i1: ; CHECK-LABEL: intrinsic_vmsof_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0 ; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsof.m v10, v8, v0.t ; CHECK-NEXT: vmsof.m v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1( %a = call <vscale x 64 x i1> @llvm.riscv.vmsof.mask.nxv64i1(
<vscale x 64 x i1> %0, <vscale x 64 x i1> %0,
<vscale x 64 x i1> %1, <vscale x 64 x i1> %1,
<vscale x 64 x i1> %2, <vscale x 64 x i1> %2,
iXLen %3) iXLen %3, iXLen 1)
ret <vscale x 64 x i1> %a ret <vscale x 64 x i1> %a
} }