[RISCV] Add policy operand for masked vid and viota IR intrinsics.

[khchen]

Summary

Those masked operations are missed the policy operand.

[rogfer01]

LGTM. Thanks @khchen !

clang/include/clang/Basic/riscv_vector.td

 // 16.4. vmsbf.m set-before-first mask bit
 def vmsbf : RVVMaskUnaryBuiltin;
 
 // 16.5. vmsif.m set-including-first mask bit
 def vmsif : RVVMaskUnaryBuiltin;
 
 // 16.6. vmsof.m set-only-first mask bit
 def vmsof : RVVMaskUnaryBuiltin;
+}
 
 let NoMaskPolicy = HasPassthruOperand, HasNoMaskedOverloaded = false in {
   // 16.8. Vector Iota Instruction
   defm viota : RVVOutBuiltinSet<"viota", "csil", [["m", "Uv", "Uvm"]]>;
 
   // 16.9. Vector Element Index Instruction
   defm vid : RVVOutBuiltinSet<"vid", "csil", [["v", "v", "v"],
                                               ["v", "Uv", "Uv"]]>;
 }
-}
 
 // 17. Vector Permutation Instructions
 // 17.1. Integer Scalar Move Instructions
 let HasMask = false, HasPolicy = false in {
   let HasVL = false, MangledName = "vmv_x" in
     defm vmv_x : RVVOp0BuiltinSet<"vmv_x_s", "csil",
                                    [["s", "ve", "ev"],
                                     ["s", "UvUe", "UeUv"]]>;

llvm/include/llvm/IR/IntrinsicsRISCV.td

let TargetPrefix = "riscv" in {
   // Input: (vl)
   class RISCVNullaryIntrinsic
         : Intrinsic<[llvm_anyvector_ty],
                     [llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic {
     let VLOperand = 1;
   }
   // Output: (vector)
   // Input: (passthru, vl)
-  class RISCVNullaryIntrinsicTU
+  class RISCVID
         : Intrinsic<[llvm_anyvector_ty],
                     [LLVMMatchType<0>, llvm_anyint_ty],
                     [IntrNoMem]>, RISCVVIntrinsic {
     let VLOperand = 1;
   }
   // For Conversion unary operations.
   // Input: (passthru, vector_in, vl)
   class RISCVConversionNoMask

   def int_riscv_viota : Intrinsic<[llvm_anyvector_ty],
                                   [LLVMMatchType<0>,
                                    LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                                    llvm_anyint_ty],
                                   [IntrNoMem]>, RISCVVIntrinsic {
     let VLOperand = 2;
   }
   // Output: (vector)
-  // Input: (maskedoff, mask type vector_in, mask, vl)
+  // Input: (maskedoff, mask type vector_in, mask, vl, policy)
   def int_riscv_viota_mask : Intrinsic<[llvm_anyvector_ty],
                                        [LLVMMatchType<0>,
                                         LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
                                         LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
-                                        llvm_anyint_ty],
-                                       [IntrNoMem]>, RISCVVIntrinsic {
+                                        llvm_anyint_ty, LLVMMatchType<1>],
+                                       [ImmArg<ArgIndex<4>>, IntrNoMem]>, RISCVVIntrinsic {
     let VLOperand = 3;
   }
   // Output: (vector)
   // Input: (passthru, vl)
-  def int_riscv_vid : RISCVNullaryIntrinsicTU;
+  def int_riscv_vid : RISCVID;
 
   // Output: (vector)
-  // Input: (maskedoff, mask, vl)
+  // Input: (maskedoff, mask, vl, policy)
   def int_riscv_vid_mask : Intrinsic<[llvm_anyvector_ty],
                                      [LLVMMatchType<0>,
                                       LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
-                                      llvm_anyint_ty],
-                                     [IntrNoMem]>, RISCVVIntrinsic {
+                                      llvm_anyint_ty, LLVMMatchType<1>],
+                                     [ImmArg<ArgIndex<3>>, IntrNoMem]>, RISCVVIntrinsic {
     let VLOperand = 2;
   }
 
   foreach nf = [2, 3, 4, 5, 6, 7, 8] in {
     defm vlseg # nf : RISCVUSSegLoad<nf>;
     defm vlseg # nf # ff : RISCVUSSegLoadFF<nf>;
     defm vlsseg # nf : RISCVSSegLoad<nf>;
     defm vloxseg # nf : RISCVISegLoad<nf>;

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

class VPseudoNullaryNoMaskTU<VReg RegClass>:
   let HasDummyMask = 1;
   let HasMergeOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 class VPseudoNullaryMask<VReg RegClass>:
       Pseudo<(outs GetVRegNoV0<RegClass>.R:$rd),
              (ins GetVRegNoV0<RegClass>.R:$merge, VMaskOp:$vm, AVL:$vl,
-              ixlenimm:$sew), []>, RISCVVPseudo {
+              ixlenimm:$sew, ixlenimm:$policy), []>, RISCVVPseudo {
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
   let Constraints ="$rd = $merge";
   let HasVLOp = 1;
   let HasSEWOp = 1;
   let HasMergeOp = 1;
   let UsesMaskPolicy = 1;
+  let HasVecPolicyOp = 1;
   let BaseInstr = !cast<Instruction>(PseudoToVInst<NAME>.VInst);
 }
 
 // Nullary for pseudo instructions. They are expanded in
 // RISCVExpandPseudoInsts pass.
 class VPseudoNullaryPseudoM<string BaseInst>
        : Pseudo<(outs VR:$rd), (ins AVL:$vl, ixlenimm:$sew), []>,
        RISCVVPseudo {

 multiclass VPseudoVIOT_M {
   defvar constraint = "@earlyclobber $rd";
   foreach m = MxList in {
     let VLMul = m.value in {
       def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, VR, constraint>,
                        Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>;
       def "_" # m.MX # "_TU" : VPseudoUnaryNoMaskTU<m.vrclass, VR, constraint>,
                                Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>;
-      def "_" # m.MX # "_MASK" : VPseudoUnaryMask<m.vrclass, VR, constraint>,
+      def "_" # m.MX # "_MASK" : VPseudoUnaryMaskTA<m.vrclass, VR, constraint>,
                                  Sched<[WriteVMIotV, ReadVMIotV, ReadVMask]>;
     }
   }
 }
 
 multiclass VPseudoVCPR_V {
   foreach m = MxList in {
     let VLMul = m.value in

 
 multiclass VPatUnaryV_M<string intrinsic, string instruction>
 {
   foreach vti = AllIntegerVectors in {
     def : VPatUnaryNoMask<intrinsic, instruction, "M", vti.Vector, vti.Mask,
                           vti.Log2SEW, vti.LMul, VR>;
     def : VPatUnaryNoMaskTU<intrinsic, instruction, "M", vti.Vector, vti.Mask,
                             vti.Log2SEW, vti.LMul, vti.RegClass,VR>;
-    def : VPatUnaryMask<intrinsic, instruction, "M", vti.Vector, vti.Mask,
+    def : VPatUnaryMaskTA<intrinsic, instruction, "M", vti.Vector, vti.Mask,
                           vti.Mask, vti.Log2SEW, vti.LMul, vti.RegClass, VR>;
   }
 }
 
 multiclass VPatUnaryV_VF<string intrinsic, string instruction, string suffix,
                          list<VTypeInfoToFraction> fractionList>
 {
   foreach vtiTofti = fractionList in
   {
def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic)
                           GPR:$vl, vti.Log2SEW)>;
     def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic)
                           (vti.Vector vti.RegClass:$merge),
                           VLOpFrag)),
                           (!cast<Instruction>(instruction#"_V_" # vti.LMul.MX # "_TU")
                           vti.RegClass:$merge, GPR:$vl, vti.Log2SEW)>;
     def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic # "_mask")
                           (vti.Vector vti.RegClass:$merge),
-                          (vti.Mask V0), VLOpFrag)),
+                          (vti.Mask V0), VLOpFrag, (XLenVT timm:$policy))),
                           (!cast<Instruction>(instruction#"_V_" # vti.LMul.MX # "_MASK")
                           vti.RegClass:$merge, (vti.Mask V0),
-                          GPR:$vl, vti.Log2SEW)>;
+                          GPR:$vl, vti.Log2SEW, (XLenVT timm:$policy))>;
   }
 }
 
 multiclass VPatNullaryM<string intrinsic, string inst> {
   foreach mti = AllMasks in
     def : Pat<(mti.Mask (!cast<Intrinsic>(intrinsic)
                         VLOpFrag)),
                         (!cast<Instruction>(inst#"_M_"#mti.BX)

llvm/test/CodeGen/RISCV/rvv/masked-tama.ll

%a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv1i8(
     <vscale x 1 x i8> undef,
     <vscale x 1 x i8> %0,
     <vscale x 1 x i16> %1,
     <vscale x 1 x i1> %2,
     iXLen %3, iXLen 3)
 
   ret <vscale x 1 x i8> %a
 }
+
+declare <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 1 x i8> @intrinsic_vid_mask_v_nxv1i8(<vscale x 1 x i1> %0, iXLen %1) nounwind {
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT:    vid.v v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
+    <vscale x 1 x i8> undef,
+    <vscale x 1 x i1> %0,
+    iXLen %1, iXLen 3)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 1 x i8> @intrinsic_viota_mask_m_nxv1i8_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i8_nxv1i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmv1r.v v9, v0
+; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT:    vmv1r.v v0, v8
+; CHECK-NEXT:    viota.m v8, v9, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
+    <vscale x 1 x i8> undef,
+    <vscale x 1 x i1> %0,
+    <vscale x 1 x i1> %1,
+    iXLen %2, iXLen 3)
+
+  ret <vscale x 1 x i8> %a
+}

llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll

%a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv1i8(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8> %1,
     <vscale x 1 x i16> %2,
     <vscale x 1 x i1> %3,
     iXLen %4, iXLen 1)
 
   ret <vscale x 1 x i8> %a
 }
+
+declare <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 1 x i8> @intrinsic_vid_mask_v_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT:    vid.v v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i1> %1,
+    iXLen %2, iXLen 1)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 1 x i8> @intrinsic_viota_mask_m_nxv1i8_nxv1i1(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i8_nxv1i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT:    viota.m v8, v0, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i1> %1,
+    <vscale x 1 x i1> %1,
+    iXLen %2, iXLen 1)
+
+  ret <vscale x 1 x i8> %a
+}

llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll

%a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv1i8(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8> %1,
     <vscale x 1 x i16> %2,
     <vscale x 1 x i1> %3,
     iXLen %4, iXLen 2)
 
   ret <vscale x 1 x i8> %a
 }
+
+declare <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 1 x i8> @intrinsic_vid_mask_v_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, tu, ma
+; CHECK-NEXT:    vid.v v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i1> %1,
+    iXLen %2, iXLen 2)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 1 x i8> @intrinsic_viota_mask_m_nxv1i8_nxv1i1(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i8_nxv1i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, tu, ma
+; CHECK-NEXT:    viota.m v8, v0, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i1> %1,
+    <vscale x 1 x i1> %1,
+    iXLen %2, iXLen 2)
+
+  ret <vscale x 1 x i8> %a
+}

llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll

%a = call <vscale x 1 x i8> @llvm.riscv.vrgatherei16.vv.mask.nxv1i8(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i8> %1,
     <vscale x 1 x i16> %2,
     <vscale x 1 x i1> %3,
     iXLen %4, iXLen 0)
 
   ret <vscale x 1 x i8> %a
 }
+
+declare <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 1 x i8> @intrinsic_vid_mask_v_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i8:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, tu, mu
+; CHECK-NEXT:    vid.v v8, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i1> %1,
+    iXLen %2, iXLen 0)
+
+  ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
+  <vscale x 1 x i8>,
+  <vscale x 1 x i1>,
+  <vscale x 1 x i1>,
+  iXLen, iXLen);
+
+define <vscale x 1 x i8> @intrinsic_viota_mask_m_nxv1i8_nxv1i1(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i8_nxv1i1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, tu, mu
+; CHECK-NEXT:    viota.m v8, v0, v0.t
+; CHECK-NEXT:    ret
+entry:
+  %a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
+    <vscale x 1 x i8> %0,
+    <vscale x 1 x i1> %1,
+    <vscale x 1 x i1> %1,
+    iXLen %2, iXLen 0)
+
+  ret <vscale x 1 x i8> %a
+}

llvm/test/CodeGen/RISCV/rvv/vid.ll

%a = call <vscale x 1 x i8> @llvm.riscv.vid.nxv1i8(
     iXLen %0)
 
   ret <vscale x 1 x i8> %a
 }
 
 declare <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
   <vscale x 1 x i8>,
   <vscale x 1 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 1 x i8> @intrinsic_vid_mask_v_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 1 x i8> @llvm.riscv.vid.mask.nxv1i8(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 1 x i8> %a
 }
 
 declare <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8(
   <vscale x 2 x i8>,
   iXLen);
 
%a = call <vscale x 2 x i8> @llvm.riscv.vid.nxv2i8(
     iXLen %0)
 
   ret <vscale x 2 x i8> %a
 }
 
 declare <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8(
   <vscale x 2 x i8>,
   <vscale x 2 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 2 x i8> @intrinsic_vid_mask_v_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 2 x i8> @llvm.riscv.vid.mask.nxv2i8(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 2 x i8> %a
 }
 
 declare <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8(
   <vscale x 4 x i8>,
   iXLen);
 
%a = call <vscale x 4 x i8> @llvm.riscv.vid.nxv4i8(
     iXLen %0)
 
   ret <vscale x 4 x i8> %a
 }
 
 declare <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8(
   <vscale x 4 x i8>,
   <vscale x 4 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 4 x i8> @intrinsic_vid_mask_v_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i8> @llvm.riscv.vid.mask.nxv4i8(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 4 x i8> %a
 }
 
 declare <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8(
   <vscale x 8 x i8>,
   iXLen);
 
%a = call <vscale x 8 x i8> @llvm.riscv.vid.nxv8i8(
     iXLen %0)
 
   ret <vscale x 8 x i8> %a
 }
 
 declare <vscale x 8 x i8> @llvm.riscv.vid.mask.nxv8i8(
   <vscale x 8 x i8>,
   <vscale x 8 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 8 x i8> @intrinsic_vid_mask_v_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i8> @llvm.riscv.vid.mask.nxv8i8(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 8 x i8> %a
 }
 
 declare <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8(
   <vscale x 16 x i8>,
   iXLen);
 
%a = call <vscale x 16 x i8> @llvm.riscv.vid.nxv16i8(
     iXLen %0)
 
   ret <vscale x 16 x i8> %a
 }
 
 declare <vscale x 16 x i8> @llvm.riscv.vid.mask.nxv16i8(
   <vscale x 16 x i8>,
   <vscale x 16 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 16 x i8> @intrinsic_vid_mask_v_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m2, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i8> @llvm.riscv.vid.mask.nxv16i8(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 16 x i8> %a
 }
 
 declare <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8(
   <vscale x 32 x i8>,
   iXLen);
 
%a = call <vscale x 32 x i8> @llvm.riscv.vid.nxv32i8(
     iXLen %0)
 
   ret <vscale x 32 x i8> %a
 }
 
 declare <vscale x 32 x i8> @llvm.riscv.vid.mask.nxv32i8(
   <vscale x 32 x i8>,
   <vscale x 32 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 32 x i8> @intrinsic_vid_mask_v_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i8:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m4, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 32 x i8> @llvm.riscv.vid.mask.nxv32i8(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 32 x i8> %a
 }
 
 declare <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16(
   <vscale x 1 x i16>,
   iXLen);
 
%a = call <vscale x 1 x i16> @llvm.riscv.vid.nxv1i16(
     iXLen %0)
 
   ret <vscale x 1 x i16> %a
 }
 
 declare <vscale x 1 x i16> @llvm.riscv.vid.mask.nxv1i16(
   <vscale x 1 x i16>,
   <vscale x 1 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 1 x i16> @intrinsic_vid_mask_v_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 1 x i16> @llvm.riscv.vid.mask.nxv1i16(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 1 x i16> %a
 }
 
 declare <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16(
   <vscale x 2 x i16>,
   iXLen);
 
%a = call <vscale x 2 x i16> @llvm.riscv.vid.nxv2i16(
     iXLen %0)
 
   ret <vscale x 2 x i16> %a
 }
 
 declare <vscale x 2 x i16> @llvm.riscv.vid.mask.nxv2i16(
   <vscale x 2 x i16>,
   <vscale x 2 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 2 x i16> @intrinsic_vid_mask_v_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 2 x i16> @llvm.riscv.vid.mask.nxv2i16(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 2 x i16> %a
 }
 
 declare <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16(
   <vscale x 4 x i16>,
   iXLen);
 
%a = call <vscale x 4 x i16> @llvm.riscv.vid.nxv4i16(
     iXLen %0)
 
   ret <vscale x 4 x i16> %a
 }
 
 declare <vscale x 4 x i16> @llvm.riscv.vid.mask.nxv4i16(
   <vscale x 4 x i16>,
   <vscale x 4 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 4 x i16> @intrinsic_vid_mask_v_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i16> @llvm.riscv.vid.mask.nxv4i16(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 4 x i16> %a
 }
 
 declare <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16(
   <vscale x 8 x i16>,
   iXLen);
 
%a = call <vscale x 8 x i16> @llvm.riscv.vid.nxv8i16(
     iXLen %0)
 
   ret <vscale x 8 x i16> %a
 }
 
 declare <vscale x 8 x i16> @llvm.riscv.vid.mask.nxv8i16(
   <vscale x 8 x i16>,
   <vscale x 8 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 8 x i16> @intrinsic_vid_mask_v_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i16> @llvm.riscv.vid.mask.nxv8i16(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 8 x i16> %a
 }
 
 declare <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16(
   <vscale x 16 x i16>,
   iXLen);
 
%a = call <vscale x 16 x i16> @llvm.riscv.vid.nxv16i16(
     iXLen %0)
 
   ret <vscale x 16 x i16> %a
 }
 
 declare <vscale x 16 x i16> @llvm.riscv.vid.mask.nxv16i16(
   <vscale x 16 x i16>,
   <vscale x 16 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 16 x i16> @intrinsic_vid_mask_v_nxv16i16(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i16> @llvm.riscv.vid.mask.nxv16i16(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 16 x i16> %a
 }
 
 declare <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16(
   <vscale x 32 x i16>,
   iXLen);
 
%a = call <vscale x 32 x i16> @llvm.riscv.vid.nxv32i16(
     iXLen %0)
 
   ret <vscale x 32 x i16> %a
 }
 
 declare <vscale x 32 x i16> @llvm.riscv.vid.mask.nxv32i16(
   <vscale x 32 x i16>,
   <vscale x 32 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 32 x i16> @intrinsic_vid_mask_v_nxv32i16(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv32i16:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m8, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 32 x i16> @llvm.riscv.vid.mask.nxv32i16(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 32 x i16> %a
 }
 
 declare <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32(
   <vscale x 1 x i32>,
   iXLen);
 
%a = call <vscale x 1 x i32> @llvm.riscv.vid.nxv1i32(
     iXLen %0)
 
   ret <vscale x 1 x i32> %a
 }
 
 declare <vscale x 1 x i32> @llvm.riscv.vid.mask.nxv1i32(
   <vscale x 1 x i32>,
   <vscale x 1 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 1 x i32> @intrinsic_vid_mask_v_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 1 x i32> @llvm.riscv.vid.mask.nxv1i32(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 1 x i32> %a
 }
 
 declare <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32(
   <vscale x 2 x i32>,
   iXLen);
 
%a = call <vscale x 2 x i32> @llvm.riscv.vid.nxv2i32(
     iXLen %0)
 
   ret <vscale x 2 x i32> %a
 }
 
 declare <vscale x 2 x i32> @llvm.riscv.vid.mask.nxv2i32(
   <vscale x 2 x i32>,
   <vscale x 2 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 2 x i32> @intrinsic_vid_mask_v_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.vid.mask.nxv2i32(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 2 x i32> %a
 }
 
 declare <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32(
   <vscale x 4 x i32>,
   iXLen);
 
%a = call <vscale x 4 x i32> @llvm.riscv.vid.nxv4i32(
     iXLen %0)
 
   ret <vscale x 4 x i32> %a
 }
 
 declare <vscale x 4 x i32> @llvm.riscv.vid.mask.nxv4i32(
   <vscale x 4 x i32>,
   <vscale x 4 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 4 x i32> @intrinsic_vid_mask_v_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.vid.mask.nxv4i32(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 4 x i32> %a
 }
 
 declare <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32(
   <vscale x 8 x i32>,
   iXLen);
 
%a = call <vscale x 8 x i32> @llvm.riscv.vid.nxv8i32(
     iXLen %0)
 
   ret <vscale x 8 x i32> %a
 }
 
 declare <vscale x 8 x i32> @llvm.riscv.vid.mask.nxv8i32(
   <vscale x 8 x i32>,
   <vscale x 8 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 8 x i32> @intrinsic_vid_mask_v_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.vid.mask.nxv8i32(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 8 x i32> %a
 }
 
 declare <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32(
   <vscale x 16 x i32>,
   iXLen);
 
%a = call <vscale x 16 x i32> @llvm.riscv.vid.nxv16i32(
     iXLen %0)
 
   ret <vscale x 16 x i32> %a
 }
 
 declare <vscale x 16 x i32> @llvm.riscv.vid.mask.nxv16i32(
   <vscale x 16 x i32>,
   <vscale x 16 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 16 x i32> @intrinsic_vid_mask_v_nxv16i32(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv16i32:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e32, m8, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.vid.mask.nxv16i32(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 16 x i32> %a
 }
 
 declare <vscale x 1 x i64> @llvm.riscv.vid.nxv1i64(
   <vscale x 1 x i64>,
   iXLen);
 
%a = call <vscale x 1 x i64> @llvm.riscv.vid.nxv1i64(
     iXLen %0)
 
   ret <vscale x 1 x i64> %a
 }
 
 declare <vscale x 1 x i64> @llvm.riscv.vid.mask.nxv1i64(
   <vscale x 1 x i64>,
   <vscale x 1 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 1 x i64> @intrinsic_vid_mask_v_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m1, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 1 x i64> @llvm.riscv.vid.mask.nxv1i64(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 1 x i64> %a
 }
 
 declare <vscale x 2 x i64> @llvm.riscv.vid.nxv2i64(
   <vscale x 2 x i64>,
   iXLen);
 
%a = call <vscale x 2 x i64> @llvm.riscv.vid.nxv2i64(
     iXLen %0)
 
   ret <vscale x 2 x i64> %a
 }
 
 declare <vscale x 2 x i64> @llvm.riscv.vid.mask.nxv2i64(
   <vscale x 2 x i64>,
   <vscale x 2 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 2 x i64> @intrinsic_vid_mask_v_nxv2i64(<vscale x 2 x i64> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv2i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m2, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 2 x i64> @llvm.riscv.vid.mask.nxv2i64(
     <vscale x 2 x i64> %0,
     <vscale x 2 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 2 x i64> %a
 }
 
 declare <vscale x 4 x i64> @llvm.riscv.vid.nxv4i64(
   <vscale x 4 x i64>,
   iXLen);
 
%a = call <vscale x 4 x i64> @llvm.riscv.vid.nxv4i64(
     iXLen %0)
 
   ret <vscale x 4 x i64> %a
 }
 
 declare <vscale x 4 x i64> @llvm.riscv.vid.mask.nxv4i64(
   <vscale x 4 x i64>,
   <vscale x 4 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 4 x i64> @intrinsic_vid_mask_v_nxv4i64(<vscale x 4 x i64> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv4i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m4, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i64> @llvm.riscv.vid.mask.nxv4i64(
     <vscale x 4 x i64> %0,
     <vscale x 4 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 4 x i64> %a
 }
 
 declare <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64(
   <vscale x 8 x i64>,
   iXLen);
 
%a = call <vscale x 8 x i64> @llvm.riscv.vid.nxv8i64(
     iXLen %0)
 
   ret <vscale x 8 x i64> %a
 }
 
 declare <vscale x 8 x i64> @llvm.riscv.vid.mask.nxv8i64(
   <vscale x 8 x i64>,
   <vscale x 8 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 8 x i64> @intrinsic_vid_mask_v_nxv8i64(<vscale x 8 x i64> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vid_mask_v_nxv8i64:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m8, tu, mu
 ; CHECK-NEXT:    vid.v v8, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i64> @llvm.riscv.vid.mask.nxv8i64(
     <vscale x 8 x i64> %0,
     <vscale x 8 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 8 x i64> %a
 }

llvm/test/CodeGen/RISCV/rvv/viota.ll

entry:
 
   ret <vscale x 1 x i8> %a
 }
 
 declare <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
   <vscale x 1 x i8>,
   <vscale x 1 x i1>,
   <vscale x 1 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 1 x i8> @intrinsic_viota_mask_m_nxv1i8_nxv1i1(<vscale x 1 x i8> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i8_nxv1i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, mf8, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 1 x i8> @llvm.riscv.viota.mask.nxv1i8(
     <vscale x 1 x i8> %0,
     <vscale x 1 x i1> %1,
     <vscale x 1 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 1 x i8> %a
 }
 
 declare <vscale x 2 x i8> @llvm.riscv.viota.nxv2i8(
   <vscale x 2 x i8>,
   <vscale x 2 x i1>,
   iXLen);
entry:
 
   ret <vscale x 2 x i8> %a
 }
 
 declare <vscale x 2 x i8> @llvm.riscv.viota.mask.nxv2i8(
   <vscale x 2 x i8>,
   <vscale x 2 x i1>,
   <vscale x 2 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 2 x i8> @intrinsic_viota_mask_m_nxv2i8_nxv2i1(<vscale x 2 x i8> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i8_nxv2i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, mf4, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 2 x i8> @llvm.riscv.viota.mask.nxv2i8(
     <vscale x 2 x i8> %0,
     <vscale x 2 x i1> %1,
     <vscale x 2 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 2 x i8> %a
 }
 
 declare <vscale x 4 x i8> @llvm.riscv.viota.nxv4i8(
   <vscale x 4 x i8>,
   <vscale x 4 x i1>,
   iXLen);
entry:
 
   ret <vscale x 4 x i8> %a
 }
 
 declare <vscale x 4 x i8> @llvm.riscv.viota.mask.nxv4i8(
   <vscale x 4 x i8>,
   <vscale x 4 x i1>,
   <vscale x 4 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 4 x i8> @intrinsic_viota_mask_m_nxv4i8_nxv4i1(<vscale x 4 x i8> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i8_nxv4i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, mf2, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i8> @llvm.riscv.viota.mask.nxv4i8(
     <vscale x 4 x i8> %0,
     <vscale x 4 x i1> %1,
     <vscale x 4 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 4 x i8> %a
 }
 
 declare <vscale x 8 x i8> @llvm.riscv.viota.nxv8i8(
   <vscale x 8 x i8>,
   <vscale x 8 x i1>,
   iXLen);
entry:
 
   ret <vscale x 8 x i8> %a
 }
 
 declare <vscale x 8 x i8> @llvm.riscv.viota.mask.nxv8i8(
   <vscale x 8 x i8>,
   <vscale x 8 x i1>,
   <vscale x 8 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 8 x i8> @intrinsic_viota_mask_m_nxv8i8_nxv8i1(<vscale x 8 x i8> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i8_nxv8i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m1, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i8> @llvm.riscv.viota.mask.nxv8i8(
     <vscale x 8 x i8> %0,
     <vscale x 8 x i1> %1,
     <vscale x 8 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 8 x i8> %a
 }
 
 declare <vscale x 16 x i8> @llvm.riscv.viota.nxv16i8(
   <vscale x 16 x i8>,
   <vscale x 16 x i1>,
   iXLen);
entry:
 
   ret <vscale x 16 x i8> %a
 }
 
 declare <vscale x 16 x i8> @llvm.riscv.viota.mask.nxv16i8(
   <vscale x 16 x i8>,
   <vscale x 16 x i1>,
   <vscale x 16 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 16 x i8> @intrinsic_viota_mask_m_nxv16i8_nxv16i1(<vscale x 16 x i8> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i8_nxv16i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m2, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i8> @llvm.riscv.viota.mask.nxv16i8(
     <vscale x 16 x i8> %0,
     <vscale x 16 x i1> %1,
     <vscale x 16 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 16 x i8> %a
 }
 
 declare <vscale x 32 x i8> @llvm.riscv.viota.nxv32i8(
   <vscale x 32 x i8>,
   <vscale x 32 x i1>,
   iXLen);
entry:
 
   ret <vscale x 32 x i8> %a
 }
 
 declare <vscale x 32 x i8> @llvm.riscv.viota.mask.nxv32i8(
   <vscale x 32 x i8>,
   <vscale x 32 x i1>,
   <vscale x 32 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 32 x i8> @intrinsic_viota_mask_m_nxv32i8_nxv32i1(<vscale x 32 x i8> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i8_nxv32i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m4, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 32 x i8> @llvm.riscv.viota.mask.nxv32i8(
     <vscale x 32 x i8> %0,
     <vscale x 32 x i1> %1,
     <vscale x 32 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 32 x i8> %a
 }
 
 declare <vscale x 64 x i8> @llvm.riscv.viota.nxv64i8(
   <vscale x 64 x i8>,
   <vscale x 64 x i1>,
   iXLen);
entry:
 
   ret <vscale x 64 x i8> %a
 }
 
 declare <vscale x 64 x i8> @llvm.riscv.viota.mask.nxv64i8(
   <vscale x 64 x i8>,
   <vscale x 64 x i1>,
   <vscale x 64 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 64 x i8> @intrinsic_viota_mask_m_nxv64i8_nxv64i1(<vscale x 64 x i8> %0, <vscale x 64 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv64i8_nxv64i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m8, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 64 x i8> @llvm.riscv.viota.mask.nxv64i8(
     <vscale x 64 x i8> %0,
     <vscale x 64 x i1> %1,
     <vscale x 64 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 64 x i8> %a
 }
 
 declare <vscale x 1 x i16> @llvm.riscv.viota.nxv1i16(
   <vscale x 1 x i16>,
   <vscale x 1 x i1>,
   iXLen);
entry:
 
   ret <vscale x 1 x i16> %a
 }
 
 declare <vscale x 1 x i16> @llvm.riscv.viota.mask.nxv1i16(
   <vscale x 1 x i16>,
   <vscale x 1 x i1>,
   <vscale x 1 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 1 x i16> @intrinsic_viota_mask_m_nxv1i16_nxv1i1(<vscale x 1 x i16> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i16_nxv1i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 1 x i16> @llvm.riscv.viota.mask.nxv1i16(
     <vscale x 1 x i16> %0,
     <vscale x 1 x i1> %1,
     <vscale x 1 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 1 x i16> %a
 }
 
 declare <vscale x 2 x i16> @llvm.riscv.viota.nxv2i16(
   <vscale x 2 x i16>,
   <vscale x 2 x i1>,
   iXLen);
entry:
 
   ret <vscale x 2 x i16> %a
 }
 
 declare <vscale x 2 x i16> @llvm.riscv.viota.mask.nxv2i16(
   <vscale x 2 x i16>,
   <vscale x 2 x i1>,
   <vscale x 2 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 2 x i16> @intrinsic_viota_mask_m_nxv2i16_nxv2i1(<vscale x 2 x i16> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i16_nxv2i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 2 x i16> @llvm.riscv.viota.mask.nxv2i16(
     <vscale x 2 x i16> %0,
     <vscale x 2 x i1> %1,
     <vscale x 2 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 2 x i16> %a
 }
 
 declare <vscale x 4 x i16> @llvm.riscv.viota.nxv4i16(
   <vscale x 4 x i16>,
   <vscale x 4 x i1>,
   iXLen);
entry:
 
   ret <vscale x 4 x i16> %a
 }
 
 declare <vscale x 4 x i16> @llvm.riscv.viota.mask.nxv4i16(
   <vscale x 4 x i16>,
   <vscale x 4 x i1>,
   <vscale x 4 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 4 x i16> @intrinsic_viota_mask_m_nxv4i16_nxv4i1(<vscale x 4 x i16> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i16_nxv4i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m1, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i16> @llvm.riscv.viota.mask.nxv4i16(
     <vscale x 4 x i16> %0,
     <vscale x 4 x i1> %1,
     <vscale x 4 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 4 x i16> %a
 }
 
 declare <vscale x 8 x i16> @llvm.riscv.viota.nxv8i16(
   <vscale x 8 x i16>,
   <vscale x 8 x i1>,
   iXLen);
entry:
 
   ret <vscale x 8 x i16> %a
 }
 
 declare <vscale x 8 x i16> @llvm.riscv.viota.mask.nxv8i16(
   <vscale x 8 x i16>,
   <vscale x 8 x i1>,
   <vscale x 8 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 8 x i16> @intrinsic_viota_mask_m_nxv8i16_nxv8i1(<vscale x 8 x i16> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i16_nxv8i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m2, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i16> @llvm.riscv.viota.mask.nxv8i16(
     <vscale x 8 x i16> %0,
     <vscale x 8 x i1> %1,
     <vscale x 8 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 8 x i16> %a
 }
 
 declare <vscale x 16 x i16> @llvm.riscv.viota.nxv16i16(
   <vscale x 16 x i16>,
   <vscale x 16 x i1>,
   iXLen);
entry:
 
   ret <vscale x 16 x i16> %a
 }
 
 declare <vscale x 16 x i16> @llvm.riscv.viota.mask.nxv16i16(
   <vscale x 16 x i16>,
   <vscale x 16 x i1>,
   <vscale x 16 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 16 x i16> @intrinsic_viota_mask_m_nxv16i16_nxv16i1(<vscale x 16 x i16> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i16_nxv16i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m4, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i16> @llvm.riscv.viota.mask.nxv16i16(
     <vscale x 16 x i16> %0,
     <vscale x 16 x i1> %1,
     <vscale x 16 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 16 x i16> %a
 }
 
 declare <vscale x 32 x i16> @llvm.riscv.viota.nxv32i16(
   <vscale x 32 x i16>,
   <vscale x 32 x i1>,
   iXLen);
entry:
 
   ret <vscale x 32 x i16> %a
 }
 
 declare <vscale x 32 x i16> @llvm.riscv.viota.mask.nxv32i16(
   <vscale x 32 x i16>,
   <vscale x 32 x i1>,
   <vscale x 32 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 32 x i16> @intrinsic_viota_mask_m_nxv32i16_nxv32i1(<vscale x 32 x i16> %0, <vscale x 32 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv32i16_nxv32i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e16, m8, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 32 x i16> @llvm.riscv.viota.mask.nxv32i16(
     <vscale x 32 x i16> %0,
     <vscale x 32 x i1> %1,
     <vscale x 32 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 32 x i16> %a
 }
 
 declare <vscale x 1 x i32> @llvm.riscv.viota.nxv1i32(
   <vscale x 1 x i32>,
   <vscale x 1 x i1>,
   iXLen);
entry:
 
   ret <vscale x 1 x i32> %a
 }
 
 declare <vscale x 1 x i32> @llvm.riscv.viota.mask.nxv1i32(
   <vscale x 1 x i32>,
   <vscale x 1 x i1>,
   <vscale x 1 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 1 x i32> @intrinsic_viota_mask_m_nxv1i32_nxv1i1(<vscale x 1 x i32> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i32_nxv1i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e32, mf2, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 1 x i32> @llvm.riscv.viota.mask.nxv1i32(
     <vscale x 1 x i32> %0,
     <vscale x 1 x i1> %1,
     <vscale x 1 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 1 x i32> %a
 }
 
 declare <vscale x 2 x i32> @llvm.riscv.viota.nxv2i32(
   <vscale x 2 x i32>,
   <vscale x 2 x i1>,
   iXLen);
entry:
 
   ret <vscale x 2 x i32> %a
 }
 
 declare <vscale x 2 x i32> @llvm.riscv.viota.mask.nxv2i32(
   <vscale x 2 x i32>,
   <vscale x 2 x i1>,
   <vscale x 2 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 2 x i32> @intrinsic_viota_mask_m_nxv2i32_nxv2i1(<vscale x 2 x i32> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i32_nxv2i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 2 x i32> @llvm.riscv.viota.mask.nxv2i32(
     <vscale x 2 x i32> %0,
     <vscale x 2 x i1> %1,
     <vscale x 2 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 2 x i32> %a
 }
 
 declare <vscale x 4 x i32> @llvm.riscv.viota.nxv4i32(
   <vscale x 4 x i32>,
   <vscale x 4 x i1>,
   iXLen);
entry:
 
   ret <vscale x 4 x i32> %a
 }
 
 declare <vscale x 4 x i32> @llvm.riscv.viota.mask.nxv4i32(
   <vscale x 4 x i32>,
   <vscale x 4 x i1>,
   <vscale x 4 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 4 x i32> @intrinsic_viota_mask_m_nxv4i32_nxv4i1(<vscale x 4 x i32> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i32_nxv4i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e32, m2, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i32> @llvm.riscv.viota.mask.nxv4i32(
     <vscale x 4 x i32> %0,
     <vscale x 4 x i1> %1,
     <vscale x 4 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 4 x i32> %a
 }
 
 declare <vscale x 8 x i32> @llvm.riscv.viota.nxv8i32(
   <vscale x 8 x i32>,
   <vscale x 8 x i1>,
   iXLen);
entry:
 
   ret <vscale x 8 x i32> %a
 }
 
 declare <vscale x 8 x i32> @llvm.riscv.viota.mask.nxv8i32(
   <vscale x 8 x i32>,
   <vscale x 8 x i1>,
   <vscale x 8 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 8 x i32> @intrinsic_viota_mask_m_nxv8i32_nxv8i1(<vscale x 8 x i32> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i32_nxv8i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e32, m4, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i32> @llvm.riscv.viota.mask.nxv8i32(
     <vscale x 8 x i32> %0,
     <vscale x 8 x i1> %1,
     <vscale x 8 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 8 x i32> %a
 }
 
 declare <vscale x 16 x i32> @llvm.riscv.viota.nxv16i32(
   <vscale x 16 x i32>,
   <vscale x 16 x i1>,
   iXLen);
entry:
 
   ret <vscale x 16 x i32> %a
 }
 
 declare <vscale x 16 x i32> @llvm.riscv.viota.mask.nxv16i32(
   <vscale x 16 x i32>,
   <vscale x 16 x i1>,
   <vscale x 16 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 16 x i32> @intrinsic_viota_mask_m_nxv16i32_nxv16i1(<vscale x 16 x i32> %0, <vscale x 16 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv16i32_nxv16i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e32, m8, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 16 x i32> @llvm.riscv.viota.mask.nxv16i32(
     <vscale x 16 x i32> %0,
     <vscale x 16 x i1> %1,
     <vscale x 16 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 16 x i32> %a
 }
 
 declare <vscale x 1 x i64> @llvm.riscv.viota.nxv1i64(
   <vscale x 1 x i64>,
   <vscale x 1 x i1>,
   iXLen);
entry:
 
   ret <vscale x 1 x i64> %a
 }
 
 declare <vscale x 1 x i64> @llvm.riscv.viota.mask.nxv1i64(
   <vscale x 1 x i64>,
   <vscale x 1 x i1>,
   <vscale x 1 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 1 x i64> @intrinsic_viota_mask_m_nxv1i64_nxv1i1(<vscale x 1 x i64> %0, <vscale x 1 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv1i64_nxv1i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m1, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 1 x i64> @llvm.riscv.viota.mask.nxv1i64(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i1> %1,
     <vscale x 1 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 1 x i64> %a
 }
 
 declare <vscale x 2 x i64> @llvm.riscv.viota.nxv2i64(
   <vscale x 2 x i64>,
   <vscale x 2 x i1>,
   iXLen);
entry:
 
   ret <vscale x 2 x i64> %a
 }
 
 declare <vscale x 2 x i64> @llvm.riscv.viota.mask.nxv2i64(
   <vscale x 2 x i64>,
   <vscale x 2 x i1>,
   <vscale x 2 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 2 x i64> @intrinsic_viota_mask_m_nxv2i64_nxv2i1(<vscale x 2 x i64> %0, <vscale x 2 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv2i64_nxv2i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m2, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 2 x i64> @llvm.riscv.viota.mask.nxv2i64(
     <vscale x 2 x i64> %0,
     <vscale x 2 x i1> %1,
     <vscale x 2 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 2 x i64> %a
 }
 
 declare <vscale x 4 x i64> @llvm.riscv.viota.nxv4i64(
   <vscale x 4 x i64>,
   <vscale x 4 x i1>,
   iXLen);
entry:
 
   ret <vscale x 4 x i64> %a
 }
 
 declare <vscale x 4 x i64> @llvm.riscv.viota.mask.nxv4i64(
   <vscale x 4 x i64>,
   <vscale x 4 x i1>,
   <vscale x 4 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 4 x i64> @intrinsic_viota_mask_m_nxv4i64_nxv4i1(<vscale x 4 x i64> %0, <vscale x 4 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv4i64_nxv4i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m4, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 4 x i64> @llvm.riscv.viota.mask.nxv4i64(
     <vscale x 4 x i64> %0,
     <vscale x 4 x i1> %1,
     <vscale x 4 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 4 x i64> %a
 }
 
 declare <vscale x 8 x i64> @llvm.riscv.viota.nxv8i64(
   <vscale x 8 x i64>,
   <vscale x 8 x i1>,
   iXLen);
entry:
 
   ret <vscale x 8 x i64> %a
 }
 
 declare <vscale x 8 x i64> @llvm.riscv.viota.mask.nxv8i64(
   <vscale x 8 x i64>,
   <vscale x 8 x i1>,
   <vscale x 8 x i1>,
-  iXLen);
+  iXLen, iXLen);
 
 define <vscale x 8 x i64> @intrinsic_viota_mask_m_nxv8i64_nxv8i1(<vscale x 8 x i64> %0, <vscale x 8 x i1> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_viota_mask_m_nxv8i64_nxv8i1:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m8, tu, mu
 ; CHECK-NEXT:    viota.m v8, v0, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %a = call <vscale x 8 x i64> @llvm.riscv.viota.mask.nxv8i64(
     <vscale x 8 x i64> %0,
     <vscale x 8 x i1> %1,
     <vscale x 8 x i1> %1,
-    iXLen %2)
+    iXLen %2, iXLen 0)
 
   ret <vscale x 8 x i64> %a
 }