User Details
User Details
- User Since
- Nov 12 2020, 11:37 PM (149 w, 4 d)
Jul 9 2023
Jul 9 2023
lhtin added a comment to D154576: [RISCV] RISCV vector calling convention (1/2).
Mar 13 2022
Mar 13 2022
lhtin committed rG1648852c9807: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32 (authored by lhtin).
[RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32
Mar 13 2022, 3:07 AM · Restricted Project
Mar 12 2022
Mar 12 2022
lhtin updated the diff for D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.
Rebase and thank @craig.topper and @kito-cheng for your comments.
Mar 10 2022
Mar 10 2022
lhtin removed a project from D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32: Restricted Project.
lhtin updated the diff for D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.
Update code based on review.
Mar 8 2022
Mar 8 2022
lhtin updated the diff for D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.
update as suggested by @craig.topper
Mar 7 2022
Mar 7 2022
lhtin updated the diff for D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.
Update as suggested by @kito-cheng
lhtin added a reviewer for D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32: kito-cheng.
Mar 6 2022
Mar 6 2022
lhtin updated the diff for D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.
add getMaxVLen and encodeSEW helper function
Herald added a project to D120228: [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR intrinsics.: Restricted Project.
Mar 5 2022
Mar 5 2022
lhtin updated the diff for D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.
Updated based on reviews
lhtin updated the diff for D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.
updating based on the latest main branch
lhtin updated the diff for D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.
I fixed the extra bug found by the review and made some optimizations for the case where AVL is constant.
This is my first patch to the llvm project. Please feel free to point out any irregularities. Thanks.
Mar 4 2022
Mar 4 2022
lhtin added a comment to D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.
Mar 3 2022
Mar 3 2022
lhtin updated the summary of D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.
lhtin requested review of D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.