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lhtin (Lehua Ding)
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User Since
Nov 12 2020, 11:37 PM (149 w, 4 d)

Recent Activity

Jul 9 2023

lhtin added a comment to D154576: [RISCV] RISCV vector calling convention (1/2).

Does this only change the calling convention when __attribute__((riscv_vector_cc)) is used? The attribute should be mentioned in the patch description.

Yes it only changes when __attribute__((riscv_vector_cc)) is used, thanks for reminding, I will mention in the description.

Jul 9 2023, 6:24 PM · Restricted Project, Restricted Project, Restricted Project

Mar 13 2022

lhtin committed rG1648852c9807: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32 (authored by lhtin).
[RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32
Mar 13 2022, 3:07 AM · Restricted Project
lhtin closed D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.
Mar 13 2022, 3:07 AM · Restricted Project, Restricted Project

Mar 12 2022

lhtin updated the diff for D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.

Rebase and thank @craig.topper and @kito-cheng for your comments.

Mar 12 2022, 10:42 PM · Restricted Project, Restricted Project

Mar 10 2022

lhtin removed a project from D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32: Restricted Project.
Mar 10 2022, 4:56 PM · Restricted Project, Restricted Project
lhtin updated the diff for D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.

Update code based on review.

Mar 10 2022, 6:13 AM · Restricted Project, Restricted Project

Mar 8 2022

lhtin updated the diff for D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.

update as suggested by @craig.topper

Mar 8 2022, 4:15 AM · Restricted Project, Restricted Project

Mar 7 2022

lhtin updated the diff for D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.

Update as suggested by @kito-cheng

Mar 7 2022, 7:10 AM · Restricted Project, Restricted Project
lhtin added a reviewer for D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32: kito-cheng.
Mar 7 2022, 6:36 AM · Restricted Project, Restricted Project
lhtin updated lhtin.
Mar 7 2022, 4:16 AM

Mar 6 2022

lhtin updated the diff for D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.

add getMaxVLen and encodeSEW helper function

Mar 6 2022, 10:48 PM · Restricted Project, Restricted Project
Herald added a project to D120228: [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR intrinsics.: Restricted Project.
Mar 6 2022, 1:06 AM · Restricted Project, Restricted Project, Restricted Project

Mar 5 2022

lhtin updated the diff for D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.

Updated based on reviews

Mar 5 2022, 11:32 PM · Restricted Project, Restricted Project
lhtin updated the diff for D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.

updating based on the latest main branch

Mar 5 2022, 5:14 PM · Restricted Project, Restricted Project
lhtin updated the diff for D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.

I fixed the extra bug found by the review and made some optimizations for the case where AVL is constant.
This is my first patch to the llvm project. Please feel free to point out any irregularities. Thanks.

Mar 5 2022, 9:47 AM · Restricted Project, Restricted Project

Mar 4 2022

lhtin added a comment to D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.

This isn't the only problem with this code. It's broken for CPUs that implement this sentence from the spec. "this permits an implementation to set vl = ceil(AVL / 2) for VLMAX < AVL < 2*VLMAX".

As a concrete example:
If SEW=64 VLMAX is 8 and AVL is 9. The implementation is allowed to return 5 for the VL.
If we multiply the 9 by 2 we create an AVL of 18 for the SEW=32. The implementation is would be allowed to return 9 for the VL. We need it to return 10 to be 2x5 to match the SEW=64 VL.

The only way I see out of this is to insert a SEW=64 vsetvli to explicitly create a VL less than or equal to the SEW=64 VLMAX, then multiply that by 2. This will fix both the overflow you identified and the case I just described.

Mar 4 2022, 12:06 AM · Restricted Project, Restricted Project

Mar 3 2022

lhtin updated the summary of D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.
Mar 3 2022, 5:44 AM · Restricted Project, Restricted Project
lhtin requested review of D120899: [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32.
Mar 3 2022, 5:44 AM · Restricted Project, Restricted Project