[RISCV] Add initial support for getRegUsageForType and getNumberOfRegisters

[kito-cheng]

Summary

Those two TTI hooks are used during vectorization for calculating
register pressure, the default implementation isn't consider for LMUL,
and that's also definitly wrong value for register number (all register class
are 8 registers).

So in this patch we tried to:

1. Calculate right register usage for vector type and scalar type.
2. Return right number of register for general purpose register and vector register.

[kito-cheng]

Minor cleanup

[kito-cheng]

Minor cleanup

[craig.topper]

llvm/lib/Target/RISCV/RISCVSubtarget.h

132

No else after return

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

283

Don't use auto

287

No else after return

291

Don't use auto

292

Drop curly braces

[kito-cheng]

Changes:

• Address @craig.topper's comment

[kito-cheng]

Minor cleanup

[craig.topper]

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

289

Does this give a different answer than what the default implementation using getTypeLegalizationCost would give?

[craig.topper]

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

289

Err nevermind. Of course it would

292

Can we fall back to the default implementation for non-vector?

[kito-cheng]

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

292

Although I think the default one is not good, but we didn't find good way to testing those part yet, so OK to me.

[craig.topper]

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

292

It's calling getTypeLegalizationCost which should say how many pieces a GPR splits into. I'm not sure what the right answer for FP is because FP can't be split.

[kito-cheng]

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

292

Oh, I got that, I thought the default one is this, which is always return 1:
https://llvm.org/doxygen/TargetTransformInfoImpl_8h_source.html#l00305

But it should be this one:
https://llvm.org/doxygen/BasicTTIImpl_8h_source.html#l00365

[kito-cheng]

Changes:

• Use BasicTTIImplBase::getRegUsageForType for non-vector types.

[craig.topper]

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

285

Do we need to check the V extension is enabled here?

[kito-cheng]

Changes:

• Check V ext. when calculating register usage for scalable types.

[kito-cheng]

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

285

Good catch, thanks!

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVSubtarget.h

public:
   bool hasStdExtZfh() const { return HasStdExtZfh; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
   bool enableSaveRestore() const { return EnableSaveRestore; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
+  unsigned getFLen() const {
+    if (HasStdExtD)
+      return 64;
+
+    if (HasStdExtF)
+      return 32;
+
+    return 0;
+  }
   RISCVABI::ABI getTargetABI() const { return TargetABI; }
   bool isRegisterReservedByUser(Register i) const {
     assert(i < RISCV::NUM_TARGET_REGS && "Register out of range");
     return UserReservedRegister[i];
   }
 
   // Vector codegen related methods.
   bool hasVInstructions() const { return HasStdExtV; }

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

public:
   TargetTransformInfo::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
 
   bool shouldExpandReduction(const IntrinsicInst *II) const;
   bool supportsScalableVectors() const { return ST->hasVInstructions(); }
   Optional<unsigned> getMaxVScale() const;
 
   TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const;
 
+  InstructionCost getRegUsageForType(Type *Ty);
+
   void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
                                TTI::UnrollingPreferences &UP,
                                OptimizationRemarkEmitter *ORE);
 
   void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
                              TTI::PeelingPreferences &PP);
 
   unsigned getMinVectorRegisterBitWidth() const {
bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc,
     }
   }
 
   unsigned getMaxInterleaveFactor(unsigned VF) {
     // If the loop will not be vectorized, don't interleave the loop.
     // Let regular unroll to unroll the loop.
     return VF == 1 ? 1 : ST->getMaxInterleaveFactor();
   }
+
+  // TODO: We should define RISC-V's own register classes.
+  //       e.g. register class for FPR.
+  unsigned getNumberOfRegisters(unsigned ClassID) const {
+    bool Vector = (ClassID == 1);
+    if (Vector) {
+      if (ST->hasVInstructions())
+        return 32;
+      return 0;
+    }
+    // 31 = 32 GPR - x0 (zero register)
+    // FIXME: Should we exclude fixed registers like SP, TP or GP?
+    return 31;
+  }
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

void RISCVTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
   if (Cost < 12)
     UP.Force = true;
 }
 
 void RISCVTTIImpl::getPeelingPreferences(Loop *L, ScalarEvolution &SE,
                                          TTI::PeelingPreferences &PP) {
   BaseT::getPeelingPreferences(L, SE, PP);
 }
+
+InstructionCost RISCVTTIImpl::getRegUsageForType(Type *Ty) {
+  TypeSize Size = Ty->getPrimitiveSizeInBits();
+  if (Ty->isVectorTy()) {
+    if (Size.isScalable() && ST->hasVInstructions())
+      return divideCeil(Size.getKnownMinValue(), RISCV::RVVBitsPerBlock);
+
+    if (ST->useRVVForFixedLengthVectors())
+      return divideCeil(Size, ST->getMinRVVVectorSizeInBits());
+  }
+
+  return BaseT::getRegUsageForType(Ty);
+}

llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll

+; REQUIRES: asserts
+; RUN: opt -loop-vectorize -mtriple riscv64-linux-gnu \
+; RUN:   -mattr=+experimental-v,+d -debug-only=loop-vectorize \
+; RUN:   -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=1 \
+; RUN:   -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL1
+; RUN: opt -loop-vectorize -mtriple riscv64-linux-gnu \
+; RUN:   -mattr=+experimental-v,+d -debug-only=loop-vectorize \
+; RUN:   -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=2 \
+; RUN:   -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL2
+; RUN: opt -loop-vectorize -mtriple riscv64-linux-gnu \
+; RUN:   -mattr=+experimental-v,+d -debug-only=loop-vectorize \
+; RUN:   -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=4 \
+; RUN:   -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL4
+; RUN: opt -loop-vectorize -mtriple riscv64-linux-gnu \
+; RUN:   -mattr=+experimental-v,+d -debug-only=loop-vectorize \
+; RUN:   -riscv-v-vector-bits-min=128 -riscv-v-register-bit-width-lmul=8 \
+; RUN:   -S < %s 2>&1 | FileCheck %s --check-prefix=CHECK-LMUL8
+
+define void @add(float* noalias nocapture readonly %src1, float* noalias nocapture readonly %src2, i32 signext %size, float* noalias nocapture writeonly %result) {
+; CHECK-LABEL: add
+; CHECK-LMUL1:      LV(REG): Found max usage: 2 item
+; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers
+; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 2 registers
+; CHECK-LMUL1-NEXT: LV(REG): Found invariant usage: 1 item
+; CHECK-LMUL1-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 2 registers
+; CHECK-LMUL2:      LV(REG): Found max usage: 2 item
+; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers
+; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 4 registers
+; CHECK-LMUL2-NEXT: LV(REG): Found invariant usage: 1 item
+; CHECK-LMUL2-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 4 registers
+; CHECK-LMUL4:      LV(REG): Found max usage: 2 item
+; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers
+; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 8 registers
+; CHECK-LMUL4-NEXT: LV(REG): Found invariant usage: 1 item
+; CHECK-LMUL4-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 8 registers
+; CHECK-LMUL8:      LV(REG): Found max usage: 2 item
+; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: Generic::ScalarRC, 2 registers
+; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 16 registers
+; CHECK-LMUL8-NEXT: LV(REG): Found invariant usage: 1 item
+; CHECK-LMUL8-NEXT: LV(REG): RegisterClass: Generic::VectorRC, 16 registers
+
+entry:
+  %conv = zext i32 %size to i64
+  %cmp10.not = icmp eq i32 %size, 0
+  br i1 %cmp10.not, label %for.cond.cleanup, label %for.body
+
+for.cond.cleanup:
+  ret void
+
+for.body:
+  %i.011 = phi i64 [ %add4, %for.body ], [ 0, %entry ]
+  %arrayidx = getelementptr inbounds float, float* %src1, i64 %i.011
+  %0 = load float, float* %arrayidx, align 4
+  %arrayidx2 = getelementptr inbounds float, float* %src2, i64 %i.011
+  %1 = load float, float* %arrayidx2, align 4
+  %add = fadd float %0, %1
+  %arrayidx3 = getelementptr inbounds float, float* %result, i64 %i.011
+  store float %add, float* %arrayidx3, align 4
+  %add4 = add nuw nsw i64 %i.011, 1
+  %exitcond.not = icmp eq i64 %add4, %conv
+  br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
+}