[RISCV] Prevent crashes when bitcasting between fixed vectors and scalars.

[craig.topper]

Summary

Not all scalar element types are allowed in vectors so we may not
be able to bitcast to a 1 element vector to use insert/extract.

This will become a bigger issue when the Zve extensions are commited.
For now, I'm using the ELEN limit to limit the element types.

[frasercrmck]

LGTM, good catch!

[foad]

This causes a crash in lit testing in my LLVM_ENABLE_EXPENSIVE_CHECKS build:

$ git checkout main~13 && ninja -C ~/llvm-expensive/ llc && ~/llvm-release/bin/llvm-lit -s -vv test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
Previous HEAD position was 48bb5f4cbe8d [clang] Add early exit when checking for const init of arrays.
HEAD is now at 57bc7b108937 [RISCV] Prevent crashes when bitcasting between fixed vectors and scalars.
ninja: Entering directory `/home/jayfoad2/llvm-expensive/'
[4/4] Linking CXX executable bin/llc
FAIL: LLVM :: CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll (1 of 1)
******************** TEST 'LLVM :: CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll' FAILED ********************
Script:
--
: 'RUN: at line 2';   /home/jayfoad2/llvm-release/bin/llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs      -riscv-v-vector-bits-min=128 -target-abi=ilp32d < /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll      | /home/jayfoad2/llvm-release/bin/FileCheck /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll --check-prefixes=CHECK,RV32
: 'RUN: at line 5';   /home/jayfoad2/llvm-release/bin/llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs      -riscv-v-vector-bits-min=128 -target-abi=lp64d < /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll      | /home/jayfoad2/llvm-release/bin/FileCheck /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll --check-prefixes=CHECK,RV64
: 'RUN: at line 8';   /home/jayfoad2/llvm-release/bin/llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs      -riscv-v-vector-bits-min=128      -riscv-v-fixed-length-vector-elen-max=32 -target-abi=ilp32d < /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll      | /home/jayfoad2/llvm-release/bin/FileCheck /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll --check-prefixes=ELEN32,RV32ELEN32
: 'RUN: at line 12';   /home/jayfoad2/llvm-release/bin/llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs      -riscv-v-vector-bits-min=128      -riscv-v-fixed-length-vector-elen-max=32 -target-abi=lp64d < /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll      | /home/jayfoad2/llvm-release/bin/FileCheck /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll --check-prefixes=ELEN32,RV64ELEN32
--
Exit Code: 1

Command Output (stderr):
--
+ : 'RUN: at line 2'
+ /home/jayfoad2/llvm-release/bin/llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs -riscv-v-vector-bits-min=128 -target-abi=ilp32d
+ /home/jayfoad2/llvm-release/bin/FileCheck /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll --check-prefixes=CHECK,RV32
+ : 'RUN: at line 5'
+ /home/jayfoad2/llvm-release/bin/llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs -riscv-v-vector-bits-min=128 -target-abi=lp64d
+ /home/jayfoad2/llvm-release/bin/FileCheck /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll --check-prefixes=CHECK,RV64
+ : 'RUN: at line 8'
+ /home/jayfoad2/llvm-release/bin/llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=32 -target-abi=ilp32d
+ /home/jayfoad2/llvm-release/bin/FileCheck /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll --check-prefixes=ELEN32,RV32ELEN32
llc: /home/jayfoad2/git/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:979: void (anonymous namespace)::SelectionDAGLegalize::LegalizeOp(llvm::SDNode *): Assertion `(TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) == TargetLowering::TypeLegal || Op.getOpcode() == ISD::TargetConstant || Op.getOpcode() == ISD::Register) && "Unexpected illegal type!"' failed.
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0.	Program arguments: /home/jayfoad2/llvm-release/bin/llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=32 -target-abi=ilp32d
1.	Running pass 'Function Pass Manager' on module '<stdin>'.
2.	Running pass 'RISCV DAG->DAG Pattern Instruction Selection' on function '@bitcast_v8i8_f64'
 #0 0x00000000052aa793 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/home/jayfoad2/llvm-release/bin/llc+0x52aa793)
 #1 0x00000000052a84de llvm::sys::RunSignalHandlers() (/home/jayfoad2/llvm-release/bin/llc+0x52a84de)
 #2 0x00000000052aab1f SignalHandler(int) Signals.cpp:0:0
 #3 0x00007fd1cbd723c0 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x153c0)
 #4 0x00007fd1cb80618b raise /build/glibc-eX1tMB/glibc-2.31/signal/../sysdeps/unix/sysv/linux/raise.c:51:1
 #5 0x00007fd1cb7e5859 abort /build/glibc-eX1tMB/glibc-2.31/stdlib/abort.c:81:7
 #6 0x00007fd1cb7e5729 get_sysdep_segment_value /build/glibc-eX1tMB/glibc-2.31/intl/loadmsgcat.c:509:8
 #7 0x00007fd1cb7e5729 _nl_load_domain /build/glibc-eX1tMB/glibc-2.31/intl/loadmsgcat.c:970:34
 #8 0x00007fd1cb7f6f36 (/lib/x86_64-linux-gnu/libc.so.6+0x36f36)
 #9 0x0000000004fcc33a (anonymous namespace)::SelectionDAGLegalize::LegalizeOp(llvm::SDNode*) LegalizeDAG.cpp:0:0
#10 0x0000000004fcc08a llvm::SelectionDAG::Legalize() (/home/jayfoad2/llvm-release/bin/llc+0x4fcc08a)
#11 0x00000000050d953c llvm::SelectionDAGISel::CodeGenAndEmitDAG() (/home/jayfoad2/llvm-release/bin/llc+0x50d953c)
#12 0x00000000050d73be llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) (/home/jayfoad2/llvm-release/bin/llc+0x50d73be)
#13 0x00000000050d3dfa llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) (/home/jayfoad2/llvm-release/bin/llc+0x50d3dfa)
#14 0x00000000045fd29e llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (/home/jayfoad2/llvm-release/bin/llc+0x45fd29e)
#15 0x0000000004a48fa8 llvm::FPPassManager::runOnFunction(llvm::Function&) (/home/jayfoad2/llvm-release/bin/llc+0x4a48fa8)
#16 0x0000000004a4f7a8 llvm::FPPassManager::runOnModule(llvm::Module&) (/home/jayfoad2/llvm-release/bin/llc+0x4a4f7a8)
#17 0x0000000004a49657 llvm::legacy::PassManagerImpl::run(llvm::Module&) (/home/jayfoad2/llvm-release/bin/llc+0x4a49657)
#18 0x0000000002ee12cc main (/home/jayfoad2/llvm-release/bin/llc+0x2ee12cc)
#19 0x00007fd1cb7e70b3 __libc_start_main /build/glibc-eX1tMB/glibc-2.31/csu/../csu/libc-start.c:342:3
#20 0x0000000002ede7ce _start (/home/jayfoad2/llvm-release/bin/llc+0x2ede7ce)
/home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll:262:17: error: ELEN32-LABEL: expected string not found in input
; ELEN32-LABEL: bitcast_v1i64_i64:
                ^
<stdin>:130:19: note: scanning from here
bitcast_v2i32_i64: # @bitcast_v2i32_i64
                  ^
<stdin>:130:23: note: possible intended match here
bitcast_v2i32_i64: # @bitcast_v2i32_i64
                      ^

Input file: <stdin>
Check file: /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
             .
             .
             .
           125:  .cfi_endproc 
           126:  # -- End function 
           127:  .globl bitcast_v2i32_i64 # -- Begin function bitcast_v2i32_i64 
           128:  .p2align 2 
           129:  .type bitcast_v2i32_i64,@function 
           130: bitcast_v2i32_i64: # @bitcast_v2i32_i64 
label:262'0                       X~~~~~~~~~~~~~~~~~~~~~ error: no match found
label:262'1                           ?                  possible intended match
           131:  .cfi_startproc 
label:262'0     ~~~~~~~~~~~~~~~~
           132: # %bb.0: 
label:262'0     ~~~~~~~~~
           133:  vsetivli zero, 1, e32, m
label:262'0     ~~~~~~~~~~~~~~~~~~~~~~~~~
>>>>>>

--

********************
********************
Failed Tests (1):
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll


Testing Time: 0.20s
  Failed: 1

[craig.topper]

In D113219#3122231, @foad wrote:

This causes a crash in lit testing in my LLVM_ENABLE_EXPENSIVE_CHECKS build:

$ git checkout main~13 && ninja -C ~/llvm-expensive/ llc && ~/llvm-release/bin/llvm-lit -s -vv test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
Previous HEAD position was 48bb5f4cbe8d [clang] Add early exit when checking for const init of arrays.
HEAD is now at 57bc7b108937 [RISCV] Prevent crashes when bitcasting between fixed vectors and scalars.
ninja: Entering directory `/home/jayfoad2/llvm-expensive/'
[4/4] Linking CXX executable bin/llc
FAIL: LLVM :: CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll (1 of 1)
******************** TEST 'LLVM :: CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll' FAILED ********************
Script:
--
: 'RUN: at line 2';   /home/jayfoad2/llvm-release/bin/llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs      -riscv-v-vector-bits-min=128 -target-abi=ilp32d < /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll      | /home/jayfoad2/llvm-release/bin/FileCheck /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll --check-prefixes=CHECK,RV32
: 'RUN: at line 5';   /home/jayfoad2/llvm-release/bin/llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs      -riscv-v-vector-bits-min=128 -target-abi=lp64d < /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll      | /home/jayfoad2/llvm-release/bin/FileCheck /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll --check-prefixes=CHECK,RV64
: 'RUN: at line 8';   /home/jayfoad2/llvm-release/bin/llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs      -riscv-v-vector-bits-min=128      -riscv-v-fixed-length-vector-elen-max=32 -target-abi=ilp32d < /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll      | /home/jayfoad2/llvm-release/bin/FileCheck /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll --check-prefixes=ELEN32,RV32ELEN32
: 'RUN: at line 12';   /home/jayfoad2/llvm-release/bin/llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs      -riscv-v-vector-bits-min=128      -riscv-v-fixed-length-vector-elen-max=32 -target-abi=lp64d < /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll      | /home/jayfoad2/llvm-release/bin/FileCheck /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll --check-prefixes=ELEN32,RV64ELEN32
--
Exit Code: 1

Command Output (stderr):
--
+ : 'RUN: at line 2'
+ /home/jayfoad2/llvm-release/bin/llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs -riscv-v-vector-bits-min=128 -target-abi=ilp32d
+ /home/jayfoad2/llvm-release/bin/FileCheck /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll --check-prefixes=CHECK,RV32
+ : 'RUN: at line 5'
+ /home/jayfoad2/llvm-release/bin/llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs -riscv-v-vector-bits-min=128 -target-abi=lp64d
+ /home/jayfoad2/llvm-release/bin/FileCheck /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll --check-prefixes=CHECK,RV64
+ : 'RUN: at line 8'
+ /home/jayfoad2/llvm-release/bin/llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=32 -target-abi=ilp32d
+ /home/jayfoad2/llvm-release/bin/FileCheck /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll --check-prefixes=ELEN32,RV32ELEN32
llc: /home/jayfoad2/git/llvm-project/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:979: void (anonymous namespace)::SelectionDAGLegalize::LegalizeOp(llvm::SDNode *): Assertion `(TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) == TargetLowering::TypeLegal || Op.getOpcode() == ISD::TargetConstant || Op.getOpcode() == ISD::Register) && "Unexpected illegal type!"' failed.
PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.
Stack dump:
0.	Program arguments: /home/jayfoad2/llvm-release/bin/llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-elen-max=32 -target-abi=ilp32d
1.	Running pass 'Function Pass Manager' on module '<stdin>'.
2.	Running pass 'RISCV DAG->DAG Pattern Instruction Selection' on function '@bitcast_v8i8_f64'
 #0 0x00000000052aa793 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/home/jayfoad2/llvm-release/bin/llc+0x52aa793)
 #1 0x00000000052a84de llvm::sys::RunSignalHandlers() (/home/jayfoad2/llvm-release/bin/llc+0x52a84de)
 #2 0x00000000052aab1f SignalHandler(int) Signals.cpp:0:0
 #3 0x00007fd1cbd723c0 __restore_rt (/lib/x86_64-linux-gnu/libpthread.so.0+0x153c0)
 #4 0x00007fd1cb80618b raise /build/glibc-eX1tMB/glibc-2.31/signal/../sysdeps/unix/sysv/linux/raise.c:51:1
 #5 0x00007fd1cb7e5859 abort /build/glibc-eX1tMB/glibc-2.31/stdlib/abort.c:81:7
 #6 0x00007fd1cb7e5729 get_sysdep_segment_value /build/glibc-eX1tMB/glibc-2.31/intl/loadmsgcat.c:509:8
 #7 0x00007fd1cb7e5729 _nl_load_domain /build/glibc-eX1tMB/glibc-2.31/intl/loadmsgcat.c:970:34
 #8 0x00007fd1cb7f6f36 (/lib/x86_64-linux-gnu/libc.so.6+0x36f36)
 #9 0x0000000004fcc33a (anonymous namespace)::SelectionDAGLegalize::LegalizeOp(llvm::SDNode*) LegalizeDAG.cpp:0:0
#10 0x0000000004fcc08a llvm::SelectionDAG::Legalize() (/home/jayfoad2/llvm-release/bin/llc+0x4fcc08a)
#11 0x00000000050d953c llvm::SelectionDAGISel::CodeGenAndEmitDAG() (/home/jayfoad2/llvm-release/bin/llc+0x50d953c)
#12 0x00000000050d73be llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) (/home/jayfoad2/llvm-release/bin/llc+0x50d73be)
#13 0x00000000050d3dfa llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) (/home/jayfoad2/llvm-release/bin/llc+0x50d3dfa)
#14 0x00000000045fd29e llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (/home/jayfoad2/llvm-release/bin/llc+0x45fd29e)
#15 0x0000000004a48fa8 llvm::FPPassManager::runOnFunction(llvm::Function&) (/home/jayfoad2/llvm-release/bin/llc+0x4a48fa8)
#16 0x0000000004a4f7a8 llvm::FPPassManager::runOnModule(llvm::Module&) (/home/jayfoad2/llvm-release/bin/llc+0x4a4f7a8)
#17 0x0000000004a49657 llvm::legacy::PassManagerImpl::run(llvm::Module&) (/home/jayfoad2/llvm-release/bin/llc+0x4a49657)
#18 0x0000000002ee12cc main (/home/jayfoad2/llvm-release/bin/llc+0x2ee12cc)
#19 0x00007fd1cb7e70b3 __libc_start_main /build/glibc-eX1tMB/glibc-2.31/csu/../csu/libc-start.c:342:3
#20 0x0000000002ede7ce _start (/home/jayfoad2/llvm-release/bin/llc+0x2ede7ce)
/home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll:262:17: error: ELEN32-LABEL: expected string not found in input
; ELEN32-LABEL: bitcast_v1i64_i64:
                ^
<stdin>:130:19: note: scanning from here
bitcast_v2i32_i64: # @bitcast_v2i32_i64
                  ^
<stdin>:130:23: note: possible intended match here
bitcast_v2i32_i64: # @bitcast_v2i32_i64
                      ^

Input file: <stdin>
Check file: /home/jayfoad2/git/llvm-project/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll

-dump-input=help explains the following input dump.

Input was:
<<<<<<
             .
             .
             .
           125:  .cfi_endproc 
           126:  # -- End function 
           127:  .globl bitcast_v2i32_i64 # -- Begin function bitcast_v2i32_i64 
           128:  .p2align 2 
           129:  .type bitcast_v2i32_i64,@function 
           130: bitcast_v2i32_i64: # @bitcast_v2i32_i64 
label:262'0                       X~~~~~~~~~~~~~~~~~~~~~ error: no match found
label:262'1                           ?                  possible intended match
           131:  .cfi_startproc 
label:262'0     ~~~~~~~~~~~~~~~~
           132: # %bb.0: 
label:262'0     ~~~~~~~~~
           133:  vsetivli zero, 1, e32, m
label:262'0     ~~~~~~~~~~~~~~~~~~~~~~~~~
>>>>>>

--

********************
********************
Failed Tests (1):
  LLVM :: CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll


Testing Time: 0.20s
  Failed: 1

I haven't had luck reproducing that error yet, but enabling expensive checks did find another problem that I fixed in 9ee5cec688add4c0589a8ff08f49e274fa6d45a2. Maybe that will fix your crash too?

[foad]

I haven't had luck reproducing that error yet, but enabling expensive checks did find another problem that I fixed in 9ee5cec688add4c0589a8ff08f49e274fa6d45a2. Maybe that will fix your crash too?

Yes that fixed it, thanks!

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (VT.isFixedLengthVector()) {
       // We can handle fixed length vector bitcasts with a simple replacement
       // in isel.
       if (Op0VT.isFixedLengthVector())
         return Op;
       // When bitcasting from scalar to fixed-length vector, insert the scalar
       // into a one-element vector of the result type, and perform a vector
       // bitcast.
       if (!Op0VT.isVector()) {
-        auto BVT = EVT::getVectorVT(*DAG.getContext(), Op0VT, 1);
+        EVT BVT = EVT::getVectorVT(*DAG.getContext(), Op0VT, 1);
+        if (!isTypeLegal(BVT))
+          return SDValue();
         return DAG.getBitcast(VT, DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, BVT,
                                               DAG.getUNDEF(BVT), Op0,
                                               DAG.getConstant(0, DL, XLenVT)));
       }
       return SDValue();
     }
     // Custom-legalize bitcasts from fixed-length vector types to scalar types
     // thus: bitcast the vector to a one-element vector type whose element type
     // is the same as the result type, and extract the first element.
     if (!VT.isVector() && Op0VT.isFixedLengthVector()) {
-      LLVMContext &Context = *DAG.getContext();
-      SDValue BVec = DAG.getBitcast(EVT::getVectorVT(Context, VT, 1), Op0);
+      EVT BVT = EVT::getVectorVT(*DAG.getContext(), VT, 1);
+      if (!isTypeLegal(BVT))
+        return SDValue();
+      SDValue BVec = DAG.getBitcast(BVT, Op0);
       return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, BVec,
                          DAG.getConstant(0, DL, XLenVT));
     }
     if (VT == MVT::f16 && Op0VT == MVT::i16 && Subtarget.hasStdExtZfh()) {
       SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Op0);
       SDValue FPConv = DAG.getNode(RISCVISD::FMV_H_X, DL, MVT::f16, NewOp0);
       return FPConv;
     }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
 ; RUN:     -riscv-v-vector-bits-min=128 -target-abi=ilp32d < %s \
 ; RUN:     | FileCheck %s --check-prefixes=CHECK,RV32
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
 ; RUN:     -riscv-v-vector-bits-min=128 -target-abi=lp64d < %s \
 ; RUN:     | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:     -riscv-v-vector-bits-min=128 \
+; RUN:     -riscv-v-fixed-length-vector-elen-max=32 -target-abi=ilp32d < %s \
+; RUN:     | FileCheck %s --check-prefixes=ELEN32,RV32ELEN32
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
+; RUN:     -riscv-v-vector-bits-min=128 \
+; RUN:     -riscv-v-fixed-length-vector-elen-max=32 -target-abi=lp64d < %s \
+; RUN:     | FileCheck %s --check-prefixes=ELEN32,RV64ELEN32
 
 define <32 x i1> @bitcast_v4i8_v32i1(<4 x i8> %a, <32 x i1> %b) {
 ; CHECK-LABEL: bitcast_v4i8_v32i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 32
 ; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, mu
 ; CHECK-NEXT:    vmxor.mm v0, v0, v8
 ; CHECK-NEXT:    ret
+;
+; ELEN32-LABEL: bitcast_v4i8_v32i1:
+; ELEN32:       # %bb.0:
+; ELEN32-NEXT:    addi a0, zero, 32
+; ELEN32-NEXT:    vsetvli zero, a0, e8, m2, ta, mu
+; ELEN32-NEXT:    vmxor.mm v0, v0, v8
+; ELEN32-NEXT:    ret
   %c = bitcast <4 x i8> %a to <32 x i1>
   %d = xor <32 x i1> %b, %c
   ret <32 x i1> %d
 }
 
 define i8 @bitcast_v1i8_i8(<1 x i8> %a) {
 ; CHECK-LABEL: bitcast_v1i8_i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 0, e8, mf8, ta, mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
+;
+; ELEN32-LABEL: bitcast_v1i8_i8:
+; ELEN32:       # %bb.0:
+; ELEN32-NEXT:    vsetivli zero, 0, e8, mf4, ta, mu
+; ELEN32-NEXT:    vmv.x.s a0, v8
+; ELEN32-NEXT:    ret
   %b = bitcast <1 x i8> %a to i8
   ret i8 %b
 }
 
 define i16 @bitcast_v2i8_i16(<2 x i8> %a) {
 ; CHECK-LABEL: bitcast_v2i8_i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 0, e16, mf4, ta, mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
+;
+; ELEN32-LABEL: bitcast_v2i8_i16:
+; ELEN32:       # %bb.0:
+; ELEN32-NEXT:    vsetivli zero, 0, e16, mf2, ta, mu
+; ELEN32-NEXT:    vmv.x.s a0, v8
+; ELEN32-NEXT:    ret
   %b = bitcast <2 x i8> %a to i16
   ret i16 %b
 }
 
 define i16 @bitcast_v1i16_i16(<1 x i16> %a) {
 ; CHECK-LABEL: bitcast_v1i16_i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 0, e16, mf4, ta, mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
+;
+; ELEN32-LABEL: bitcast_v1i16_i16:
+; ELEN32:       # %bb.0:
+; ELEN32-NEXT:    vsetivli zero, 0, e16, mf2, ta, mu
+; ELEN32-NEXT:    vmv.x.s a0, v8
+; ELEN32-NEXT:    ret
   %b = bitcast <1 x i16> %a to i16
   ret i16 %b
 }
 
 define i32 @bitcast_v4i8_i32(<4 x i8> %a) {
 ; CHECK-LABEL: bitcast_v4i8_i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 0, e32, mf2, ta, mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
+;
+; ELEN32-LABEL: bitcast_v4i8_i32:
+; ELEN32:       # %bb.0:
+; ELEN32-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
+; ELEN32-NEXT:    vmv.x.s a0, v8
+; ELEN32-NEXT:    ret
   %b = bitcast <4 x i8> %a to i32
   ret i32 %b
 }
 
 define i32 @bitcast_v2i16_i32(<2 x i16> %a) {
 ; CHECK-LABEL: bitcast_v2i16_i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 0, e32, mf2, ta, mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
+;
+; ELEN32-LABEL: bitcast_v2i16_i32:
+; ELEN32:       # %bb.0:
+; ELEN32-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
+; ELEN32-NEXT:    vmv.x.s a0, v8
+; ELEN32-NEXT:    ret
   %b = bitcast <2 x i16> %a to i32
   ret i32 %b
 }
 
 define i32 @bitcast_v1i32_i32(<1 x i32> %a) {
 ; CHECK-LABEL: bitcast_v1i32_i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 0, e32, mf2, ta, mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
+;
+; ELEN32-LABEL: bitcast_v1i32_i32:
+; ELEN32:       # %bb.0:
+; ELEN32-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
+; ELEN32-NEXT:    vmv.x.s a0, v8
+; ELEN32-NEXT:    ret
   %b = bitcast <1 x i32> %a to i32
   ret i32 %b
 }
 
 define i64 @bitcast_v8i8_i64(<8 x i8> %a) {
 ; RV32-LABEL: bitcast_v8i8_i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi a0, zero, 32
 ; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; RV32-NEXT:    vsrl.vx v9, v8, a0
 ; RV32-NEXT:    vmv.x.s a1, v9
 ; RV32-NEXT:    vmv.x.s a0, v8
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitcast_v8i8_i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
 ; RV64-NEXT:    vmv.x.s a0, v8
 ; RV64-NEXT:    ret
+;
+; RV32ELEN32-LABEL: bitcast_v8i8_i64:
+; RV32ELEN32:       # %bb.0:
+; RV32ELEN32-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
+; RV32ELEN32-NEXT:    vslidedown.vi v9, v8, 1
+; RV32ELEN32-NEXT:    vmv.x.s a1, v9
+; RV32ELEN32-NEXT:    vmv.x.s a0, v8
+; RV32ELEN32-NEXT:    ret
+;
+; RV64ELEN32-LABEL: bitcast_v8i8_i64:
+; RV64ELEN32:       # %bb.0:
+; RV64ELEN32-NEXT:    addi sp, sp, -16
+; RV64ELEN32-NEXT:    .cfi_def_cfa_offset 16
+; RV64ELEN32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; RV64ELEN32-NEXT:    addi a0, sp, 8
+; RV64ELEN32-NEXT:    vse8.v v8, (a0)
+; RV64ELEN32-NEXT:    ld a0, 8(sp)
+; RV64ELEN32-NEXT:    addi sp, sp, 16
+; RV64ELEN32-NEXT:    ret
   %b = bitcast <8 x i8> %a to i64
   ret i64 %b
 }
 
 define i64 @bitcast_v4i16_i64(<4 x i16> %a) {
 ; RV32-LABEL: bitcast_v4i16_i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi a0, zero, 32
 ; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; RV32-NEXT:    vsrl.vx v9, v8, a0
 ; RV32-NEXT:    vmv.x.s a1, v9
 ; RV32-NEXT:    vmv.x.s a0, v8
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitcast_v4i16_i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
 ; RV64-NEXT:    vmv.x.s a0, v8
 ; RV64-NEXT:    ret
+;
+; RV32ELEN32-LABEL: bitcast_v4i16_i64:
+; RV32ELEN32:       # %bb.0:
+; RV32ELEN32-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
+; RV32ELEN32-NEXT:    vslidedown.vi v9, v8, 1
+; RV32ELEN32-NEXT:    vmv.x.s a1, v9
+; RV32ELEN32-NEXT:    vmv.x.s a0, v8
+; RV32ELEN32-NEXT:    ret
+;
+; RV64ELEN32-LABEL: bitcast_v4i16_i64:
+; RV64ELEN32:       # %bb.0:
+; RV64ELEN32-NEXT:    addi sp, sp, -16
+; RV64ELEN32-NEXT:    .cfi_def_cfa_offset 16
+; RV64ELEN32-NEXT:    vsetivli zero, 4, e16, mf2, ta, mu
+; RV64ELEN32-NEXT:    addi a0, sp, 8
+; RV64ELEN32-NEXT:    vse16.v v8, (a0)
+; RV64ELEN32-NEXT:    ld a0, 8(sp)
+; RV64ELEN32-NEXT:    addi sp, sp, 16
+; RV64ELEN32-NEXT:    ret
   %b = bitcast <4 x i16> %a to i64
   ret i64 %b
 }
 
 define i64 @bitcast_v2i32_i64(<2 x i32> %a) {
 ; RV32-LABEL: bitcast_v2i32_i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi a0, zero, 32
 ; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; RV32-NEXT:    vsrl.vx v9, v8, a0
 ; RV32-NEXT:    vmv.x.s a1, v9
 ; RV32-NEXT:    vmv.x.s a0, v8
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitcast_v2i32_i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
 ; RV64-NEXT:    vmv.x.s a0, v8
 ; RV64-NEXT:    ret
+;
+; RV32ELEN32-LABEL: bitcast_v2i32_i64:
+; RV32ELEN32:       # %bb.0:
+; RV32ELEN32-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
+; RV32ELEN32-NEXT:    vslidedown.vi v9, v8, 1
+; RV32ELEN32-NEXT:    vmv.x.s a1, v9
+; RV32ELEN32-NEXT:    vmv.x.s a0, v8
+; RV32ELEN32-NEXT:    ret
+;
+; RV64ELEN32-LABEL: bitcast_v2i32_i64:
+; RV64ELEN32:       # %bb.0:
+; RV64ELEN32-NEXT:    addi sp, sp, -16
+; RV64ELEN32-NEXT:    .cfi_def_cfa_offset 16
+; RV64ELEN32-NEXT:    vsetivli zero, 2, e32, m1, ta, mu
+; RV64ELEN32-NEXT:    addi a0, sp, 8
+; RV64ELEN32-NEXT:    vse32.v v8, (a0)
+; RV64ELEN32-NEXT:    ld a0, 8(sp)
+; RV64ELEN32-NEXT:    addi sp, sp, 16
+; RV64ELEN32-NEXT:    ret
   %b = bitcast <2 x i32> %a to i64
   ret i64 %b
 }
 
 define i64 @bitcast_v1i64_i64(<1 x i64> %a) {
 ; RV32-LABEL: bitcast_v1i64_i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi a0, zero, 32
 ; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; RV32-NEXT:    vsrl.vx v9, v8, a0
 ; RV32-NEXT:    vmv.x.s a1, v9
 ; RV32-NEXT:    vmv.x.s a0, v8
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitcast_v1i64_i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
 ; RV64-NEXT:    vmv.x.s a0, v8
 ; RV64-NEXT:    ret
+;
+; ELEN32-LABEL: bitcast_v1i64_i64:
+; ELEN32:       # %bb.0:
+; ELEN32-NEXT:    ret
   %b = bitcast <1 x i64> %a to i64
   ret i64 %b
 }
 
 define half @bitcast_v2i8_f16(<2 x i8> %a) {
 ; CHECK-LABEL: bitcast_v2i8_f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 0, e16, mf4, ta, mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
+;
+; ELEN32-LABEL: bitcast_v2i8_f16:
+; ELEN32:       # %bb.0:
+; ELEN32-NEXT:    vsetivli zero, 0, e16, mf2, ta, mu
+; ELEN32-NEXT:    vfmv.f.s fa0, v8
+; ELEN32-NEXT:    ret
   %b = bitcast <2 x i8> %a to half
   ret half %b
 }
 
 define half @bitcast_v1i16_f16(<1 x i16> %a) {
 ; CHECK-LABEL: bitcast_v1i16_f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 0, e16, mf4, ta, mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
+;
+; ELEN32-LABEL: bitcast_v1i16_f16:
+; ELEN32:       # %bb.0:
+; ELEN32-NEXT:    vsetivli zero, 0, e16, mf2, ta, mu
+; ELEN32-NEXT:    vfmv.f.s fa0, v8
+; ELEN32-NEXT:    ret
   %b = bitcast <1 x i16> %a to half
   ret half %b
 }
 
 define float @bitcast_v4i8_f32(<4 x i8> %a) {
 ; CHECK-LABEL: bitcast_v4i8_f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 0, e32, mf2, ta, mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
+;
+; ELEN32-LABEL: bitcast_v4i8_f32:
+; ELEN32:       # %bb.0:
+; ELEN32-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
+; ELEN32-NEXT:    vfmv.f.s fa0, v8
+; ELEN32-NEXT:    ret
   %b = bitcast <4 x i8> %a to float
   ret float %b
 }
 
 define float @bitcast_v2i16_f32(<2 x i16> %a) {
 ; CHECK-LABEL: bitcast_v2i16_f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 0, e32, mf2, ta, mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
+;
+; ELEN32-LABEL: bitcast_v2i16_f32:
+; ELEN32:       # %bb.0:
+; ELEN32-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
+; ELEN32-NEXT:    vfmv.f.s fa0, v8
+; ELEN32-NEXT:    ret
   %b = bitcast <2 x i16> %a to float
   ret float %b
 }
 
 define float @bitcast_v1i32_f32(<1 x i32> %a) {
 ; CHECK-LABEL: bitcast_v1i32_f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 0, e32, mf2, ta, mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
+;
+; ELEN32-LABEL: bitcast_v1i32_f32:
+; ELEN32:       # %bb.0:
+; ELEN32-NEXT:    vsetivli zero, 0, e32, m1, ta, mu
+; ELEN32-NEXT:    vfmv.f.s fa0, v8
+; ELEN32-NEXT:    ret
   %b = bitcast <1 x i32> %a to float
   ret float %b
 }
 
 define double @bitcast_v8i8_f64(<8 x i8> %a) {
 ; CHECK-LABEL: bitcast_v8i8_f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
+;
+; ELEN32-LABEL: bitcast_v8i8_f64:
+; ELEN32:       # %bb.0:
+; ELEN32-NEXT:    addi sp, sp, -16
+; ELEN32-NEXT:    .cfi_def_cfa_offset 16
+; ELEN32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; ELEN32-NEXT:    addi a0, sp, 8
+; ELEN32-NEXT:    vse8.v v8, (a0)
+; ELEN32-NEXT:    fld fa0, 8(sp)
+; ELEN32-NEXT:    addi sp, sp, 16
+; ELEN32-NEXT:    ret
   %b = bitcast <8 x i8> %a to double
   ret double %b
 }
 
 define double @bitcast_v4i16_f64(<4 x i16> %a) {
 ; CHECK-LABEL: bitcast_v4i16_f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
+;
+; ELEN32-LABEL: bitcast_v4i16_f64:
+; ELEN32:       # %bb.0:
+; ELEN32-NEXT:    addi sp, sp, -16
+; ELEN32-NEXT:    .cfi_def_cfa_offset 16
+; ELEN32-NEXT:    vsetivli zero, 4, e16, mf2, ta, mu
+; ELEN32-NEXT:    addi a0, sp, 8
+; ELEN32-NEXT:    vse16.v v8, (a0)
+; ELEN32-NEXT:    fld fa0, 8(sp)
+; ELEN32-NEXT:    addi sp, sp, 16
+; ELEN32-NEXT:    ret
   %b = bitcast <4 x i16> %a to double
   ret double %b
 }
 
 define double @bitcast_v2i32_f64(<2 x i32> %a) {
 ; CHECK-LABEL: bitcast_v2i32_f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
+;
+; ELEN32-LABEL: bitcast_v2i32_f64:
+; ELEN32:       # %bb.0:
+; ELEN32-NEXT:    addi sp, sp, -16
+; ELEN32-NEXT:    .cfi_def_cfa_offset 16
+; ELEN32-NEXT:    vsetivli zero, 2, e32, m1, ta, mu
+; ELEN32-NEXT:    addi a0, sp, 8
+; ELEN32-NEXT:    vse32.v v8, (a0)
+; ELEN32-NEXT:    fld fa0, 8(sp)
+; ELEN32-NEXT:    addi sp, sp, 16
+; ELEN32-NEXT:    ret
   %b = bitcast <2 x i32> %a to double
   ret double %b
 }
 
 define double @bitcast_v1i64_f64(<1 x i64> %a) {
 ; CHECK-LABEL: bitcast_v1i64_f64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 0, e64, m1, ta, mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
+;
+; RV32ELEN32-LABEL: bitcast_v1i64_f64:
+; RV32ELEN32:       # %bb.0:
+; RV32ELEN32-NEXT:    addi sp, sp, -16
+; RV32ELEN32-NEXT:    .cfi_def_cfa_offset 16
+; RV32ELEN32-NEXT:    sw a1, 12(sp)
+; RV32ELEN32-NEXT:    sw a0, 8(sp)
+; RV32ELEN32-NEXT:    fld fa0, 8(sp)
+; RV32ELEN32-NEXT:    addi sp, sp, 16
+; RV32ELEN32-NEXT:    ret
+;
+; RV64ELEN32-LABEL: bitcast_v1i64_f64:
+; RV64ELEN32:       # %bb.0:
+; RV64ELEN32-NEXT:    addi sp, sp, -16
+; RV64ELEN32-NEXT:    .cfi_def_cfa_offset 16
+; RV64ELEN32-NEXT:    sd a0, 8(sp)
+; RV64ELEN32-NEXT:    fld fa0, 8(sp)
+; RV64ELEN32-NEXT:    addi sp, sp, 16
+; RV64ELEN32-NEXT:    ret
   %b = bitcast <1 x i64> %a to double
   ret double %b
 }
 
 define <1 x i16> @bitcast_i16_v1i16(i16 %a) {
 ; CHECK-LABEL: bitcast_i16_v1i16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, ta, mu
 ; CHECK-NEXT:    vmv.v.x v8, a0
 ; CHECK-NEXT:    ret
+;
+; ELEN32-LABEL: bitcast_i16_v1i16:
+; ELEN32:       # %bb.0:
+; ELEN32-NEXT:    vsetivli zero, 1, e16, mf2, ta, mu
+; ELEN32-NEXT:    vmv.v.x v8, a0
+; ELEN32-NEXT:    ret
   %b = bitcast i16 %a to <1 x i16>
   ret <1 x i16> %b
 }
 
 define <2 x i16> @bitcast_i32_v2i16(i32 %a) {
 ; RV32-LABEL: bitcast_i32_v2i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 1, e32, mf2, ta, mu
 ; RV32-NEXT:    vmv.s.x v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitcast_i32_v2i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 1, e32, mf2, ta, mu
 ; RV64-NEXT:    vmv.v.x v8, a0
 ; RV64-NEXT:    ret
+;
+; RV32ELEN32-LABEL: bitcast_i32_v2i16:
+; RV32ELEN32:       # %bb.0:
+; RV32ELEN32-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
+; RV32ELEN32-NEXT:    vmv.s.x v8, a0
+; RV32ELEN32-NEXT:    ret
+;
+; RV64ELEN32-LABEL: bitcast_i32_v2i16:
+; RV64ELEN32:       # %bb.0:
+; RV64ELEN32-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
+; RV64ELEN32-NEXT:    vmv.v.x v8, a0
+; RV64ELEN32-NEXT:    ret
   %b = bitcast i32 %a to <2 x i16>
   ret <2 x i16> %b
 }
 
 define <1 x i32> @bitcast_i32_v1i32(i32 %a) {
 ; RV32-LABEL: bitcast_i32_v1i32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 1, e32, mf2, ta, mu
 ; RV32-NEXT:    vmv.s.x v8, a0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitcast_i32_v1i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 1, e32, mf2, ta, mu
 ; RV64-NEXT:    vmv.v.x v8, a0
 ; RV64-NEXT:    ret
+;
+; RV32ELEN32-LABEL: bitcast_i32_v1i32:
+; RV32ELEN32:       # %bb.0:
+; RV32ELEN32-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
+; RV32ELEN32-NEXT:    vmv.s.x v8, a0
+; RV32ELEN32-NEXT:    ret
+;
+; RV64ELEN32-LABEL: bitcast_i32_v1i32:
+; RV64ELEN32:       # %bb.0:
+; RV64ELEN32-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
+; RV64ELEN32-NEXT:    vmv.v.x v8, a0
+; RV64ELEN32-NEXT:    ret
   %b = bitcast i32 %a to <1 x i32>
   ret <1 x i32> %b
 }
 
 define <4 x i16> @bitcast_i64_v4i16(i64 %a) {
 ; RV32-LABEL: bitcast_i64_v4i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 2, e32, m1, ta, mu
 ; RV32-NEXT:    vmv.v.i v8, 0
 ; RV32-NEXT:    vslide1up.vx v9, v8, a1
 ; RV32-NEXT:    vslide1up.vx v10, v9, a0
 ; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; RV32-NEXT:    vslideup.vi v8, v10, 0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitcast_i64_v4i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; RV64-NEXT:    vmv.s.x v8, a0
 ; RV64-NEXT:    ret
+;
+; RV32ELEN32-LABEL: bitcast_i64_v4i16:
+; RV32ELEN32:       # %bb.0:
+; RV32ELEN32-NEXT:    vsetivli zero, 2, e32, m1, ta, mu
+; RV32ELEN32-NEXT:    vmv.v.x v8, a1
+; RV32ELEN32-NEXT:    vsetvli zero, zero, e32, m1, tu, mu
+; RV32ELEN32-NEXT:    vmv.s.x v8, a0
+; RV32ELEN32-NEXT:    ret
+;
+; RV64ELEN32-LABEL: bitcast_i64_v4i16:
+; RV64ELEN32:       # %bb.0:
+; RV64ELEN32-NEXT:    addi sp, sp, -16
+; RV64ELEN32-NEXT:    .cfi_def_cfa_offset 16
+; RV64ELEN32-NEXT:    sd a0, 8(sp)
+; RV64ELEN32-NEXT:    vsetivli zero, 4, e16, mf2, ta, mu
+; RV64ELEN32-NEXT:    addi a0, sp, 8
+; RV64ELEN32-NEXT:    vle16.v v8, (a0)
+; RV64ELEN32-NEXT:    addi sp, sp, 16
+; RV64ELEN32-NEXT:    ret
   %b = bitcast i64 %a to <4 x i16>
   ret <4 x i16> %b
 }
 
 define <2 x i32> @bitcast_i64_v2i32(i64 %a) {
 ; RV32-LABEL: bitcast_i64_v2i32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 2, e32, m1, ta, mu
 ; RV32-NEXT:    vmv.v.i v8, 0
 ; RV32-NEXT:    vslide1up.vx v9, v8, a1
 ; RV32-NEXT:    vslide1up.vx v10, v9, a0
 ; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; RV32-NEXT:    vslideup.vi v8, v10, 0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitcast_i64_v2i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; RV64-NEXT:    vmv.s.x v8, a0
 ; RV64-NEXT:    ret
+;
+; RV32ELEN32-LABEL: bitcast_i64_v2i32:
+; RV32ELEN32:       # %bb.0:
+; RV32ELEN32-NEXT:    vsetivli zero, 2, e32, m1, ta, mu
+; RV32ELEN32-NEXT:    vmv.v.x v8, a1
+; RV32ELEN32-NEXT:    vsetvli zero, zero, e32, m1, tu, mu
+; RV32ELEN32-NEXT:    vmv.s.x v8, a0
+; RV32ELEN32-NEXT:    ret
+;
+; RV64ELEN32-LABEL: bitcast_i64_v2i32:
+; RV64ELEN32:       # %bb.0:
+; RV64ELEN32-NEXT:    addi sp, sp, -16
+; RV64ELEN32-NEXT:    .cfi_def_cfa_offset 16
+; RV64ELEN32-NEXT:    sd a0, 8(sp)
+; RV64ELEN32-NEXT:    vsetivli zero, 2, e32, m1, ta, mu
+; RV64ELEN32-NEXT:    addi a0, sp, 8
+; RV64ELEN32-NEXT:    vle32.v v8, (a0)
+; RV64ELEN32-NEXT:    addi sp, sp, 16
+; RV64ELEN32-NEXT:    ret
   %b = bitcast i64 %a to <2 x i32>
   ret <2 x i32> %b
 }
 
 define <1 x i64> @bitcast_i64_v1i64(i64 %a) {
 ; RV32-LABEL: bitcast_i64_v1i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 2, e32, m1, ta, mu
 ; RV32-NEXT:    vmv.v.i v8, 0
 ; RV32-NEXT:    vslide1up.vx v9, v8, a1
 ; RV32-NEXT:    vslide1up.vx v10, v9, a0
 ; RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; RV32-NEXT:    vslideup.vi v8, v10, 0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bitcast_i64_v1i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, mu
 ; RV64-NEXT:    vmv.s.x v8, a0
 ; RV64-NEXT:    ret
+;
+; ELEN32-LABEL: bitcast_i64_v1i64:
+; ELEN32:       # %bb.0:
+; ELEN32-NEXT:    ret
   %b = bitcast i64 %a to <1 x i64>
   ret <1 x i64> %b
 }