[RISCV] Emit DWARF location expression for RVV stack objects.

[HsiangKai]

Summary

VLENB is the length of a vector register in bytes. We use
<vscale x 64 bits> to represent one vector register. The dwarf offset is
VLENB * scalable_offset / 8.

For the mask vector, it occupies one vector register.

[frasercrmck]

Sorry, I'm a bit out of my depth with these DWARF offset opcodes. I think what you're doing here makes sense, though.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

344

Is this path tested by this patch? I don't see any DW_OP_minus in the expected output. I may be missing something, though.

[HsiangKai]

Add test cases for (frame base pointer - VLENB x n).

[frasercrmck]

LGTM. Anyone else?

llvm/lib/Target/RISCV/RISCVRegisterInfo.h

struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
   getPointerRegClass(const MachineFunction &MF,
                      unsigned Kind = 0) const override {
     return &RISCV::GPRRegClass;
   }
 
   const TargetRegisterClass *
   getLargestLegalSuperClass(const TargetRegisterClass *RC,
                             const MachineFunction &) const override;
+
+  void getOffsetOpcodes(const StackOffset &Offset,
+                        SmallVectorImpl<uint64_t> &Ops) const override;
 };
 }
 
 #endif

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

 #include "RISCVMachineFunctionInfo.h"
 #include "RISCVSubtarget.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/IR/DebugInfoMetadata.h"
 #include "llvm/Support/ErrorHandling.h"
 
 #define GET_REGINFO_TARGET_DESC
 #include "RISCVGenRegisterInfo.inc"
 
 using namespace llvm;
 
 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");

 
 const TargetRegisterClass *
 RISCVRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
                                              const MachineFunction &) const {
   if (RC == &RISCV::VMV0RegClass)
     return &RISCV::VRRegClass;
   return RC;
 }
+
+void RISCVRegisterInfo::getOffsetOpcodes(const StackOffset &Offset,
+                                         SmallVectorImpl<uint64_t> &Ops) const {
+  // VLENB is the length of a vector register in bytes. We use <vscale x 8 x i8>
+  // to represent one vector register. The dwarf offset is
+  // VLENB * scalable_offset / 8.
+  assert(Offset.getScalable() % 8 == 0 && "Invalid frame offset");
+
+  // Add fixed-sized offset using existing DIExpression interface.
+  DIExpression::appendOffset(Ops, Offset.getFixed());
+
+  unsigned VLENB = getDwarfRegNum(RISCV::VLENB, true);
+  int64_t VLENBSized = Offset.getScalable() / 8;
+  if (VLENBSized > 0) {
+    Ops.push_back(dwarf::DW_OP_constu);
+    Ops.push_back(VLENBSized);
+    Ops.append({dwarf::DW_OP_bregx, VLENB, 0ULL});
+    Ops.push_back(dwarf::DW_OP_mul);
+    Ops.push_back(dwarf::DW_OP_plus);
+  } else if (VLENBSized < 0) {
+    Ops.push_back(dwarf::DW_OP_constu);
+    Ops.push_back(-VLENBSized);
+    Ops.append({dwarf::DW_OP_bregx, VLENB, 0ULL});
+    Ops.push_back(dwarf::DW_OP_mul);
+    Ops.push_back(dwarf::DW_OP_minus);
+  }
+}

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

def V#Index#M8 : RISCVRegWithSubRegs<Index, "v"#Index,
       let SubRegIndices = [sub_vrm4_0, sub_vrm4_1];
     }
   }
 
   def VTYPE  : RISCVReg<0, "vtype", ["vtype"]>;
   def VL     : RISCVReg<0, "vl", ["vl"]>;
   def VXSAT  : RISCVReg<0, "vxsat", ["vxsat"]>;
   def VXRM   : RISCVReg<0, "vxrm", ["vxrm"]>;
+  def VLENB  : RISCVReg<0, "vlenb", ["vlenb"]>,
+               DwarfRegNum<[!add(4096, SysRegVLENB.Encoding)]>;
 }
 
 foreach m = [1, 2, 4] in {
   foreach n = NFList<m>.L in {
     def "VN" # n # "M" # m # "NoV0": RegisterTuples<
                                        SubRegSet<[], 0, n, m>.L,
                                        VRegList<[], 0, n, m, 1>.L>;
     def "VN" # n # "M" # m # "V0" : RegisterTuples<

llvm/lib/Target/RISCV/RISCVSystemOperands.td

 //===-----------------------------------------------
 // User Vector CSRs
 //===-----------------------------------------------
 def : SysReg<"vstart", 0x008>;
 def : SysReg<"vxsat", 0x009>;
 def : SysReg<"vxrm", 0x00A>;
 def : SysReg<"vl", 0xC20>;
 def : SysReg<"vtype", 0xC21>;
-def : SysReg<"vlenb", 0xC22>;
+def SysRegVLENB: SysReg<"vlenb", 0xC22>;

llvm/test/CodeGen/RISCV/rvv/debug-info-rvv-dbg-value.mir

+# RUN: llc -march=riscv64 -mattr=+experimental-v -o %t -filetype=obj \
+# RUN:   -start-before=prologepilog %s
+# RUN: llvm-dwarfdump --name="value0" %t | FileCheck %s --check-prefix=CHECK0
+# RUN: llvm-dwarfdump --name="value1" %t | FileCheck %s --check-prefix=CHECK1
+# RUN: llvm-dwarfdump --name="value2" %t | FileCheck %s --check-prefix=CHECK2
+# RUN: llvm-dwarfdump --name="value3" %t | FileCheck %s --check-prefix=CHECK3
+# RUN: llvm-dwarfdump --name="value4" %t | FileCheck %s --check-prefix=CHECK4
+# RUN: llvm-dwarfdump --name="value5" %t | FileCheck %s --check-prefix=CHECK5
+
+# CHECK0: : DW_OP_breg2 X2+24)
+# CHECK0: DW_AT_type {{.*}}int32_t
+#
+# CHECK1: : DW_OP_breg2 X2+16)
+# CHECK1: DW_AT_type {{.*}}int32_t
+#
+# CHECK2: : DW_OP_breg2 X2+32, DW_OP_lit3, DW_OP_bregx VLENB+0, DW_OP_mul, DW_OP_plus)
+# CHECK2: DW_AT_type {{.*}}vint32m1_t
+#
+# CHECK3: : DW_OP_breg2 X2+32, DW_OP_lit2, DW_OP_bregx VLENB+0, DW_OP_mul, DW_OP_plus)
+# CHECK3: DW_AT_type {{.*}}vint32m1_t
+#
+# CHECK4: : DW_OP_breg2 X2+32, DW_OP_lit1, DW_OP_bregx VLENB+0, DW_OP_mul, DW_OP_plus)
+# CHECK4: DW_AT_type {{.*}}vbool1_t
+#
+# CHECK5: : DW_OP_breg2 X2+32)
+# CHECK5: DW_AT_type {{.*}}vbool1_t
+
+--- |
+  define void @foo() !dbg !5 {
+  entry:
+    unreachable, !dbg !8
+  }
+
+  ; Function Attrs: nounwind readnone speculatable willreturn
+  declare void @llvm.dbg.value(metadata, metadata, metadata)
+
+  !llvm.dbg.cu = !{!0}
+  !llvm.debugify = !{!3, !3}
+  !llvm.module.flags = !{!4}
+
+  !0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
+  !1 = !DIFile(filename: "debug-info-rvv-dbg-value.mir", directory: "/")
+  !2 = !{}
+  !3 = !{i32 1}
+  !4 = !{i32 2, !"Debug Info Version", i32 3}
+  !5 = distinct !DISubprogram(name: "foo", linkageName: "foo", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !9)
+  !6 = !DISubroutineType(types: !2)
+  !7 = !DIBasicType(name: "int32_t", size: 32, encoding: DW_ATE_signed)
+  !8 = !DILocation(line: 1, column: 1, scope: !5)
+  !9 = !{!10, !11, !12, !13, !14, !15}
+  !10 = !DILocalVariable(name: "value0", scope: !5, file: !1, line: 1, type: !7)
+  !11 = !DILocalVariable(name: "value1", scope: !5, file: !1, line: 1, type: !7)
+  !12 = !DILocalVariable(name: "value2", scope: !5, file: !1, line: 1, type: !16)
+  !13 = !DILocalVariable(name: "value3", scope: !5, file: !1, line: 1, type: !16)
+  !14 = !DILocalVariable(name: "value4", scope: !5, file: !1, line: 1, type: !21)
+  !15 = !DILocalVariable(name: "value5", scope: !5, file: !1, line: 1, type: !21)
+  !16 = !DIDerivedType(tag: DW_TAG_typedef, name: "vint32m1_t", file: !1, line: 1, baseType: !17)
+  !17 = !DIDerivedType(tag: DW_TAG_typedef, name: "__rvv_int32m1_t", file: !1, baseType: !18)
+  !18 = !DICompositeType(tag: DW_TAG_array_type, baseType: !7, flags: DIFlagVector, elements: !19)
+  !19 = !{!20}
+  !20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_constu, 4, DW_OP_div, DW_OP_constu, 1, DW_OP_mul))
+  !21 = !DIDerivedType(tag: DW_TAG_typedef, name: "vbool1_t", file: !1, line: 90, baseType: !22)
+  !22 = !DIDerivedType(tag: DW_TAG_typedef, name: "__rvv_bool1_t", file: !1, baseType: !23)
+  !23 = !DICompositeType(tag: DW_TAG_array_type, baseType: !24, flags: DIFlagVector, elements: !25)
+  !24 = !DIBasicType(name: "_Bool", size: 8, encoding: DW_ATE_boolean)
+  !25 = !{!26}
+  !26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_constu, 1, DW_OP_div, DW_OP_constu, 1, DW_OP_mul))
+
+
+...
+---
+name:            foo
+alignment:       4
+tracksRegLiveness: true
+liveins:
+  - { reg: '$x12' }
+  - { reg: '$x13' }
+  - { reg: '$v8' }
+  - { reg: '$v9' }
+  - { reg: '$v0' }
+  - { reg: '$v1' }
+frameInfo:
+  maxAlignment:    16
+  adjustsStack:    true
+  hasCalls:        true
+  maxCallFrameSize: 0
+  localFrameSize:  4
+stack:
+  - { id: 0, size: 8, alignment: 8 }
+  - { id: 1, size: 8, alignment: 8 }
+  - { id: 2, size: 8, alignment: 4, stack-id: scalable-vector }
+  - { id: 3, size: 8, alignment: 4, stack-id: scalable-vector }
+  - { id: 4, size: 8, alignment: 1, stack-id: scalable-vector }
+  - { id: 5, size: 8, alignment: 1, stack-id: scalable-vector }
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    liveins: $x12, $x13, $v8, $v9, $v0, $v1
+
+    SD killed renamable $x12, %stack.0, 0, debug-location !8
+    DBG_VALUE %stack.0, $noreg, !10, !DIExpression(DW_OP_deref), debug-location !8
+    SD killed renamable $x13, %stack.1, 0, debug-location !8
+    DBG_VALUE %stack.1, $noreg, !11, !DIExpression(DW_OP_deref), debug-location !8
+
+    PseudoVSE32_V_M1 killed renamable $v8, %stack.2, 8, 5, debug-location !DILocation(line: 5, column: 1, scope: !5)
+    DBG_VALUE %stack.2, $noreg, !12, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 5, column: 1, scope: !5)
+    PseudoVSE32_V_M1 killed renamable $v9, %stack.3, 8, 5, debug-location !DILocation(line: 6, column: 1, scope: !5)
+    DBG_VALUE %stack.3, $noreg, !13, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 6, column: 1, scope: !5)
+
+    PseudoVSE1_V_B64 killed renamable $v0, %stack.4, 8, 0, debug-location !DILocation(line: 2, column: 1, scope: !5)
+    DBG_VALUE %stack.4, $noreg, !14, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 2, column: 1, scope: !5)
+    PseudoVSE1_V_B64 killed renamable $v1, %stack.5, 8, 0, debug-location !DILocation(line: 3, column: 1, scope: !5)
+    DBG_VALUE %stack.5, $noreg, !15, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 3, column: 1, scope: !5)
+
+    PseudoRET
+
+...