[RISCV][DebugInfo] Implement RISCVRegisterInfo::getOffsetOpcodes for RISCV

[luke957]

Summary

Implement RISCVRegisterInfo::getOffsetOpcodes for RISCV to avoid crashing when processing scalable vector debug info. In base class, TargetRegisterInfo::getOffsetOpcodes will not handle scalable offset(assert(!Offset.getScalable() && "Scalable offsets are not handled")). So first to remove the assert to avoid crashing.

[HsiangKai]

I have a patch to fix the problem. https://reviews.llvm.org/D107432

[luke957]

In D112829#3113118, @HsiangKai wrote:

I have a patch to fix the problem. https://reviews.llvm.org/D107432

Oh, thanks.

[luke957]

See https://reviews.llvm.org/D107432

llvm/lib/Target/RISCV/RISCVRegisterInfo.h

struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
   getPointerRegClass(const MachineFunction &MF,
                      unsigned Kind = 0) const override {
     return &RISCV::GPRRegClass;
   }
 
   const TargetRegisterClass *
   getLargestLegalSuperClass(const TargetRegisterClass *RC,
                             const MachineFunction &) const override;
+
+  void getOffsetOpcodes(const StackOffset &Offset,
+                        SmallVectorImpl<uint64_t> &Ops) const override;
 };
 }
 
 #endif

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

 #include "RISCVMachineFunctionInfo.h"
 #include "RISCVSubtarget.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
+#include "llvm/IR/DebugInfoMetadata.h"
 #include "llvm/Support/ErrorHandling.h"
 
 #define GET_REGINFO_TARGET_DESC
 #include "RISCVGenRegisterInfo.inc"
 
 using namespace llvm;
 
 static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");

 
 const TargetRegisterClass *
 RISCVRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
                                              const MachineFunction &) const {
   if (RC == &RISCV::VMV0RegClass)
     return &RISCV::VRRegClass;
   return RC;
 }
+
+void RISCVRegisterInfo::getOffsetOpcodes(const StackOffset &Offset,
+                                         SmallVectorImpl<uint64_t> &Ops) const {
+  // FIXME: Need to check Offset.getScalable()
+  DIExpression::appendOffset(Ops, Offset.getFixed());
+}

llvm/test/CodeGen/RISCV/rvv/rvv-debuginfo.ll

+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 \
+; RUN:     -verify-machineinstrs < %s | FileCheck %s
+
+; CHECK: .section .debug_info
+
+; Function Attrs: noinline nounwind optnone
+define dso_local <vscale x 8 x i16> @f1() #0 !dbg !9 {
+entry:
+  %ret = alloca <vscale x 8 x i16>, align 2
+  call void @llvm.dbg.declare(metadata <vscale x 8 x i16>* %ret, metadata !18, metadata !DIExpression()), !dbg !19
+  %0 = load <vscale x 8 x i16>, <vscale x 8 x i16>* %ret, align 2, !dbg !20
+  ret <vscale x 8 x i16> %0, !dbg !21
+}
+
+; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
+declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
+
+attributes #0 = { noinline nounwind optnone "frame-pointer"="all" "min-legal-vector-width"="128" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+a,+c,+d,+experimental-v,+experimental-zvlsseg,+f,+m,+relax,-save-restore" }
+attributes #1 = { nofree nosync nounwind readnone speculatable willreturn }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!2, !3, !4, !5, !6, !7}
+!llvm.ident = !{!8}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 14.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, splitDebugInlining: false, nameTableKind: None)
+!1 = !DIFile(filename: "test.c", directory: "llvm-project")
+!2 = !{i32 7, !"Dwarf Version", i32 4}
+!3 = !{i32 2, !"Debug Info Version", i32 3}
+!4 = !{i32 1, !"wchar_size", i32 4}
+!5 = !{i32 1, !"target-abi", !"lp64d"}
+!6 = !{i32 7, !"frame-pointer", i32 2}
+!7 = !{i32 1, !"SmallDataLimit", i32 8}
+!8 = !{!"clang version 14.0.0"}
+!9 = distinct !DISubprogram(name: "f1", scope: !1, file: !1, line: 6, type: !10, scopeLine: 6, spFlags: DISPFlagDefinition, unit: !0, retainedNodes: !17)
+!10 = !DISubroutineType(types: !11)
+!11 = !{!12}
+!12 = !DIDerivedType(tag: DW_TAG_typedef, name: "__rvv_int16m2_t", file: !1, baseType: !13)
+!13 = !DICompositeType(tag: DW_TAG_array_type, baseType: !14, flags: DIFlagVector, elements: !15)
+!14 = !DIBasicType(name: "short", size: 16, encoding: DW_ATE_signed)
+!15 = !{!16}
+!16 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_constu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul))
+!17 = !{}
+!18 = !DILocalVariable(name: "ret", scope: !9, file: !1, line: 7, type: !12)
+!19 = !DILocation(line: 7, column: 19, scope: !9)
+!20 = !DILocation(line: 8, column: 10, scope: !9)
+!21 = !DILocation(line: 8, column: 3, scope: !9)