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[RISCV] Emit DWARF location expression for RVV stack objects.
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Authored by HsiangKai on Aug 4 2021, 1:19 AM.

Details

Summary

VLENB is the length of a vector register in bytes. We use
<vscale x 64 bits> to represent one vector register. The dwarf offset is
VLENB * scalable_offset / 8.

For the mask vector, it occupies one vector register.

Diff Detail

Event Timeline

HsiangKai created this revision.Aug 4 2021, 1:19 AM
HsiangKai requested review of this revision.Aug 4 2021, 1:19 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 4 2021, 1:19 AM

Sorry, I'm a bit out of my depth with these DWARF offset opcodes. I think what you're doing here makes sense, though.

frasercrmck added inline comments.Mon, Nov 15, 9:57 AM
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
344

Is this path tested by this patch? I don't see any DW_OP_minus in the expected output. I may be missing something, though.

Add test cases for (frame base pointer - VLENB x n).

frasercrmck accepted this revision.Tue, Nov 23, 4:18 AM

LGTM. Anyone else?

This revision is now accepted and ready to land.Tue, Nov 23, 4:18 AM