[RISCV] "V" Extention coming with "F" "D" "Zfh" Extentions

[luke957]

Summary

If a target has StdExtF, it also has StdExtF, StdExtD and StdExtZfh?
When running command "./build/bin/opt -loop-vectorize -dce -instcombine -mtriple riscv64-linux-gnu -mattr=+experimental-v -debug-only=loop-vectorize -S llvm/test/Transforms/LoopVectorize/RISCV/basic-vec.ll", an "UNREACHABLE executed" error was received.
Missing "+f" in "-mattr" is the reason of "UNREACHABLE executed" error.

[Jim]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

139

It is incorrect. Only Zfh imply F enabled and D imply F enabled.

[HsiangKai]

There is no such implication in the V specification. See https://github.com/riscv/riscv-v-spec/issues/608.

[luke957]

In D99492#2655701, @HsiangKai wrote:

There is no such implication in the V specification. See https://github.com/riscv/riscv-v-spec/issues/608.

Get it. Thanks.

[luke957]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

139

Yeah, I should find another way to solve the crash problem.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

     for (MVT VT : IntVecVTs)
       addRegClassForRVV(VT);
 
-    if (Subtarget.hasStdExtZfh())
-      for (MVT VT : F16VecVTs)
-        addRegClassForRVV(VT);
+    for (MVT VT : F16VecVTs)
+      addRegClassForRVV(VT);
 
-    if (Subtarget.hasStdExtF())
-      for (MVT VT : F32VecVTs)
-        addRegClassForRVV(VT);
+    for (MVT VT : F32VecVTs)
+      addRegClassForRVV(VT);
 
-    if (Subtarget.hasStdExtD())
-      for (MVT VT : F64VecVTs)
-        addRegClassForRVV(VT);
+    for (MVT VT : F64VecVTs)
+      addRegClassForRVV(VT);
 
     if (Subtarget.useRVVForFixedLengthVectors()) {
       auto addRegClassForFixedVectors = [this](MVT VT) {

llvm/test/Transforms/LoopVectorize/RISCV/basic-vec.ll

+; RUN: opt -loop-vectorize -dce -instcombine -mtriple riscv64-linux-gnu -mattr=+experimental-v < %s -S 2>%t | FileCheck %s
+
+; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
+
+; WARN-NOT: warning
+
+define void @cmpsel_i32(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i64 %n) {
+; CHECK-LABEL: @cmpsel_i32(
+; CHECK-NEXT:  entry:
+; CHECK:       vector.body:
+; CHECK:         [[WIDE_LOAD:%.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* {{.*}}, align 4
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq <vscale x 4 x i32> [[WIDE_LOAD]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 0, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
+; CHECK-NEXT:    [[TMP2:%.*]] = select <vscale x 4 x i1> [[TMP1]], <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 2, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer), <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 10, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
+; CHECK:         store <vscale x 4 x i32> [[TMP2]], <vscale x 4 x i32>* {{.*}}, align 4
+;
+entry:
+  %cmp7 = icmp sgt i64 %n, 0
+  br i1 %cmp7, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %arrayidx = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
+  %0 = load i32, i32* %arrayidx, align 4
+  %tobool.not = icmp eq i32 %0, 0
+  %cond = select i1 %tobool.not, i32 2, i32 10
+  %arrayidx2 = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
+  store i32 %cond, i32* %arrayidx2, align 4
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %exitcond.not = icmp eq i64 %indvars.iv.next, %n
+  br i1 %exitcond.not, label %for.end.loopexit, label %for.body, !llvm.loop !0
+
+for.end.loopexit:                                 ; preds = %for.body
+  br label %for.end
+
+for.end:                                          ; preds = %for.end.loopexit, %entry
+  ret void
+}
+
+define void @cmpsel_f32(float* noalias nocapture %a, float* noalias nocapture readonly %b, i64 %n) {
+; CHECK-LABEL: @cmpsel_f32(
+; CHECK-NEXT:  entry:
+; CHECK:       vector.body:
+; CHECK:         [[WIDE_LOAD:%.*]] = load <vscale x 4 x float>, <vscale x 4 x float>* {{.*}}, align 4
+; CHECK-NEXT:    [[TMP1:%.*]] = fcmp ogt <vscale x 4 x float> [[WIDE_LOAD]], shufflevector (<vscale x 4 x float> insertelement (<vscale x 4 x float> poison, float 3.000000e+00, i32 0), <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer)
+; CHECK-NEXT:    [[TMP2:%.*]] = select <vscale x 4 x i1> [[TMP1]], <vscale x 4 x float> shufflevector (<vscale x 4 x float> insertelement (<vscale x 4 x float> poison, float 1.000000e+01, i32 0), <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer), <vscale x 4 x float> shufflevector (<vscale x 4 x float> insertelement (<vscale x 4 x float> poison, float 2.000000e+00, i32 0), <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer)
+; CHECK:         store <vscale x 4 x float> [[TMP2]], <vscale x 4 x float>* {{.*}}, align 4
+
+entry:
+  %cmp8 = icmp sgt i64 %n, 0
+  br i1 %cmp8, label %for.body, label %for.end
+
+for.body:                                         ; preds = %entry, %for.body
+  %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
+  %arrayidx = getelementptr inbounds float, float* %b, i64 %indvars.iv
+  %0 = load float, float* %arrayidx, align 4
+  %cmp1 = fcmp ogt float %0, 3.000000e+00
+  %conv = select i1 %cmp1, float 1.000000e+01, float 2.000000e+00
+  %arrayidx3 = getelementptr inbounds float, float* %a, i64 %indvars.iv
+  store float %conv, float* %arrayidx3, align 4
+  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
+  %exitcond.not = icmp eq i64 %indvars.iv.next, %n
+  br i1 %exitcond.not, label %for.end, label %for.body, !llvm.loop !6
+
+for.end:                                          ; preds = %for.body, %entry
+  ret void
+}
+
+!0 = distinct !{!0, !1, !2, !3, !4, !5}
+!1 = !{!"llvm.loop.mustprogress"}
+!2 = !{!"llvm.loop.vectorize.width", i32 4}
+!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
+!4 = !{!"llvm.loop.interleave.count", i32 1}
+!5 = !{!"llvm.loop.vectorize.enable", i1 true}
+!6 = distinct !{!6, !1, !2, !3, !4, !5}