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Differential D98938

[RISCV] Maintain fixed-length info when optimizing BUILD_VECTORs
ClosedPublic

Authored by frasercrmck on Mar 19 2021, 3:26 AM.

Details

Reviewers
craig.topper
rogfer01
evandro
HsiangKai
khchen
arcbbb
Commits
rGd399b82e2ab2: [RISCV] Maintain fixed-length info when optimizing BUILD_VECTORs
Summary

I'm not sure how I failed to notice this before, but when optimizing
dominant-element BUILD_VECTORs we would lower via the scalable container type,
which lost us the information about the fixed length of the vector types. By
lowering via the fixed-length type we can preserve that information and
eliminate redundant vsetvli instructions.

Diff Detail

Event Timeline

frasercrmck created this revision.Mar 19 2021, 3:26 AM
Herald added subscribers: vkmr, luismarques, apazos and 22 others. · View Herald TranscriptMar 19 2021, 3:26 AM
frasercrmck requested review of this revision.Mar 19 2021, 3:26 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 19 2021, 3:26 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B94657: Diff 331815.Mar 19 2021, 4:05 AM
frasercrmck added a parent revision: D98776: [RISCV] Fix missing scalable->fixed-length vector conversion.Mar 19 2021, 5:46 AM
frasercrmck updated this revision to Diff 331841.Mar 19 2021, 5:46 AM
frasercrmck updated this revision to Diff 331843.Mar 19 2021, 5:55 AM
frasercrmck edited parent revisions, added: D98944: [RISCV] Add missing CHECKs to vector test; removed: D98776: [RISCV] Fix missing scalable->fixed-length vector conversion.Mar 19 2021, 5:55 AM
Harbormaster completed remote builds in B94679: Diff 331841.Mar 19 2021, 6:51 AM
Harbormaster completed remote builds in B94681: Diff 331843.Mar 19 2021, 6:54 AM
craig.topper accepted this revision.Mar 19 2021, 9:08 AM

LGTM

This revision is now accepted and ready to land.Mar 19 2021, 9:08 AM
Closed by commit rGd399b82e2ab2: [RISCV] Maintain fixed-length info when optimizing BUILD_VECTORs (authored by frasercrmck). · Explain WhyMar 19 2021, 10:27 AM
This revision was automatically updated to reflect the committed changes.
frasercrmck added a commit: rGd399b82e2ab2: [RISCV] Maintain fixed-length info when optimizing BUILD_VECTORs.

Revision Contents

Diff 331843

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,189 Lines • ▼ Show 20 Lines for (SDValue V : Op->op_values()) {
// Is this value dominant? // Is this value dominant?
if (++Count > DominantValueCountThreshold) if (++Count > DominantValueCountThreshold)
DominantValue = V; DominantValue = V;
} }
// Don't perform this optimization when optimizing for size, since // Don't perform this optimization when optimizing for size, since
// materializing elements and inserting them tends to cause code bloat. // materializing elements and inserting them tends to cause code bloat.
if (DominantValue && !DAG.shouldOptForSize()) { if (DominantValue && !DAG.shouldOptForSize()) {
unsigned Opc = SDValue Vec = DAG.getSplatBuildVector(VT, DL, DominantValue);
VT.isFloatingPoint() ? RISCVISD::VFMV_V_F_VL : RISCVISD::VMV_V_X_VL;
SDValue Vec = DAG.getNode(Opc, DL, ContainerVT, DominantValue, VL);
if (ValueCounts.size() != 1) { if (ValueCounts.size() != 1) {
MVT XLenVT = Subtarget.getXLenVT(); MVT XLenVT = Subtarget.getXLenVT();
for (unsigned I = 0; I < NumElts; ++I) { for (unsigned I = 0; I < NumElts; ++I) {
if (!Op.getOperand(I).isUndef() && Op.getOperand(I) != DominantValue) if (!Op.getOperand(I).isUndef() && Op.getOperand(I) != DominantValue)
Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ContainerVT, Vec, Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Vec,
Op.getOperand(I), DAG.getConstant(I, DL, XLenVT)); Op.getOperand(I), DAG.getConstant(I, DL, XLenVT));
} }
} }
return convertFromScalableVector(VT, Vec, DAG, Subtarget); return Vec;
} }
return SDValue(); return SDValue();
} }
static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG, static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) { const RISCVSubtarget &Subtarget) {
SDValue V1 = Op.getOperand(0); SDValue V1 = Op.getOperand(0);
▲ Show 20 Lines • Show All 6,029 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll

Show First 20 Lines • Show All 664 Lines • ▼ Show 20 Lines
; LMULMAX2-RV64-NEXT: slli a5, a2, 40 ; LMULMAX2-RV64-NEXT: slli a5, a2, 40
; LMULMAX2-RV64-NEXT: and a3, a5, a3 ; LMULMAX2-RV64-NEXT: and a3, a5, a3
; LMULMAX2-RV64-NEXT: slli a2, a2, 56 ; LMULMAX2-RV64-NEXT: slli a2, a2, 56
; LMULMAX2-RV64-NEXT: or a2, a2, a3 ; LMULMAX2-RV64-NEXT: or a2, a2, a3
; LMULMAX2-RV64-NEXT: or a2, a2, a4 ; LMULMAX2-RV64-NEXT: or a2, a2, a4
; LMULMAX2-RV64-NEXT: or a1, a2, a1 ; LMULMAX2-RV64-NEXT: or a1, a2, a1
; LMULMAX2-RV64-NEXT: vsetivli a2, 2, e64,m1,ta,mu ; LMULMAX2-RV64-NEXT: vsetivli a2, 2, e64,m1,ta,mu
; LMULMAX2-RV64-NEXT: vmv.v.x v25, a1 ; LMULMAX2-RV64-NEXT: vmv.v.x v25, a1
; LMULMAX2-RV64-NEXT: vsetvli a1, zero, e64,m1,ta,mu
; LMULMAX2-RV64-NEXT: vmv.s.x v25, t1 ; LMULMAX2-RV64-NEXT: vmv.s.x v25, t1
; LMULMAX2-RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; LMULMAX2-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX2-RV64-NEXT: vse64.v v25, (a0)
; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: bswap_v2i64: ; LMULMAX1-RV32-LABEL: bswap_v2i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi sp, sp, -16 ; LMULMAX1-RV32-NEXT: addi sp, sp, -16
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 16 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 16
; LMULMAX1-RV32-NEXT: vsetivli a1, 2, e64,m1,ta,mu ; LMULMAX1-RV32-NEXT: vsetivli a1, 2, e64,m1,ta,mu
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; LMULMAX1-RV64-NEXT: slli a5, a2, 40 ; LMULMAX1-RV64-NEXT: slli a5, a2, 40
; LMULMAX1-RV64-NEXT: and a3, a5, a3 ; LMULMAX1-RV64-NEXT: and a3, a5, a3
; LMULMAX1-RV64-NEXT: slli a2, a2, 56 ; LMULMAX1-RV64-NEXT: slli a2, a2, 56
; LMULMAX1-RV64-NEXT: or a2, a2, a3 ; LMULMAX1-RV64-NEXT: or a2, a2, a3
; LMULMAX1-RV64-NEXT: or a2, a2, a4 ; LMULMAX1-RV64-NEXT: or a2, a2, a4
; LMULMAX1-RV64-NEXT: or a1, a2, a1 ; LMULMAX1-RV64-NEXT: or a1, a2, a1
; LMULMAX1-RV64-NEXT: vsetivli a2, 2, e64,m1,ta,mu ; LMULMAX1-RV64-NEXT: vsetivli a2, 2, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmv.v.x v25, a1 ; LMULMAX1-RV64-NEXT: vmv.v.x v25, a1
; LMULMAX1-RV64-NEXT: vsetvli a1, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v25, t1 ; LMULMAX1-RV64-NEXT: vmv.s.x v25, t1
; LMULMAX1-RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x %a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y %b = load <2 x i64>, <2 x i64>* %y
%c = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %a) %c = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %a)
store <2 x i64> %c, <2 x i64>* %x store <2 x i64> %c, <2 x i64>* %x
ret void ret void
} }
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; LMULMAX1-RV64-NEXT: slli a5, a2, 40 ; LMULMAX1-RV64-NEXT: slli a5, a2, 40
; LMULMAX1-RV64-NEXT: and a5, a5, a4 ; LMULMAX1-RV64-NEXT: and a5, a5, a4
; LMULMAX1-RV64-NEXT: slli a2, a2, 56 ; LMULMAX1-RV64-NEXT: slli a2, a2, 56
; LMULMAX1-RV64-NEXT: or a2, a2, a5 ; LMULMAX1-RV64-NEXT: or a2, a2, a5
; LMULMAX1-RV64-NEXT: or a2, a2, a3 ; LMULMAX1-RV64-NEXT: or a2, a2, a3
; LMULMAX1-RV64-NEXT: or a1, a2, a1 ; LMULMAX1-RV64-NEXT: or a1, a2, a1
; LMULMAX1-RV64-NEXT: vsetivli a2, 2, e64,m1,ta,mu ; LMULMAX1-RV64-NEXT: vsetivli a2, 2, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmv.v.x v26, a1 ; LMULMAX1-RV64-NEXT: vmv.v.x v26, a1
; LMULMAX1-RV64-NEXT: vsetvli a1, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v26, t4 ; LMULMAX1-RV64-NEXT: vmv.s.x v26, t4
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25 ; LMULMAX1-RV64-NEXT: vmv.x.s a1, v25
; LMULMAX1-RV64-NEXT: srli a2, a1, 40 ; LMULMAX1-RV64-NEXT: srli a2, a1, 40
; LMULMAX1-RV64-NEXT: and a2, a2, t0 ; LMULMAX1-RV64-NEXT: and a2, a2, t0
; LMULMAX1-RV64-NEXT: srli a3, a1, 56 ; LMULMAX1-RV64-NEXT: srli a3, a1, 56
; LMULMAX1-RV64-NEXT: or a2, a2, a3 ; LMULMAX1-RV64-NEXT: or a2, a2, a3
; LMULMAX1-RV64-NEXT: srli a3, a1, 24 ; LMULMAX1-RV64-NEXT: srli a3, a1, 24
; LMULMAX1-RV64-NEXT: and a3, a3, a7 ; LMULMAX1-RV64-NEXT: and a3, a3, a7
Show All 33 Lines
; LMULMAX1-RV64-NEXT: slli a5, a2, 40 ; LMULMAX1-RV64-NEXT: slli a5, a2, 40
; LMULMAX1-RV64-NEXT: and a4, a5, a4 ; LMULMAX1-RV64-NEXT: and a4, a5, a4
; LMULMAX1-RV64-NEXT: slli a2, a2, 56 ; LMULMAX1-RV64-NEXT: slli a2, a2, 56
; LMULMAX1-RV64-NEXT: or a2, a2, a4 ; LMULMAX1-RV64-NEXT: or a2, a2, a4
; LMULMAX1-RV64-NEXT: or a2, a2, a3 ; LMULMAX1-RV64-NEXT: or a2, a2, a3
; LMULMAX1-RV64-NEXT: or a1, a2, a1 ; LMULMAX1-RV64-NEXT: or a1, a2, a1
; LMULMAX1-RV64-NEXT: vsetivli a2, 2, e64,m1,ta,mu ; LMULMAX1-RV64-NEXT: vsetivli a2, 2, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmv.v.x v25, a1 ; LMULMAX1-RV64-NEXT: vmv.v.x v25, a1
; LMULMAX1-RV64-NEXT: vsetvli a1, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v25, t4 ; LMULMAX1-RV64-NEXT: vmv.s.x v25, t4
; LMULMAX1-RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v26, (a6) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a6)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x %a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y %b = load <4 x i64>, <4 x i64>* %y
%c = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a) %c = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a)
store <4 x i64> %c, <4 x i64>* %x store <4 x i64> %c, <4 x i64>* %x
ret void ret void
} }
declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>) declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll

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Show First 20 Lines • Show All 3,872 Lines • ▼ Show 20 Lines
; LMULMAX2-RV64-NEXT: srli a1, a1, 2 ; LMULMAX2-RV64-NEXT: srli a1, a1, 2
; LMULMAX2-RV64-NEXT: and a1, a1, a2 ; LMULMAX2-RV64-NEXT: and a1, a1, a2
; LMULMAX2-RV64-NEXT: add a1, a3, a1 ; LMULMAX2-RV64-NEXT: add a1, a3, a1
; LMULMAX2-RV64-NEXT: srli a2, a1, 4 ; LMULMAX2-RV64-NEXT: srli a2, a1, 4
; LMULMAX2-RV64-NEXT: add a1, a1, a2 ; LMULMAX2-RV64-NEXT: add a1, a1, a2
; LMULMAX2-RV64-NEXT: and a1, a1, a4 ; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: vsetvli a2, zero, e64,m1,ta,mu
; LMULMAX2-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX2-RV64-NEXT: vmv.s.x v26, a1
; LMULMAX2-RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX2-RV64-NEXT: vse64.v v26, (a0)
; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: ctlz_v2i64: ; LMULMAX1-RV32-LABEL: ctlz_v2i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi sp, sp, -16 ; LMULMAX1-RV32-NEXT: addi sp, sp, -16
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 16 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 16
; LMULMAX1-RV32-NEXT: vsetivli a1, 2, e64,m1,ta,mu ; LMULMAX1-RV32-NEXT: vsetivli a1, 2, e64,m1,ta,mu
▲ Show 20 Lines • Show All 216 Lines • ▼ Show 20 Lines
; LMULMAX1-RV64-NEXT: srli a1, a1, 2 ; LMULMAX1-RV64-NEXT: srli a1, a1, 2
; LMULMAX1-RV64-NEXT: and a1, a1, a2 ; LMULMAX1-RV64-NEXT: and a1, a1, a2
; LMULMAX1-RV64-NEXT: add a1, a3, a1 ; LMULMAX1-RV64-NEXT: add a1, a3, a1
; LMULMAX1-RV64-NEXT: srli a2, a1, 4 ; LMULMAX1-RV64-NEXT: srli a2, a1, 4
; LMULMAX1-RV64-NEXT: add a1, a1, a2 ; LMULMAX1-RV64-NEXT: add a1, a1, a2
; LMULMAX1-RV64-NEXT: and a1, a1, a4 ; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetvli a2, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1
; LMULMAX1-RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a0)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x %a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y %b = load <2 x i64>, <2 x i64>* %y
%c = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 false) %c = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 false)
store <2 x i64> %c, <2 x i64>* %x store <2 x i64> %c, <2 x i64>* %x
ret void ret void
} }
▲ Show 20 Lines • Show All 7,750 Lines • ▼ Show 20 Lines
; LMULMAX1-RV64-NEXT: srli a1, a1, 2 ; LMULMAX1-RV64-NEXT: srli a1, a1, 2
; LMULMAX1-RV64-NEXT: and a1, a1, a3 ; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: add a1, a2, a1 ; LMULMAX1-RV64-NEXT: add a1, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a1, 4 ; LMULMAX1-RV64-NEXT: srli a2, a1, 4
; LMULMAX1-RV64-NEXT: add a1, a1, a2 ; LMULMAX1-RV64-NEXT: add a1, a1, a2
; LMULMAX1-RV64-NEXT: and a1, a1, a4 ; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetvli a2, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1
; LMULMAX1-RV64-NEXT: vsetivli a1, 1, e64,m1,ta,mu ; LMULMAX1-RV64-NEXT: vsetivli a1, 1, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v25, 1 ; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v25, 1
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 ; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2 ; LMULMAX1-RV64-NEXT: or a1, a1, a2
; LMULMAX1-RV64-NEXT: srli a2, a1, 2 ; LMULMAX1-RV64-NEXT: srli a2, a1, 2
; LMULMAX1-RV64-NEXT: or a1, a1, a2 ; LMULMAX1-RV64-NEXT: or a1, a1, a2
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; LMULMAX1-RV64-NEXT: srli a1, a1, 2 ; LMULMAX1-RV64-NEXT: srli a1, a1, 2
; LMULMAX1-RV64-NEXT: and a1, a1, a3 ; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: add a1, a2, a1 ; LMULMAX1-RV64-NEXT: add a1, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a1, 4 ; LMULMAX1-RV64-NEXT: srli a2, a1, 4
; LMULMAX1-RV64-NEXT: add a1, a1, a2 ; LMULMAX1-RV64-NEXT: add a1, a1, a2
; LMULMAX1-RV64-NEXT: and a1, a1, a4 ; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetvli a2, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v27, a1 ; LMULMAX1-RV64-NEXT: vmv.s.x v27, a1
; LMULMAX1-RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vse64.v v27, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v27, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v26, (a6) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a6)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x %a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y %b = load <4 x i64>, <4 x i64>* %y
%c = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> %a, i1 false) %c = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> %a, i1 false)
store <4 x i64> %c, <4 x i64>* %x store <4 x i64> %c, <4 x i64>* %x
ret void ret void
} }
declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1) declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,700 Lines • ▼ Show 20 Lines
; LMULMAX2-RV64-NEXT: srli a1, a1, 2 ; LMULMAX2-RV64-NEXT: srli a1, a1, 2
; LMULMAX2-RV64-NEXT: and a1, a1, a2 ; LMULMAX2-RV64-NEXT: and a1, a1, a2
; LMULMAX2-RV64-NEXT: add a1, a3, a1 ; LMULMAX2-RV64-NEXT: add a1, a3, a1
; LMULMAX2-RV64-NEXT: srli a2, a1, 4 ; LMULMAX2-RV64-NEXT: srli a2, a1, 4
; LMULMAX2-RV64-NEXT: add a1, a1, a2 ; LMULMAX2-RV64-NEXT: add a1, a1, a2
; LMULMAX2-RV64-NEXT: and a1, a1, a4 ; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: vsetvli a2, zero, e64,m1,ta,mu
; LMULMAX2-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX2-RV64-NEXT: vmv.s.x v26, a1
; LMULMAX2-RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX2-RV64-NEXT: vse64.v v26, (a0)
; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: cttz_v2i64: ; LMULMAX1-RV32-LABEL: cttz_v2i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi sp, sp, -16 ; LMULMAX1-RV32-NEXT: addi sp, sp, -16
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 16 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 16
; LMULMAX1-RV32-NEXT: vsetivli a1, 2, e64,m1,ta,mu ; LMULMAX1-RV32-NEXT: vsetivli a1, 2, e64,m1,ta,mu
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Lines
; LMULMAX1-RV64-NEXT: srli a1, a1, 2 ; LMULMAX1-RV64-NEXT: srli a1, a1, 2
; LMULMAX1-RV64-NEXT: and a1, a1, a2 ; LMULMAX1-RV64-NEXT: and a1, a1, a2
; LMULMAX1-RV64-NEXT: add a1, a3, a1 ; LMULMAX1-RV64-NEXT: add a1, a3, a1
; LMULMAX1-RV64-NEXT: srli a2, a1, 4 ; LMULMAX1-RV64-NEXT: srli a2, a1, 4
; LMULMAX1-RV64-NEXT: add a1, a1, a2 ; LMULMAX1-RV64-NEXT: add a1, a1, a2
; LMULMAX1-RV64-NEXT: and a1, a1, a4 ; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetvli a2, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1
; LMULMAX1-RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a0)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x %a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y %b = load <2 x i64>, <2 x i64>* %y
%c = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 false) %c = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 false)
store <2 x i64> %c, <2 x i64>* %x store <2 x i64> %c, <2 x i64>* %x
ret void ret void
} }
▲ Show 20 Lines • Show All 5,322 Lines • ▼ Show 20 Lines
; LMULMAX1-RV64-NEXT: srli a2, a2, 2 ; LMULMAX1-RV64-NEXT: srli a2, a2, 2
; LMULMAX1-RV64-NEXT: and a2, a2, a3 ; LMULMAX1-RV64-NEXT: and a2, a2, a3
; LMULMAX1-RV64-NEXT: add a2, a4, a2 ; LMULMAX1-RV64-NEXT: add a2, a4, a2
; LMULMAX1-RV64-NEXT: srli a4, a2, 4 ; LMULMAX1-RV64-NEXT: srli a4, a2, 4
; LMULMAX1-RV64-NEXT: add a2, a2, a4 ; LMULMAX1-RV64-NEXT: add a2, a2, a4
; LMULMAX1-RV64-NEXT: and a2, a2, a5 ; LMULMAX1-RV64-NEXT: and a2, a2, a5
; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: vsetvli a4, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v27, a2 ; LMULMAX1-RV64-NEXT: vmv.s.x v27, a2
; LMULMAX1-RV64-NEXT: vsetivli a2, 1, e64,m1,ta,mu ; LMULMAX1-RV64-NEXT: vsetivli a2, 1, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1 ; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1
; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 ; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
; LMULMAX1-RV64-NEXT: addi a4, a2, -1 ; LMULMAX1-RV64-NEXT: addi a4, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2 ; LMULMAX1-RV64-NEXT: not a2, a2
; LMULMAX1-RV64-NEXT: and a2, a2, a4 ; LMULMAX1-RV64-NEXT: and a2, a2, a4
; LMULMAX1-RV64-NEXT: srli a4, a2, 1 ; LMULMAX1-RV64-NEXT: srli a4, a2, 1
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; LMULMAX1-RV64-NEXT: srli a2, a2, 2 ; LMULMAX1-RV64-NEXT: srli a2, a2, 2
; LMULMAX1-RV64-NEXT: and a2, a2, a3 ; LMULMAX1-RV64-NEXT: and a2, a2, a3
; LMULMAX1-RV64-NEXT: add a2, a4, a2 ; LMULMAX1-RV64-NEXT: add a2, a4, a2
; LMULMAX1-RV64-NEXT: srli a3, a2, 4 ; LMULMAX1-RV64-NEXT: srli a3, a2, 4
; LMULMAX1-RV64-NEXT: add a2, a2, a3 ; LMULMAX1-RV64-NEXT: add a2, a2, a3
; LMULMAX1-RV64-NEXT: and a2, a2, a5 ; LMULMAX1-RV64-NEXT: and a2, a2, a5
; LMULMAX1-RV64-NEXT: mul a1, a2, a1 ; LMULMAX1-RV64-NEXT: mul a1, a2, a1
; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetvli a2, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1
; LMULMAX1-RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v27, (a6) ; LMULMAX1-RV64-NEXT: vse64.v v27, (a6)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x %a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y %b = load <4 x i64>, <4 x i64>* %y
%c = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> %a, i1 false) %c = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> %a, i1 false)
store <4 x i64> %c, <4 x i64>* %x store <4 x i64> %c, <4 x i64>* %x
ret void ret void
} }
declare <4 x i64> @llvm.cttz.v4i64(<4 x i64>, i1) declare <4 x i64> @llvm.cttz.v4i64(<4 x i64>, i1)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

Show All 17 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <4 x float> <float 0.0, float 4.0, float 0.0, float 2.0>, <4 x float>* %x store <4 x float> <float 0.0, float 4.0, float 0.0, float 2.0>, <4 x float>* %x
ret void ret void
} }
define void @buildvec_dominant0_v4f32(<4 x float>* %x) { define void @buildvec_dominant0_v4f32(<4 x float>* %x) {
; CHECK-LABEL: buildvec_dominant0_v4f32: ; CHECK-LABEL: buildvec_dominant0_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: fmv.w.x ft0, zero
; CHECK-NEXT: lui a1, %hi(.LCPI1_0) ; CHECK-NEXT: lui a1, %hi(.LCPI1_0)
; CHECK-NEXT: flw ft1, %lo(.LCPI1_0)(a1) ; CHECK-NEXT: flw ft0, %lo(.LCPI1_0)(a1)
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu ; CHECK-NEXT: fmv.w.x ft1, zero
; CHECK-NEXT: vfmv.s.f v25, ft0
; CHECK-NEXT: vsetivli a1, 4, e32,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 4, e32,m1,ta,mu
; CHECK-NEXT: vfmv.v.f v26, ft1 ; CHECK-NEXT: vfmv.s.f v25, ft1
; CHECK-NEXT: vfmv.v.f v26, ft0
; CHECK-NEXT: vsetivli a1, 3, e32,m1,tu,mu ; CHECK-NEXT: vsetivli a1, 3, e32,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 2 ; CHECK-NEXT: vslideup.vi v26, v25, 2
; CHECK-NEXT: vsetivli a1, 4, e32,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 4, e32,m1,ta,mu
; CHECK-NEXT: vse32.v v26, (a0) ; CHECK-NEXT: vse32.v v26, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <4 x float> <float 2.0, float 2.0, float 0.0, float 2.0>, <4 x float>* %x store <4 x float> <float 2.0, float 2.0, float 0.0, float 2.0>, <4 x float>* %x
ret void ret void
} }
define void @buildvec_dominant1_v4f32(<4 x float>* %x, float %f) { define void @buildvec_dominant1_v4f32(<4 x float>* %x, float %f) {
; CHECK-LABEL: buildvec_dominant1_v4f32: ; CHECK-LABEL: buildvec_dominant1_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: fmv.w.x ft0, zero ; CHECK-NEXT: fmv.w.x ft0, zero
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu
; CHECK-NEXT: vfmv.s.f v25, ft0
; CHECK-NEXT: vsetivli a1, 4, e32,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 4, e32,m1,ta,mu
; CHECK-NEXT: vfmv.s.f v25, ft0
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vsetivli a1, 2, e32,m1,tu,mu ; CHECK-NEXT: vsetivli a1, 2, e32,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 1 ; CHECK-NEXT: vslideup.vi v26, v25, 1
; CHECK-NEXT: vsetivli a1, 4, e32,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 4, e32,m1,ta,mu
; CHECK-NEXT: vse32.v v26, (a0) ; CHECK-NEXT: vse32.v v26, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = insertelement <4 x float> undef, float %f, i32 0 %v0 = insertelement <4 x float> undef, float %f, i32 0
%v1 = insertelement <4 x float> %v0, float 0.0, i32 1 %v1 = insertelement <4 x float> %v0, float 0.0, i32 1
%v2 = insertelement <4 x float> %v1, float %f, i32 2 %v2 = insertelement <4 x float> %v1, float %f, i32 2
%v3 = insertelement <4 x float> %v2, float %f, i32 3 %v3 = insertelement <4 x float> %v2, float %f, i32 3
store <4 x float> %v3, <4 x float>* %x store <4 x float> %v3, <4 x float>* %x
ret void ret void
} }
define void @buildvec_dominant2_v4f32(<4 x float>* %x, float %f) { define void @buildvec_dominant2_v4f32(<4 x float>* %x, float %f) {
; CHECK-LABEL: buildvec_dominant2_v4f32: ; CHECK-LABEL: buildvec_dominant2_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI3_0) ; CHECK-NEXT: lui a1, %hi(.LCPI3_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI3_0)(a1) ; CHECK-NEXT: flw ft0, %lo(.LCPI3_0)(a1)
; CHECK-NEXT: vsetivli a1, 4, e32,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 4, e32,m1,ta,mu
; CHECK-NEXT: vfmv.v.f v25, fa0 ; CHECK-NEXT: vfmv.s.f v25, ft0
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu ; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vfmv.s.f v26, ft0
; CHECK-NEXT: vsetivli a1, 2, e32,m1,tu,mu ; CHECK-NEXT: vsetivli a1, 2, e32,m1,tu,mu
; CHECK-NEXT: vslideup.vi v25, v26, 1 ; CHECK-NEXT: vslideup.vi v26, v25, 1
; CHECK-NEXT: vsetivli a1, 4, e32,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 4, e32,m1,ta,mu
; CHECK-NEXT: vse32.v v25, (a0) ; CHECK-NEXT: vse32.v v26, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v0 = insertelement <4 x float> undef, float %f, i32 0 %v0 = insertelement <4 x float> undef, float %f, i32 0
%v1 = insertelement <4 x float> %v0, float 2.0, i32 1 %v1 = insertelement <4 x float> %v0, float 2.0, i32 1
%v2 = insertelement <4 x float> %v1, float %f, i32 2 %v2 = insertelement <4 x float> %v1, float %f, i32 2
%v3 = insertelement <4 x float> %v2, float %f, i32 3 %v3 = insertelement <4 x float> %v2, float %f, i32 3
store <4 x float> %v3, <4 x float>* %x store <4 x float> %v3, <4 x float>* %x
ret void ret void
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetivli a3, 8, e32,m2,ta,mu ; RV32-NEXT: vsetivli a3, 8, e32,m2,ta,mu
; RV32-NEXT: vmv.v.i v28, 0 ; RV32-NEXT: vmv.v.i v28, 0
; RV32-NEXT: vsetivli a3, 2, e64,m2,tu,mu ; RV32-NEXT: vsetivli a3, 2, e64,m2,tu,mu
; RV32-NEXT: vslideup.vi v28, v26, 0 ; RV32-NEXT: vslideup.vi v28, v26, 0
; RV32-NEXT: lw a3, 20(a0) ; RV32-NEXT: lw a3, 20(a0)
; RV32-NEXT: vsetivli a4, 4, e32,m1,ta,mu ; RV32-NEXT: vsetivli a4, 4, e32,m1,ta,mu
; RV32-NEXT: lw a4, 16(a0) ; RV32-NEXT: lw a4, 16(a0)
; RV32-NEXT: vmv.v.x v26, a3 ; RV32-NEXT: vmv.v.x v26, a3
; RV32-NEXT: vsetvli a3, zero, e32,m1,ta,mu
; RV32-NEXT: vmv.s.x v26, a4 ; RV32-NEXT: vmv.s.x v26, a4
; RV32-NEXT: vsetivli a3, 4, e64,m2,tu,mu ; RV32-NEXT: vsetivli a3, 4, e64,m2,tu,mu
; RV32-NEXT: vslideup.vi v28, v26, 2 ; RV32-NEXT: vslideup.vi v28, v26, 2
; RV32-NEXT: vsetivli a3, 2, e32,m2,ta,mu ; RV32-NEXT: vsetivli a3, 2, e32,m2,ta,mu
; RV32-NEXT: vmv.v.i v26, 0 ; RV32-NEXT: vmv.v.i v26, 0
; RV32-NEXT: vslide1up.vx v30, v26, a2 ; RV32-NEXT: vslide1up.vx v30, v26, a2
; RV32-NEXT: vslide1up.vx v26, v30, a1 ; RV32-NEXT: vslide1up.vx v26, v30, a1
; RV32-NEXT: vsetivli a3, 3, e64,m2,tu,mu ; RV32-NEXT: vsetivli a3, 3, e64,m2,tu,mu
▲ Show 20 Lines • Show All 254 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <16 x i8> <i8 0, i8 3, i8 6, i8 9, i8 12, i8 15, i8 18, i8 21, i8 24, i8 27, i8 30, i8 33, i8 36, i8 39, i8 42, i8 45>, <16 x i8>* %x store <16 x i8> <i8 0, i8 3, i8 6, i8 9, i8 12, i8 15, i8 18, i8 21, i8 24, i8 27, i8 30, i8 33, i8 36, i8 39, i8 42, i8 45>, <16 x i8>* %x
ret void ret void
} }
define void @buildvec_dominant0_v8i16(<8 x i16>* %x) { define void @buildvec_dominant0_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: buildvec_dominant0_v8i16: ; CHECK-LABEL: buildvec_dominant0_v8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu
; CHECK-NEXT: vmv.s.x v25, zero
; CHECK-NEXT: vsetivli a1, 8, e16,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 8, e16,m1,ta,mu
; CHECK-NEXT: vmv.s.x v25, zero
; CHECK-NEXT: vmv.v.i v26, 8 ; CHECK-NEXT: vmv.v.i v26, 8
; CHECK-NEXT: vsetivli a1, 4, e16,m1,tu,mu ; CHECK-NEXT: vsetivli a1, 4, e16,m1,tu,mu
; CHECK-NEXT: vslideup.vi v26, v25, 3 ; CHECK-NEXT: vslideup.vi v26, v25, 3
; CHECK-NEXT: vsetivli a1, 8, e16,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 8, e16,m1,ta,mu
; CHECK-NEXT: vse16.v v26, (a0) ; CHECK-NEXT: vse16.v v26, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <8 x i16> <i16 8, i16 8, i16 undef, i16 0, i16 8, i16 undef, i16 8, i16 8>, <8 x i16>* %x store <8 x i16> <i16 8, i16 8, i16 undef, i16 0, i16 8, i16 undef, i16 8, i16 8>, <8 x i16>* %x
ret void ret void
Show All 29 Lines; CHECK-NEXT: ret
ret void ret void
} }
define void @buildvec_dominant2_v2i8(<2 x i8>* %x) { define void @buildvec_dominant2_v2i8(<2 x i8>* %x) {
; CHECK-LABEL: buildvec_dominant2_v2i8: ; CHECK-LABEL: buildvec_dominant2_v2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, -1 ; CHECK-NEXT: vmv.v.i v25, -1
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu
; CHECK-NEXT: vmv.s.x v25, zero ; CHECK-NEXT: vmv.s.x v25, zero
; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu
; CHECK-NEXT: vse8.v v25, (a0) ; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <2 x i8> <i8 0, i8 -1>, <2 x i8>* %x store <2 x i8> <i8 0, i8 -1>, <2 x i8>* %x
ret void ret void
} }
define void @buildvec_dominant0_v2i32(<2 x i64>* %x) { define void @buildvec_dominant0_v2i32(<2 x i64>* %x) {
; RV32-LABEL: buildvec_dominant0_v2i32: ; RV32-LABEL: buildvec_dominant0_v2i32:
Show All 12 Lines
; RV64-NEXT: lui a1, 3641 ; RV64-NEXT: lui a1, 3641
; RV64-NEXT: addiw a1, a1, -455 ; RV64-NEXT: addiw a1, a1, -455
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -455 ; RV64-NEXT: addi a1, a1, -455
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -455 ; RV64-NEXT: addi a1, a1, -455
; RV64-NEXT: slli a1, a1, 13 ; RV64-NEXT: slli a1, a1, 13
; RV64-NEXT: addi a1, a1, -910 ; RV64-NEXT: addi a1, a1, -910
; RV64-NEXT: vsetvli a2, zero, e64,m1,ta,mu
; RV64-NEXT: vmv.s.x v25, a1 ; RV64-NEXT: vmv.s.x v25, a1
; RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; RV64-NEXT: vse64.v v25, (a0) ; RV64-NEXT: vse64.v v25, (a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
store <2 x i64> <i64 2049638230412172402, i64 -1>, <2 x i64>* %x store <2 x i64> <i64 2049638230412172402, i64 -1>, <2 x i64>* %x
ret void ret void
} }
define void @buildvec_dominant1_optsize_v2i32(<2 x i64>* %x) optsize { define void @buildvec_dominant1_optsize_v2i32(<2 x i64>* %x) optsize {
; RV32-LABEL: buildvec_dominant1_optsize_v2i32: ; RV32-LABEL: buildvec_dominant1_optsize_v2i32:
Show All 19 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

Show First 20 Lines • Show All 866 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret void ret void
} }
define void @mulhu_v8i16(<8 x i16>* %x) { define void @mulhu_v8i16(<8 x i16>* %x) {
; CHECK-LABEL: mulhu_v8i16: ; CHECK-LABEL: mulhu_v8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a1, 8, e16,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 8, e16,m1,ta,mu
; CHECK-NEXT: vle16.v v25, (a0) ; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: lui a1, 1048568
; CHECK-NEXT: vmv1r.v v27, v26
; CHECK-NEXT: vmv.s.x v27, a1
; CHECK-NEXT: addi a1, zero, 1 ; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: vsetvli a2, zero, e16,m1,ta,mu ; CHECK-NEXT: vmv.s.x v28, a1
; CHECK-NEXT: vmv.s.x v26, a1
; CHECK-NEXT: vsetivli a1, 8, e16,m1,ta,mu
; CHECK-NEXT: vmv.v.i v27, 0
; CHECK-NEXT: vsetivli a1, 7, e16,m1,tu,mu ; CHECK-NEXT: vsetivli a1, 7, e16,m1,tu,mu
; CHECK-NEXT: vmv1r.v v28, v27 ; CHECK-NEXT: vslideup.vi v26, v28, 6
; CHECK-NEXT: vslideup.vi v28, v26, 6
; CHECK-NEXT: vsetivli a1, 8, e16,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 8, e16,m1,ta,mu
; CHECK-NEXT: lui a1, %hi(.LCPI53_0) ; CHECK-NEXT: lui a1, %hi(.LCPI53_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI53_0) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI53_0)
; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vle16.v v28, (a1)
; CHECK-NEXT: vsrl.vv v28, v25, v28 ; CHECK-NEXT: vsrl.vv v26, v25, v26
; CHECK-NEXT: vmulhu.vv v26, v28, v26 ; CHECK-NEXT: vmulhu.vv v26, v26, v28
; CHECK-NEXT: vsub.vv v25, v25, v26
; CHECK-NEXT: lui a1, 1048568
; CHECK-NEXT: vsetvli a2, zero, e16,m1,ta,mu
; CHECK-NEXT: vmv.s.x v27, a1
; CHECK-NEXT: vsetivli a1, 8, e16,m1,ta,mu
; CHECK-NEXT: lui a1, %hi(.LCPI53_1) ; CHECK-NEXT: lui a1, %hi(.LCPI53_1)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI53_1) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI53_1)
; CHECK-NEXT: vle16.v v28, (a1) ; CHECK-NEXT: vle16.v v28, (a1)
; CHECK-NEXT: vsub.vv v25, v25, v26
; CHECK-NEXT: vmulhu.vv v25, v25, v27 ; CHECK-NEXT: vmulhu.vv v25, v25, v27
; CHECK-NEXT: vadd.vv v25, v25, v26 ; CHECK-NEXT: vadd.vv v25, v25, v26
; CHECK-NEXT: vsrl.vv v25, v25, v28 ; CHECK-NEXT: vsrl.vv v25, v25, v28
; CHECK-NEXT: vse16.v v25, (a0) ; CHECK-NEXT: vse16.v v25, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x i16>, <8 x i16>* %x %a = load <8 x i16>, <8 x i16>* %x
%b = udiv <8 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15> %b = udiv <8 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
store <8 x i16> %b, <8 x i16>* %x store <8 x i16> %b, <8 x i16>* %x
ret void ret void
} }
define void @mulhu_v4i32(<4 x i32>* %x) { define void @mulhu_v4i32(<4 x i32>* %x) {
; CHECK-LABEL: mulhu_v4i32: ; CHECK-LABEL: mulhu_v4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a1, 4, e32,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 4, e32,m1,ta,mu
; CHECK-NEXT: vle32.v v25, (a0) ; CHECK-NEXT: vle32.v v25, (a0)
; CHECK-NEXT: lui a1, 524288
; CHECK-NEXT: vmv.s.x v26, a1
; CHECK-NEXT: vmv.v.i v27, 0
; CHECK-NEXT: vsetivli a1, 3, e32,m1,tu,mu
; CHECK-NEXT: vslideup.vi v27, v26, 2
; CHECK-NEXT: lui a1, %hi(.LCPI54_0) ; CHECK-NEXT: lui a1, %hi(.LCPI54_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI54_0) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI54_0)
; CHECK-NEXT: vsetivli a2, 4, e32,m1,ta,mu
; CHECK-NEXT: vle32.v v26, (a1) ; CHECK-NEXT: vle32.v v26, (a1)
; CHECK-NEXT: vmulhu.vv v26, v25, v26 ; CHECK-NEXT: vmulhu.vv v26, v25, v26
; CHECK-NEXT: vsub.vv v25, v25, v26 ; CHECK-NEXT: vsub.vv v25, v25, v26
; CHECK-NEXT: lui a1, 524288 ; CHECK-NEXT: vmulhu.vv v25, v25, v27
; CHECK-NEXT: vsetvli a2, zero, e32,m1,ta,mu
; CHECK-NEXT: vmv.s.x v27, a1
; CHECK-NEXT: vsetivli a1, 4, e32,m1,ta,mu
; CHECK-NEXT: vmv.v.i v28, 0
; CHECK-NEXT: vsetivli a1, 3, e32,m1,tu,mu
; CHECK-NEXT: vslideup.vi v28, v27, 2
; CHECK-NEXT: vsetivli a1, 4, e32,m1,ta,mu
; CHECK-NEXT: vmulhu.vv v25, v25, v28
; CHECK-NEXT: vadd.vv v25, v25, v26 ; CHECK-NEXT: vadd.vv v25, v25, v26
; CHECK-NEXT: addi a1, zero, 1 ; CHECK-NEXT: addi a1, zero, 1
; CHECK-NEXT: vsetvli a2, zero, e32,m1,ta,mu
; CHECK-NEXT: vmv.s.x v26, a1 ; CHECK-NEXT: vmv.s.x v26, a1
; CHECK-NEXT: vsetivli a1, 4, e32,m1,ta,mu
; CHECK-NEXT: vmv.v.i v27, 2 ; CHECK-NEXT: vmv.v.i v27, 2
; CHECK-NEXT: vsetivli a1, 4, e32,m1,tu,mu ; CHECK-NEXT: vsetivli a1, 4, e32,m1,tu,mu
; CHECK-NEXT: vslideup.vi v27, v26, 3 ; CHECK-NEXT: vslideup.vi v27, v26, 3
; CHECK-NEXT: vsetivli a1, 4, e32,m1,ta,mu ; CHECK-NEXT: vsetivli a1, 4, e32,m1,ta,mu
; CHECK-NEXT: vsrl.vv v25, v25, v27 ; CHECK-NEXT: vsrl.vv v25, v25, v27
; CHECK-NEXT: vse32.v v25, (a0) ; CHECK-NEXT: vse32.v v25, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x i32>, <4 x i32>* %x %a = load <4 x i32>, <4 x i32>* %x
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; RV32-NEXT: vsrl.vv v25, v25, v26 ; RV32-NEXT: vsrl.vv v25, v25, v26
; RV32-NEXT: vse64.v v25, (a0) ; RV32-NEXT: vse64.v v25, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mulhu_v2i64: ; RV64-LABEL: mulhu_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu ; RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; RV64-NEXT: vle64.v v25, (a0) ; RV64-NEXT: vle64.v v25, (a0)
; RV64-NEXT: vmv.v.i v26, 2
; RV64-NEXT: addi a1, zero, 1
; RV64-NEXT: vmv.s.x v26, a1
; RV64-NEXT: lui a1, 1035469 ; RV64-NEXT: lui a1, 1035469
; RV64-NEXT: addiw a1, a1, -819 ; RV64-NEXT: addiw a1, a1, -819
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -819 ; RV64-NEXT: addi a1, a1, -819
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -819 ; RV64-NEXT: addi a1, a1, -819
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -819 ; RV64-NEXT: addi a1, a1, -819
; RV64-NEXT: vmv.v.x v26, a1 ; RV64-NEXT: vmv.v.x v27, a1
; RV64-NEXT: lui a1, 1026731 ; RV64-NEXT: lui a1, 1026731
; RV64-NEXT: addiw a1, a1, -1365 ; RV64-NEXT: addiw a1, a1, -1365
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -1365 ; RV64-NEXT: addi a1, a1, -1365
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -1365 ; RV64-NEXT: addi a1, a1, -1365
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -1365 ; RV64-NEXT: addi a1, a1, -1365
; RV64-NEXT: vsetvli a2, zero, e64,m1,ta,mu ; RV64-NEXT: vmv.s.x v27, a1
; RV64-NEXT: vmv.s.x v26, a1 ; RV64-NEXT: vmulhu.vv v25, v25, v27
; RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; RV64-NEXT: vmulhu.vv v25, v25, v26
; RV64-NEXT: vmv.v.i v26, 2
; RV64-NEXT: addi a1, zero, 1
; RV64-NEXT: vsetvli a2, zero, e64,m1,ta,mu
; RV64-NEXT: vmv.s.x v26, a1
; RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; RV64-NEXT: vsrl.vv v25, v25, v26 ; RV64-NEXT: vsrl.vv v25, v25, v26
; RV64-NEXT: vse64.v v25, (a0) ; RV64-NEXT: vse64.v v25, (a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x %a = load <2 x i64>, <2 x i64>* %x
%b = udiv <2 x i64> %a, <i64 3, i64 5> %b = udiv <2 x i64> %a, <i64 3, i64 5>
store <2 x i64> %b, <2 x i64>* %x store <2 x i64> %b, <2 x i64>* %x
ret void ret void
} }
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; RV32-NEXT: vle32.v v26, (a1) ; RV32-NEXT: vle32.v v26, (a1)
; RV32-NEXT: vsetivli a1, 2, e64,m1,ta,mu ; RV32-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; RV32-NEXT: vmul.vv v26, v25, v26 ; RV32-NEXT: vmul.vv v26, v25, v26
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a2, a1, 1365 ; RV32-NEXT: addi a2, a1, 1365
; RV32-NEXT: vsetivli a3, 4, e32,m1,ta,mu ; RV32-NEXT: vsetivli a3, 4, e32,m1,ta,mu
; RV32-NEXT: vmv.v.x v27, a2 ; RV32-NEXT: vmv.v.x v27, a2
; RV32-NEXT: addi a1, a1, 1366 ; RV32-NEXT: addi a1, a1, 1366
; RV32-NEXT: vsetvli a2, zero, e32,m1,ta,mu
; RV32-NEXT: vmv.s.x v27, a1 ; RV32-NEXT: vmv.s.x v27, a1
; RV32-NEXT: vsetivli a1, 2, e64,m1,ta,mu ; RV32-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; RV32-NEXT: vmulh.vv v25, v25, v27 ; RV32-NEXT: vmulh.vv v25, v25, v27
; RV32-NEXT: vadd.vv v25, v25, v26 ; RV32-NEXT: vadd.vv v25, v25, v26
; RV32-NEXT: lui a1, %hi(.LCPI59_1) ; RV32-NEXT: lui a1, %hi(.LCPI59_1)
; RV32-NEXT: addi a1, a1, %lo(.LCPI59_1) ; RV32-NEXT: addi a1, a1, %lo(.LCPI59_1)
; RV32-NEXT: vsetivli a2, 4, e32,m1,ta,mu ; RV32-NEXT: vsetivli a2, 4, e32,m1,ta,mu
; RV32-NEXT: vle32.v v26, (a1) ; RV32-NEXT: vle32.v v26, (a1)
; RV32-NEXT: vsetivli a1, 2, e64,m1,ta,mu ; RV32-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; RV32-NEXT: vsrl.vv v26, v25, v26 ; RV32-NEXT: vsrl.vv v26, v25, v26
; RV32-NEXT: addi a1, zero, 1 ; RV32-NEXT: addi a1, zero, 1
; RV32-NEXT: vsetvli a2, zero, e32,m1,ta,mu ; RV32-NEXT: vsetivli a2, 4, e32,m1,ta,mu
; RV32-NEXT: vmv.s.x v27, a1 ; RV32-NEXT: vmv.s.x v27, a1
; RV32-NEXT: vsetivli a1, 4, e32,m1,ta,mu
; RV32-NEXT: vmv.v.i v28, 0 ; RV32-NEXT: vmv.v.i v28, 0
; RV32-NEXT: vsetivli a1, 3, e32,m1,tu,mu ; RV32-NEXT: vsetivli a1, 3, e32,m1,tu,mu
; RV32-NEXT: vslideup.vi v28, v27, 2 ; RV32-NEXT: vslideup.vi v28, v27, 2
; RV32-NEXT: vsetivli a1, 2, e64,m1,ta,mu ; RV32-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; RV32-NEXT: vsra.vv v25, v25, v28 ; RV32-NEXT: vsra.vv v25, v25, v28
; RV32-NEXT: vadd.vv v25, v25, v26 ; RV32-NEXT: vadd.vv v25, v25, v26
; RV32-NEXT: vse64.v v25, (a0) ; RV32-NEXT: vse64.v v25, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mulhs_v2i64: ; RV64-LABEL: mulhs_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu ; RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; RV64-NEXT: vle64.v v25, (a0) ; RV64-NEXT: vle64.v v25, (a0)
; RV64-NEXT: vmv.v.i v26, -1 ; RV64-NEXT: vmv.v.i v26, -1
; RV64-NEXT: vsetvli a1, zero, e64,m1,ta,mu
; RV64-NEXT: vmv.s.x v26, zero ; RV64-NEXT: vmv.s.x v26, zero
; RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; RV64-NEXT: vmul.vv v26, v25, v26 ; RV64-NEXT: vmul.vv v26, v25, v26
; RV64-NEXT: lui a1, 21845 ; RV64-NEXT: lui a1, 21845
; RV64-NEXT: addiw a1, a1, 1365 ; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, 1365 ; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, 1365 ; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a2, a1, 1365 ; RV64-NEXT: addi a2, a1, 1365
; RV64-NEXT: vmv.v.x v27, a2 ; RV64-NEXT: vmv.v.x v27, a2
; RV64-NEXT: addi a1, a1, 1366 ; RV64-NEXT: addi a1, a1, 1366
; RV64-NEXT: vsetvli a2, zero, e64,m1,ta,mu
; RV64-NEXT: vmv.s.x v27, a1 ; RV64-NEXT: vmv.s.x v27, a1
; RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; RV64-NEXT: vmulh.vv v25, v25, v27 ; RV64-NEXT: vmulh.vv v25, v25, v27
; RV64-NEXT: vadd.vv v25, v25, v26 ; RV64-NEXT: vadd.vv v25, v25, v26
; RV64-NEXT: addi a1, zero, 63 ; RV64-NEXT: addi a1, zero, 63
; RV64-NEXT: vsrl.vx v26, v25, a1 ; RV64-NEXT: vsrl.vx v26, v25, a1
; RV64-NEXT: vid.v v27 ; RV64-NEXT: vid.v v27
; RV64-NEXT: vsra.vv v25, v25, v27 ; RV64-NEXT: vsra.vv v25, v25, v27
; RV64-NEXT: vadd.vv v25, v25, v26 ; RV64-NEXT: vadd.vv v25, v25, v26
; RV64-NEXT: vse64.v v25, (a0) ; RV64-NEXT: vse64.v v25, (a0)
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; LMULMAX2-NEXT: vadd.vv v26, v26, v28 ; LMULMAX2-NEXT: vadd.vv v26, v26, v28
; LMULMAX2-NEXT: vsrl.vv v26, v26, v8 ; LMULMAX2-NEXT: vsrl.vv v26, v26, v8
; LMULMAX2-NEXT: vse32.v v26, (a0) ; LMULMAX2-NEXT: vse32.v v26, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: mulhu_v8i32: ; LMULMAX1-RV32-LABEL: mulhu_v8i32:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli a1, 4, e32,m1,ta,mu ; LMULMAX1-RV32-NEXT: vsetivli a1, 4, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle32.v v25, (a0)
; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle32.v v25, (a1) ; LMULMAX1-RV32-NEXT: vle32.v v26, (a1)
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI131_0)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI131_0)
; LMULMAX1-RV32-NEXT: vle32.v v26, (a2)
; LMULMAX1-RV32-NEXT: vle32.v v27, (a0)
; LMULMAX1-RV32-NEXT: vmulhu.vv v28, v25, v26
; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v28
; LMULMAX1-RV32-NEXT: lui a2, 524288 ; LMULMAX1-RV32-NEXT: lui a2, 524288
; LMULMAX1-RV32-NEXT: vsetvli a3, zero, e32,m1,ta,mu ; LMULMAX1-RV32-NEXT: vmv.s.x v27, a2
; LMULMAX1-RV32-NEXT: vmv.s.x v29, a2 ; LMULMAX1-RV32-NEXT: vmv.v.i v28, 0
; LMULMAX1-RV32-NEXT: vsetivli a2, 4, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vmv.v.i v30, 0
; LMULMAX1-RV32-NEXT: vsetivli a2, 3, e32,m1,tu,mu ; LMULMAX1-RV32-NEXT: vsetivli a2, 3, e32,m1,tu,mu
; LMULMAX1-RV32-NEXT: vslideup.vi v30, v29, 2 ; LMULMAX1-RV32-NEXT: vslideup.vi v28, v27, 2
; LMULMAX1-RV32-NEXT: vsetivli a2, 4, e32,m1,ta,mu ; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI131_0)
; LMULMAX1-RV32-NEXT: vmulhu.vv v25, v25, v30 ; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI131_0)
; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v28 ; LMULMAX1-RV32-NEXT: vsetivli a3, 4, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle32.v v27, (a2)
; LMULMAX1-RV32-NEXT: vmulhu.vv v29, v26, v27
; LMULMAX1-RV32-NEXT: vsub.vv v26, v26, v29
; LMULMAX1-RV32-NEXT: vmulhu.vv v26, v26, v28
; LMULMAX1-RV32-NEXT: vadd.vv v26, v26, v29
; LMULMAX1-RV32-NEXT: addi a2, zero, 1 ; LMULMAX1-RV32-NEXT: addi a2, zero, 1
; LMULMAX1-RV32-NEXT: vsetvli a3, zero, e32,m1,ta,mu ; LMULMAX1-RV32-NEXT: vmv.s.x v29, a2
; LMULMAX1-RV32-NEXT: vmv.s.x v28, a2 ; LMULMAX1-RV32-NEXT: vmv.v.i v30, 2
; LMULMAX1-RV32-NEXT: vsetivli a2, 4, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vmv.v.i v29, 2
; LMULMAX1-RV32-NEXT: vsetivli a2, 4, e32,m1,tu,mu ; LMULMAX1-RV32-NEXT: vsetivli a2, 4, e32,m1,tu,mu
; LMULMAX1-RV32-NEXT: vslideup.vi v29, v28, 3 ; LMULMAX1-RV32-NEXT: vslideup.vi v30, v29, 3
; LMULMAX1-RV32-NEXT: vsetivli a2, 4, e32,m1,ta,mu ; LMULMAX1-RV32-NEXT: vsetivli a2, 4, e32,m1,ta,mu
; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v29 ; LMULMAX1-RV32-NEXT: vsrl.vv v26, v26, v30
; LMULMAX1-RV32-NEXT: vmulhu.vv v26, v27, v26 ; LMULMAX1-RV32-NEXT: vmulhu.vv v27, v25, v27
; LMULMAX1-RV32-NEXT: vsub.vv v27, v27, v26 ; LMULMAX1-RV32-NEXT: vsub.vv v25, v25, v27
; LMULMAX1-RV32-NEXT: vmulhu.vv v27, v27, v30 ; LMULMAX1-RV32-NEXT: vmulhu.vv v25, v25, v28
; LMULMAX1-RV32-NEXT: vadd.vv v26, v27, v26 ; LMULMAX1-RV32-NEXT: vadd.vv v25, v25, v27
; LMULMAX1-RV32-NEXT: vsrl.vv v26, v26, v29 ; LMULMAX1-RV32-NEXT: vsrl.vv v25, v25, v30
; LMULMAX1-RV32-NEXT: vse32.v v26, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v25, (a0)
; LMULMAX1-RV32-NEXT: vse32.v v25, (a1) ; LMULMAX1-RV32-NEXT: vse32.v v26, (a1)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: mulhu_v8i32: ; LMULMAX1-RV64-LABEL: mulhu_v8i32:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli a1, 4, e32,m1,ta,mu ; LMULMAX1-RV64-NEXT: vsetivli a1, 4, e32,m1,ta,mu
; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle32.v v25, (a1) ; LMULMAX1-RV64-NEXT: vle32.v v25, (a1)
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI131_0) ; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI131_0)
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; LMULMAX2-RV32-NEXT: lui a1, %hi(.LCPI132_0) ; LMULMAX2-RV32-NEXT: lui a1, %hi(.LCPI132_0)
; LMULMAX2-RV32-NEXT: addi a1, a1, %lo(.LCPI132_0) ; LMULMAX2-RV32-NEXT: addi a1, a1, %lo(.LCPI132_0)
; LMULMAX2-RV32-NEXT: vsetivli a2, 8, e32,m2,ta,mu ; LMULMAX2-RV32-NEXT: vsetivli a2, 8, e32,m2,ta,mu
; LMULMAX2-RV32-NEXT: vle32.v v28, (a1) ; LMULMAX2-RV32-NEXT: vle32.v v28, (a1)
; LMULMAX2-RV32-NEXT: vsetivli a1, 4, e64,m2,ta,mu ; LMULMAX2-RV32-NEXT: vsetivli a1, 4, e64,m2,ta,mu
; LMULMAX2-RV32-NEXT: vmulhu.vv v28, v26, v28 ; LMULMAX2-RV32-NEXT: vmulhu.vv v28, v26, v28
; LMULMAX2-RV32-NEXT: vsub.vv v26, v26, v28 ; LMULMAX2-RV32-NEXT: vsub.vv v26, v26, v28
; LMULMAX2-RV32-NEXT: lui a1, 524288 ; LMULMAX2-RV32-NEXT: lui a1, 524288
; LMULMAX2-RV32-NEXT: vsetvli a2, zero, e32,m2,ta,mu ; LMULMAX2-RV32-NEXT: vsetivli a2, 8, e32,m2,ta,mu
; LMULMAX2-RV32-NEXT: vmv.s.x v30, a1 ; LMULMAX2-RV32-NEXT: vmv.s.x v30, a1
; LMULMAX2-RV32-NEXT: vsetivli a1, 8, e32,m2,ta,mu
; LMULMAX2-RV32-NEXT: vmv.v.i v8, 0 ; LMULMAX2-RV32-NEXT: vmv.v.i v8, 0
; LMULMAX2-RV32-NEXT: vsetivli a1, 6, e32,m2,tu,mu ; LMULMAX2-RV32-NEXT: vsetivli a1, 6, e32,m2,tu,mu
; LMULMAX2-RV32-NEXT: vslideup.vi v8, v30, 5 ; LMULMAX2-RV32-NEXT: vslideup.vi v8, v30, 5
; LMULMAX2-RV32-NEXT: vsetivli a1, 4, e64,m2,ta,mu ; LMULMAX2-RV32-NEXT: vsetivli a1, 4, e64,m2,ta,mu
; LMULMAX2-RV32-NEXT: vmulhu.vv v26, v26, v8 ; LMULMAX2-RV32-NEXT: vmulhu.vv v26, v26, v8
; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v28 ; LMULMAX2-RV32-NEXT: vadd.vv v26, v26, v28
; LMULMAX2-RV32-NEXT: lui a1, %hi(.LCPI132_1) ; LMULMAX2-RV32-NEXT: lui a1, %hi(.LCPI132_1)
; LMULMAX2-RV32-NEXT: addi a1, a1, %lo(.LCPI132_1) ; LMULMAX2-RV32-NEXT: addi a1, a1, %lo(.LCPI132_1)
; LMULMAX2-RV32-NEXT: vsetivli a2, 8, e32,m2,ta,mu ; LMULMAX2-RV32-NEXT: vsetivli a2, 8, e32,m2,ta,mu
; LMULMAX2-RV32-NEXT: vle32.v v28, (a1) ; LMULMAX2-RV32-NEXT: vle32.v v28, (a1)
; LMULMAX2-RV32-NEXT: vsetivli a1, 4, e64,m2,ta,mu ; LMULMAX2-RV32-NEXT: vsetivli a1, 4, e64,m2,ta,mu
; LMULMAX2-RV32-NEXT: vsrl.vv v26, v26, v28 ; LMULMAX2-RV32-NEXT: vsrl.vv v26, v26, v28
; LMULMAX2-RV32-NEXT: vse64.v v26, (a0) ; LMULMAX2-RV32-NEXT: vse64.v v26, (a0)
; LMULMAX2-RV32-NEXT: ret ; LMULMAX2-RV32-NEXT: ret
; ;
; LMULMAX2-RV64-LABEL: mulhu_v4i64: ; LMULMAX2-RV64-LABEL: mulhu_v4i64:
; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli a1, 4, e64,m2,ta,mu ; LMULMAX2-RV64-NEXT: vsetivli a1, 4, e64,m2,ta,mu
; LMULMAX2-RV64-NEXT: vle64.v v26, (a0) ; LMULMAX2-RV64-NEXT: vle64.v v26, (a0)
; LMULMAX2-RV64-NEXT: addi a1, zero, -1
; LMULMAX2-RV64-NEXT: slli a1, a1, 63
; LMULMAX2-RV64-NEXT: vmv.s.x v28, a1
; LMULMAX2-RV64-NEXT: vmv.v.i v30, 0
; LMULMAX2-RV64-NEXT: vsetivli a1, 3, e64,m2,tu,mu
; LMULMAX2-RV64-NEXT: vslideup.vi v30, v28, 2
; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI132_0) ; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI132_0)
; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI132_0) ; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI132_0)
; LMULMAX2-RV64-NEXT: vsetivli a2, 4, e64,m2,ta,mu
; LMULMAX2-RV64-NEXT: vle64.v v28, (a1) ; LMULMAX2-RV64-NEXT: vle64.v v28, (a1)
; LMULMAX2-RV64-NEXT: vmulhu.vv v28, v26, v28 ; LMULMAX2-RV64-NEXT: vmulhu.vv v28, v26, v28
; LMULMAX2-RV64-NEXT: vsub.vv v26, v26, v28
; LMULMAX2-RV64-NEXT: addi a1, zero, -1
; LMULMAX2-RV64-NEXT: slli a1, a1, 63
; LMULMAX2-RV64-NEXT: vsetvli a2, zero, e64,m2,ta,mu
; LMULMAX2-RV64-NEXT: vmv.s.x v30, a1
; LMULMAX2-RV64-NEXT: vsetivli a1, 4, e64,m2,ta,mu
; LMULMAX2-RV64-NEXT: vmv.v.i v8, 0
; LMULMAX2-RV64-NEXT: vsetivli a1, 3, e64,m2,tu,mu
; LMULMAX2-RV64-NEXT: vslideup.vi v8, v30, 2
; LMULMAX2-RV64-NEXT: vsetivli a1, 4, e64,m2,ta,mu
; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI132_1) ; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI132_1)
; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI132_1) ; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI132_1)
; LMULMAX2-RV64-NEXT: vle64.v v30, (a1) ; LMULMAX2-RV64-NEXT: vle64.v v8, (a1)
; LMULMAX2-RV64-NEXT: vmulhu.vv v26, v26, v8 ; LMULMAX2-RV64-NEXT: vsub.vv v26, v26, v28
; LMULMAX2-RV64-NEXT: vmulhu.vv v26, v26, v30
; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v28 ; LMULMAX2-RV64-NEXT: vadd.vv v26, v26, v28
; LMULMAX2-RV64-NEXT: vsrl.vv v26, v26, v30 ; LMULMAX2-RV64-NEXT: vsrl.vv v26, v26, v8
; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX2-RV64-NEXT: vse64.v v26, (a0)
; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: mulhu_v4i64: ; LMULMAX1-RV32-LABEL: mulhu_v4i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli a1, 2, e64,m1,ta,mu ; LMULMAX1-RV32-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vle64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vle64.v v25, (a0)
; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: addi a1, a0, 16
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; LMULMAX1-RV32-NEXT: vsetivli a2, 2, e64,m1,ta,mu ; LMULMAX1-RV32-NEXT: vsetivli a2, 2, e64,m1,ta,mu
; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v27 ; LMULMAX1-RV32-NEXT: vdivu.vv v25, v25, v27
; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
; LMULMAX1-RV32-NEXT: vse64.v v26, (a1) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a1)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: mulhu_v4i64: ; LMULMAX1-RV64-LABEL: mulhu_v4i64:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: addi a2, zero, 2 ; LMULMAX1-RV64-NEXT: addi a1, zero, 2
; LMULMAX1-RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu ; LMULMAX1-RV64-NEXT: vsetivli a2, 2, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: addi a2, a0, 16
; LMULMAX1-RV64-NEXT: vle64.v v26, (a1) ; LMULMAX1-RV64-NEXT: vle64.v v26, (a2)
; LMULMAX1-RV64-NEXT: vmv.v.i v27, 0
; LMULMAX1-RV64-NEXT: addi a3, zero, -1
; LMULMAX1-RV64-NEXT: slli a3, a3, 63
; LMULMAX1-RV64-NEXT: vmv.s.x v27, a3
; LMULMAX1-RV64-NEXT: lui a3, 1044935 ; LMULMAX1-RV64-NEXT: lui a3, 1044935
; LMULMAX1-RV64-NEXT: addiw a3, a3, 455 ; LMULMAX1-RV64-NEXT: addiw a3, a3, 455
; LMULMAX1-RV64-NEXT: slli a3, a3, 12 ; LMULMAX1-RV64-NEXT: slli a3, a3, 12
; LMULMAX1-RV64-NEXT: addi a3, a3, 455 ; LMULMAX1-RV64-NEXT: addi a3, a3, 455
; LMULMAX1-RV64-NEXT: slli a3, a3, 12 ; LMULMAX1-RV64-NEXT: slli a3, a3, 12
; LMULMAX1-RV64-NEXT: addi a3, a3, 455 ; LMULMAX1-RV64-NEXT: addi a3, a3, 455
; LMULMAX1-RV64-NEXT: slli a3, a3, 13 ; LMULMAX1-RV64-NEXT: slli a3, a3, 13
; LMULMAX1-RV64-NEXT: addi a3, a3, 911 ; LMULMAX1-RV64-NEXT: addi a3, a3, 911
; LMULMAX1-RV64-NEXT: vmv.v.x v27, a3 ; LMULMAX1-RV64-NEXT: vmv.v.x v28, a3
; LMULMAX1-RV64-NEXT: lui a3, 4681 ; LMULMAX1-RV64-NEXT: lui a3, 4681
; LMULMAX1-RV64-NEXT: addiw a3, a3, 585 ; LMULMAX1-RV64-NEXT: addiw a3, a3, 585
; LMULMAX1-RV64-NEXT: slli a3, a3, 12 ; LMULMAX1-RV64-NEXT: slli a3, a3, 12
; LMULMAX1-RV64-NEXT: addi a3, a3, 585 ; LMULMAX1-RV64-NEXT: addi a3, a3, 585
; LMULMAX1-RV64-NEXT: slli a3, a3, 12 ; LMULMAX1-RV64-NEXT: slli a3, a3, 12
; LMULMAX1-RV64-NEXT: addi a3, a3, 585 ; LMULMAX1-RV64-NEXT: addi a3, a3, 585
; LMULMAX1-RV64-NEXT: slli a3, a3, 13 ; LMULMAX1-RV64-NEXT: slli a3, a3, 13
; LMULMAX1-RV64-NEXT: addi a3, a3, 1171 ; LMULMAX1-RV64-NEXT: addi a3, a3, 1171
; LMULMAX1-RV64-NEXT: vsetvli a4, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v27, a3
; LMULMAX1-RV64-NEXT: vsetivli a3, 2, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmulhu.vv v27, v26, v27
; LMULMAX1-RV64-NEXT: vsub.vv v26, v26, v27
; LMULMAX1-RV64-NEXT: vmv.v.i v28, 0
; LMULMAX1-RV64-NEXT: addi a3, zero, -1
; LMULMAX1-RV64-NEXT: slli a3, a3, 63
; LMULMAX1-RV64-NEXT: vsetvli a4, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v28, a3 ; LMULMAX1-RV64-NEXT: vmv.s.x v28, a3
; LMULMAX1-RV64-NEXT: vsetivli a3, 2, e64,m1,ta,mu ; LMULMAX1-RV64-NEXT: vmulhu.vv v28, v26, v28
; LMULMAX1-RV64-NEXT: vmulhu.vv v26, v26, v28 ; LMULMAX1-RV64-NEXT: vsub.vv v26, v26, v28
; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v27 ; LMULMAX1-RV64-NEXT: vmulhu.vv v26, v26, v27
; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v28
; LMULMAX1-RV64-NEXT: vmv.v.i v27, 3 ; LMULMAX1-RV64-NEXT: vmv.v.i v27, 3
; LMULMAX1-RV64-NEXT: vsetvli a3, zero, e64,m1,ta,mu ; LMULMAX1-RV64-NEXT: vmv.s.x v27, a1
; LMULMAX1-RV64-NEXT: vmv.s.x v27, a2
; LMULMAX1-RV64-NEXT: vsetivli a2, 2, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vsrl.vv v26, v26, v27 ; LMULMAX1-RV64-NEXT: vsrl.vv v26, v26, v27
; LMULMAX1-RV64-NEXT: lui a2, 1035469
; LMULMAX1-RV64-NEXT: addiw a2, a2, -819
; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, -819
; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, -819
; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, -819
; LMULMAX1-RV64-NEXT: vmv.v.x v27, a2
; LMULMAX1-RV64-NEXT: lui a2, 1026731
; LMULMAX1-RV64-NEXT: addiw a2, a2, -1365
; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, -1365
; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, -1365
; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, -1365
; LMULMAX1-RV64-NEXT: vsetvli a3, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v27, a2
; LMULMAX1-RV64-NEXT: vsetivli a2, 2, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmulhu.vv v25, v25, v27
; LMULMAX1-RV64-NEXT: vmv.v.i v27, 2 ; LMULMAX1-RV64-NEXT: vmv.v.i v27, 2
; LMULMAX1-RV64-NEXT: addi a2, zero, 1 ; LMULMAX1-RV64-NEXT: addi a1, zero, 1
; LMULMAX1-RV64-NEXT: vsetvli a3, zero, e64,m1,ta,mu ; LMULMAX1-RV64-NEXT: vmv.s.x v27, a1
; LMULMAX1-RV64-NEXT: vmv.s.x v27, a2 ; LMULMAX1-RV64-NEXT: lui a1, 1035469
; LMULMAX1-RV64-NEXT: vsetivli a2, 2, e64,m1,ta,mu ; LMULMAX1-RV64-NEXT: addiw a1, a1, -819
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
; LMULMAX1-RV64-NEXT: addi a1, a1, -819
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
; LMULMAX1-RV64-NEXT: addi a1, a1, -819
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
; LMULMAX1-RV64-NEXT: addi a1, a1, -819
; LMULMAX1-RV64-NEXT: vmv.v.x v28, a1
; LMULMAX1-RV64-NEXT: lui a1, 1026731
; LMULMAX1-RV64-NEXT: addiw a1, a1, -1365
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
; LMULMAX1-RV64-NEXT: addi a1, a1, -1365
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
; LMULMAX1-RV64-NEXT: addi a1, a1, -1365
; LMULMAX1-RV64-NEXT: slli a1, a1, 12
; LMULMAX1-RV64-NEXT: addi a1, a1, -1365
; LMULMAX1-RV64-NEXT: vmv.s.x v28, a1
; LMULMAX1-RV64-NEXT: vmulhu.vv v25, v25, v28
; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v27 ; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v27
; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v26, (a1) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a2)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x %a = load <4 x i64>, <4 x i64>* %x
%b = udiv <4 x i64> %a, <i64 3, i64 5, i64 7, i64 9> %b = udiv <4 x i64> %a, <i64 3, i64 5, i64 7, i64 9>
store <4 x i64> %b, <4 x i64>* %x store <4 x i64> %b, <4 x i64>* %x
ret void ret void
} }
define void @mulhs_v32i8(<32 x i8>* %x) { define void @mulhs_v32i8(<32 x i8>* %x) {
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; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v27 ; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v27
; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
; LMULMAX1-RV32-NEXT: vse64.v v26, (a1) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a1)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: mulhs_v4i64: ; LMULMAX1-RV64-LABEL: mulhs_v4i64:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu ; LMULMAX1-RV64-NEXT: vsetivli a1, 2, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle64.v v26, (a1) ; LMULMAX1-RV64-NEXT: vle64.v v25, (a1)
; LMULMAX1-RV64-NEXT: vle64.v v26, (a0)
; LMULMAX1-RV64-NEXT: vmv.v.i v27, -1 ; LMULMAX1-RV64-NEXT: vmv.v.i v27, -1
; LMULMAX1-RV64-NEXT: vsetvli a2, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v27, zero ; LMULMAX1-RV64-NEXT: vmv.s.x v27, zero
; LMULMAX1-RV64-NEXT: vsetivli a2, 2, e64,m1,ta,mu ; LMULMAX1-RV64-NEXT: vmul.vv v28, v25, v27
; LMULMAX1-RV64-NEXT: vmul.vv v28, v26, v27
; LMULMAX1-RV64-NEXT: lui a2, 21845 ; LMULMAX1-RV64-NEXT: lui a2, 21845
; LMULMAX1-RV64-NEXT: addiw a2, a2, 1365 ; LMULMAX1-RV64-NEXT: addiw a2, a2, 1365
; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, 1365 ; LMULMAX1-RV64-NEXT: addi a2, a2, 1365
; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, 1365 ; LMULMAX1-RV64-NEXT: addi a2, a2, 1365
; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a3, a2, 1365 ; LMULMAX1-RV64-NEXT: addi a3, a2, 1365
; LMULMAX1-RV64-NEXT: vmv.v.x v29, a3 ; LMULMAX1-RV64-NEXT: vmv.v.x v29, a3
; LMULMAX1-RV64-NEXT: addi a2, a2, 1366 ; LMULMAX1-RV64-NEXT: addi a2, a2, 1366
; LMULMAX1-RV64-NEXT: vsetvli a3, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v29, a2 ; LMULMAX1-RV64-NEXT: vmv.s.x v29, a2
; LMULMAX1-RV64-NEXT: vsetivli a2, 2, e64,m1,ta,mu ; LMULMAX1-RV64-NEXT: vmulh.vv v25, v25, v29
; LMULMAX1-RV64-NEXT: vmulh.vv v26, v26, v29 ; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v28
; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v28
; LMULMAX1-RV64-NEXT: addi a2, zero, 63 ; LMULMAX1-RV64-NEXT: addi a2, zero, 63
; LMULMAX1-RV64-NEXT: vsrl.vx v28, v26, a2 ; LMULMAX1-RV64-NEXT: vsrl.vx v28, v25, a2
; LMULMAX1-RV64-NEXT: vid.v v30 ; LMULMAX1-RV64-NEXT: vid.v v30
; LMULMAX1-RV64-NEXT: vsra.vv v26, v26, v30
; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v28
; LMULMAX1-RV64-NEXT: vmul.vv v27, v25, v27
; LMULMAX1-RV64-NEXT: vmulh.vv v25, v25, v29
; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v27
; LMULMAX1-RV64-NEXT: vsrl.vx v27, v25, a2
; LMULMAX1-RV64-NEXT: vsra.vv v25, v25, v30 ; LMULMAX1-RV64-NEXT: vsra.vv v25, v25, v30
; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v27 ; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v28
; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vmul.vv v27, v26, v27
; LMULMAX1-RV64-NEXT: vse64.v v26, (a1) ; LMULMAX1-RV64-NEXT: vmulh.vv v26, v26, v29
; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v27
; LMULMAX1-RV64-NEXT: vsrl.vx v27, v26, a2
; LMULMAX1-RV64-NEXT: vsra.vv v26, v26, v30
; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v27
; LMULMAX1-RV64-NEXT: vse64.v v26, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v25, (a1)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x %a = load <4 x i64>, <4 x i64>* %x
%b = sdiv <4 x i64> %a, <i64 3, i64 -3, i64 3, i64 -3> %b = sdiv <4 x i64> %a, <i64 3, i64 -3, i64 3, i64 -3>
store <4 x i64> %b, <4 x i64>* %x store <4 x i64> %b, <4 x i64>* %x
ret void ret void
} }
define void @smin_v32i8(<32 x i8>* %x, <32 x i8>* %y) { define void @smin_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
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