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[RISCV] Support INSERT_SUBVECTOR on vector masks
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Authored by frasercrmck on Feb 26 2021, 8:35 AM.

Details

Summary

Like with EXTRACT_SUBVECTOR, INSERT_SUBVECTOR poses a problem
for vector masks as RVV isn't able to slide mask types around. We choose
instead to bitcast to equivalently-sized i8 types where we can, else we
zero-extend, perform the operation, and truncate back down.

One test was left disabled due to a crash in the legalizer.

Diff Detail

Event Timeline

frasercrmck created this revision.Feb 26 2021, 8:35 AM
frasercrmck requested review of this revision.Feb 26 2021, 8:35 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 26 2021, 8:35 AM
  • add missing bitcast
craig.topper added inline comments.Feb 26 2021, 2:24 PM
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
396

I'm working on a fix for this.

craig.topper added inline comments.Feb 26 2021, 2:48 PM
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
396

https://reviews.llvm.org/D97582 should fix this. Before the introduction of experimental.vector.insert there was almost no way to create an INSERT_SUBVECTOR until after type legalization so the code wasn't well exercised.

craig.topper accepted this revision.Feb 26 2021, 4:09 PM

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp
2583

You can call getBitcast unconditionally.

This revision is now accepted and ready to land.Feb 26 2021, 4:09 PM
This revision was automatically updated to reflect the committed changes.
frasercrmck marked 3 inline comments as done.Mar 1 2021, 4:12 AM
frasercrmck added inline comments.
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
2583

Yep, did so prior to merging. Cheers.

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
396

Thanks. Now that this was merged you can hopefully enable this as your test case.