Hidden behind a compilation option -riscv-fixed-len-rvv, the RISC-V
backend may now compile simple functions for non-scalable v2i32 and
v4i32 vector types.
The approach is VLEN-agnostic but assumes VLEN>=64, much like the
scalable RVV support. This allows the compiler to support any 64-byte
vector type with a consistent ABI:
v2i8: e8, m1, AVL=2 v2i32: e32, m1, AVL=2 v4i32: e32, m2, AVL=4 v16i16: e16, m4, AVL=16 v8i64: e64, m8, AVL=8 v16i32: e32, m8, AVL=16
There are tradeoffs to this design. Requiring an LMUL=8 for v16i32 even when VLEN>=512 could fit it in LMUL=1 is an example.
Other designs are available, such as by supporting non-scalable vectors by compiling for a specific VLEN, and/or by using VLMAX equal to the vector length. It's not clear to me how well LLVM would cope with this design, though.