[AArch64][SVE] Emit DWARF location expression for SVE stack objects.

[sdesmalen]

Summary

Extend PEI to emit a DWARF expression for StackOffsets that have
a fixed and scalable component. This means the expression that needs
to be added is either:

<base> + offset

or:

<base> + offset + scalable_offset * scalereg

where for SVE, the scale reg is the Vector Granule Dwarf register, which
encodes the number of 64bit 'granules' in an SVE vector and which
the debugger can evaluate at runtime.

[SjoerdMeijer]

Adding @ostannard who might have looked at DWARF info before.

[sdesmalen]

Gentle ping.

(Or perhaps someone has a suggestion for a reviewer?)

[aprantl]

llvm/lib/IR/DebugInfoMetadata.cpp

1143 ↗

(On Diff #300205)

We currently don't allow hardcoded registers inside of a DIExpression, The clean solution for this would be to rebase this on the patch that adds support for DW_OP_LLVM_argX / DBG_VALUE_LIST.

[sdesmalen]

llvm/lib/IR/DebugInfoMetadata.cpp

1143 ↗

(On Diff #300205)

Hi @aprantl, thanks for having a look at this patch.

I looked at the proposal for DW_OP_LLVM_argX/DBG_VALUE_LIST and it seems that the scope of that work is a lot wider than what's needed for this purpose and I don't immediately see how I would represent these expressions using that mechanism, specifically because ScaleReg itself has no value in IR/MIR.

Just to clarify the use-case for AArch64 SVE: ScaleReg is always the same register, namely register 46 which is the DWARF register that contains the value for VG, the number of 64-bit "vector granules " in a scalable vector. During the program VG is constant. A runtime value is needed, because the length of the vector isn't known at compile-time. Hence the reason that DWARF for the Arm® 64-bit Architecture (AArch64) specifies the VG register to contain this value, so it can be used in forming DWARF expressions, e.g. to say that an offset (or number of elements when describing a vector type) is scaled by VG.

I can see why it is not customary or considered bad practice to hard-code registers directly in a DIExpression, but in this case I don't think this is really this a problem, given that in this context the register should actually be a hardcoded register.

Given this somewhat limited use-case, I'm not sure if the concern here is with the interface (i.e. we don't want to expose an explicit ScaleReg in this interface, as that opens the interface up to wrong uses of it), or whether the problem really is with the data that the DIExpression contains. i.e. Is there anything fundamental that prevents a DIExpression from containing a hard-coded register?

If not, I could modify the patch to have the target return a self-built DIExpression for the given offset, that can be prepended in PEI. If that would be fine, then I would much prefer that route over rebasing on what seems like a significant functional refactoring effort, which may take a while before it all lands.

What do you think?

[sdesmalen]

Refactored the patch so that DIExpression no longer exposes a possibility to hard-code a register. Instead this patch adds TargetRegisterInfo::prependOffsetExpression, which can be overridden by the target to generate an expression for a StackOffset if part of that offset is scalable (and thus needs a target-specific expression to describe the offset). For SVE it generates the expression manually in the form of a SmallVector<uint64_t> and prepends it to the given DIExpression. The default implementation in TargetRegisterInfo will use DIExpression::prepend() with a byte-sized offset.

[david-arm]

I think the approach here looks good to me, but maybe give others a chance to review first?

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

618

nit: Additional whitespace

llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir

16

I'm not very familiar with the DWARF dump so I apologise if I misunderstood something, but is this only testing either pure scalable or pure fixed offsets? Looking at fillOffsetExpression I thought there might be offsets made up of byte-sized and vg-sized offsets, i.e. with two DW_OP_plus commands.

[sdesmalen]

Removed whitespace.

[sdesmalen]

llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir

16

This is testing a combination of both, i.e.

(DW_OP_breg31 WSP+16), 
((DW_OP_lit16, DW_OP_bregx VG+0), DW_OP_mul),
DW_OP_plus

<=> (SP + 16) + (16 * VG)

[jmorse]

(Responding to inline comments) I think the main concern with hard-coding registers in DIExpressions at this stage is that LLVM isn't able to identify when that register is clobbered later on, and terminate the variable location. However, as you say:

Just to clarify the use-case for AArch64 SVE: ScaleReg is always the same register, namely register 46 which is the DWARF register that contains the value for VG, the number of 64-bit "vector granules " in a scalable vector. During the program VG is constant. A runtime value is needed, because the length of the vector isn't known at compile-time.

To confirm my understanding, 'VG' isn't a conventional "register", but instead it's a target-specific way to signal "whatever the vector scale factor is right now"? Given that it's a runtime constant, I think that resolves the concerns about being a hard-coded value, it doesn't need to be tracked in the same way that conventional registers are.

On the whole, LGTM, but I'd wait a bit to see if @aprantl is happy with the explanation. (Adding debug-info group too).

llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir

10–11

Could I suggest adding a larger DIExpression as the input to this check, for example an extra DW_OP_uconst, 8, DW_OP_plus just to ensure expression composition through your prependOffsetExpression implementation is covered in this test.

I'm assuming that the "*svint32_t" types act like aggregates in some way, and so can't have any other DWARF expression operators applied to them.

42

Could you remove the attributes for #1; for debug-info tests un-necessary attributes become an un-necessary burden.

[sdesmalen]

• Extended DIExpression to better test prepend.
• Removed unnecessary attributes

[sdesmalen]

Hi @jmorse, thanks for reviewing this patch!

In D90020#2436998, @jmorse wrote:

(Responding to inline comments) I think the main concern with hard-coding registers in DIExpressions at this stage is that LLVM isn't able to identify when that register is clobbered later on, and terminate the variable location. However, as you say:

Just to clarify the use-case for AArch64 SVE: ScaleReg is always the same register, namely register 46 which is the DWARF register that contains the value for VG, the number of 64-bit "vector granules " in a scalable vector. During the program VG is constant. A runtime value is needed, because the length of the vector isn't known at compile-time.

To confirm my understanding, 'VG' isn't a conventional "register", but instead it's a target-specific way to signal "whatever the vector scale factor is right now"? Given that it's a runtime constant, I think that resolves the concerns about being a hard-coded value, it doesn't need to be tracked in the same way that conventional registers are.

Yes, I think that's a good summary. It is indeed a way to describe a runtime constant, rather than describing a register, since there is no physical register associated with it.

On the whole, LGTM, but I'd wait a bit to see if @aprantl is happy with the explanation. (Adding debug-info group too).

Thanks, will do!

llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir

10–11

Could I suggest adding a larger DIExpression as the input to this check, for example an extra DW_OP_uconst, 8, DW_OP_plus just to ensure expression composition through your prependOffsetExpression implementation is covered in this test.

Good suggestion, I've updated the test.

I'm assuming that the "*svint32_t" types act like aggregates in some way, and so can't have any other DWARF expression operators applied to them.

I think that's right, svint32_t are more or less opaque vector types. Do you have an example of expressions that would apply for regular (fixed-width) vectors?

[jmorse]

llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir

10–11

Do you have an example of expressions that would apply for regular (fixed-width) vectors?

Doing a quick search, I see a couple of examples:

llvm/test/DebugInfo/MIR/ARM/split-superreg-complex.mir
llvm/test/CodeGen/AMDGPU/debug-value.ll

that appear to apply non-trivial DIExpressions to fixed width vectors. Exactly how to interpret them is a bit beyond me alas, it may or may not be a concern with scalable vectors.

[StephenTozer]

llvm/lib/IR/DebugInfoMetadata.cpp

1143 ↗

(On Diff #300205)

As the author of the DBG_VALUE_LIST patch I agree that it'd be a bad idea to rebase onto that patch, since this patch doesn't strictly need it and that patch will probably take some time to land. I'm not sure if there's really a problem with including a hard-coded register in a DIExpression before final DWARF emission. If at some point we wish to add validation that registers never appear in DIExpressions, or if another implementation of scalable vector implementation that uses a different register is added, then I think the answer would be to create a new DIExpression operator specifically to refer to the contents of the scalable vector register; this could then be replaced by the hardcoded register during DWARF emission.

[sdesmalen]

In D90020#2436998, @jmorse wrote:

On the whole, LGTM, but I'd wait a bit to see if @aprantl is happy with the explanation. (Adding debug-info group too).

@jmorse, would you be happy to formally accept the patch?

@aprantl based on the discussion, are you happy with the approach set out in this patch?

llvm/lib/IR/DebugInfoMetadata.cpp

1143 ↗

(On Diff #300205)

Thank you for confirming @StephenTozer!

[jmorse]

LGTM

[david-arm]

Hi everyone, thanks for all the review comments! Unless anyone has strong objections I'd like to land this patch on Thursday on Sander's behalf, since he is on holiday at the moment.

[dstenb]

I'm sorry for chiming in so late here! I have a comment about the prependOffsetExpression target hook.

llvm/lib/CodeGen/TargetRegisterInfo.cpp

538

I think I would be better to have explicit bool arguments for each of the flags that are contained here. If we keep the mask here, we could later on, when introducing a new flag, end up in situations where the new flag would be ignored by some target implementations, and that could be hard to detect.

Another solution could be to have the deref, stack value and entry value handling in this function, and then have it invoke a getOffsetOpcodes(Offset, Ops) target hook, or something along those lines, that produces the target specific expression for the offset.

At the risk of me overlooking some details for why it would be feasible or practical, I think I would prefer the latter interface.

[dstenb]

llvm/lib/CodeGen/TargetRegisterInfo.cpp

538

would not be feasible or practical

[sdesmalen]

• Made TargetRegisterInfo::prependOffsetExpression non-virtual and changed it to handle the Prepend flags.
• Added virtual method TargetRegisterInfo::getOffsetOpcodes, which gets called by prependOffsetExpression.

[sdesmalen]

In D90020#2455122, @dstenb wrote:

I'm sorry for chiming in so late here! I have a comment about the prependOffsetExpression target hook.

Thanks for the suggestion, you made a good point that this interface was error prone when new flags are added in the future. I've updated the patch and added the virtual interface getOffsetOpcodes alongside prependOffsetExpression (made non-virtual and now handles the Deref, Stack/Entry Value). Let me know if this is how you imagined it.

[dstenb]

In D90020#2477208, @sdesmalen wrote:

In D90020#2455122, @dstenb wrote:

I'm sorry for chiming in so late here! I have a comment about the prependOffsetExpression target hook.

Thanks for the suggestion, you made a good point that this interface was error prone when new flags are added in the future. I've updated the patch and added the virtual interface getOffsetOpcodes alongside prependOffsetExpression (made non-virtual and now handles the Deref, Stack/Entry Value). Let me know if this is how you imagined it.

Yes, thanks!

Since the prependOffsetExpression function is outside DIExpression perhaps it is worth just adding an assert that catches unknown flags?

assert((PrependFlags & ~(DerefBefore | DerefAfter | StackValue | EntryValue)) == 0 && "Unknown prepend flag");

[sdesmalen]

Added assert.

[sdesmalen]

In D90020#2478868, @dstenb wrote:

Since the prependOffsetExpression function is outside DIExpression perhaps it is worth just adding an assert that catches unknown flags?

assert((PrependFlags & ~(DerefBefore | DerefAfter | StackValue | EntryValue)) == 0 && "Unknown prepend flag");

Great suggestion, I've added the assert!

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

 #include "llvm/Support/Printable.h"
 #include <cassert>
 #include <cstdint>
 #include <functional>
 
 namespace llvm {
 
 class BitVector;
+class DIExpression;
 class LiveRegMatrix;
 class MachineFunction;
 class MachineInstr;
 class RegScavenger;
 class VirtRegMap;
 class LiveIntervals;
 class LiveInterval;
 
public:
 
   /// Determine whether a given base register plus offset immediate is
   /// encodable to resolve a frame index.
   virtual bool isFrameOffsetLegal(const MachineInstr *MI, Register BaseReg,
                                   int64_t Offset) const {
     llvm_unreachable("isFrameOffsetLegal does not exist on this target");
   }
 
+  /// Gets the DWARF expression opcodes for \p Offset.
+  virtual void getOffsetOpcodes(const StackOffset &Offset,
+                                SmallVectorImpl<uint64_t> &Ops) const;
+
+  /// Prepends a DWARF expression for \p Offset to DIExpression \p Expr.
+  DIExpression *
+  prependOffsetExpression(const DIExpression *Expr, unsigned PrependFlags,
+                          const StackOffset &Offset) const;
+
   /// Spill the register so it can be used by the register scavenger.
   /// Return true if the register was spilled, false otherwise.
   /// If this function does not spill the register, the scavenger
   /// will instead spill it to the emergency spill slot.
   virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator I,
                                      MachineBasicBlock::iterator &UseMI,
                                      const TargetRegisterClass *RC,

llvm/lib/CodeGen/PrologEpilogInserter.cpp

for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
         assert(i == 0 && "Frame indices can only appear as the first "
                          "operand of a DBG_VALUE machine instruction");
         Register Reg;
         unsigned FrameIdx = MI.getOperand(0).getIndex();
         unsigned Size = MF.getFrameInfo().getObjectSize(FrameIdx);
 
         StackOffset Offset =
             TFI->getFrameIndexReference(MF, FrameIdx, Reg);
-        assert(!Offset.getScalable() &&
-               "Frame offsets with a scalable component are not supported");
         MI.getOperand(0).ChangeToRegister(Reg, false /*isDef*/);
         MI.getOperand(0).setIsDebug();
 
         const DIExpression *DIExpr = MI.getDebugExpression();
 
         // If we have a direct DBG_VALUE, and its location expression isn't
         // currently complex, then adding an offset will morph it into a
         // complex location that is interpreted as being a memory address.
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
         // to be direct.
         if (MI.isIndirectDebugValue() && DIExpr->isImplicit()) {
           SmallVector<uint64_t, 2> Ops = {dwarf::DW_OP_deref_size, Size};
           bool WithStackValue = true;
           DIExpr = DIExpression::prependOpcodes(DIExpr, Ops, WithStackValue);
           // Make the DBG_VALUE direct.
           MI.getDebugOffset().ChangeToRegister(0, false);
         }
-        DIExpr = DIExpression::prepend(DIExpr, PrependFlags, Offset.getFixed());
+
+        DIExpr = TRI.prependOffsetExpression(DIExpr, PrependFlags, Offset);
         MI.getDebugExpressionOp().setMetadata(DIExpr);
         continue;
       }
 
       // TODO: This code should be commoned with the code for
       // PATCHPOINT. There's no good reason for the difference in
       // implementation other than historical accident.  The only
       // remaining difference is the unconditional use of the stack

llvm/lib/CodeGen/TargetRegisterInfo.cpp

 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/LiveInterval.h"
 #include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/CodeGen/VirtRegMap.h"
 #include "llvm/Config/llvm-config.h"
 #include "llvm/IR/Attributes.h"
+#include "llvm/IR/DebugInfoMetadata.h"
 #include "llvm/IR/Function.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/MachineValueType.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/Printable.h"
while (true) {
 
     if (!CopySrcReg.isVirtual())
       return CopySrcReg;
 
     SrcReg = CopySrcReg;
   }
 }
 
+void TargetRegisterInfo::getOffsetOpcodes(
+    const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {
+  assert(!Offset.getScalable() && "Scalable offsets are not handled");
+  int64_t ByteOffset = Offset.getFixed();
+  DIExpression::appendOffset(Ops, Offset.getFixed());
+}
+
+DIExpression *
+TargetRegisterInfo::prependOffsetExpression(const DIExpression *Expr,
+                                            unsigned PrependFlags,
+                                            const StackOffset &Offset) const {
+  assert((PrependFlags &
+          ~(DIExpression::DerefBefore | DIExpression::DerefAfter |
+            DIExpression::StackValue | DIExpression::EntryValue)) == 0 &&
+         "Unsupported prepend flag");
+  SmallVector<uint64_t, 16> OffsetExpr;
+  if (PrependFlags & DIExpression::DerefBefore)
+    OffsetExpr.push_back(dwarf::DW_OP_deref);
+  getOffsetOpcodes(Offset, OffsetExpr);
+  if (PrependFlags & DIExpression::DerefAfter)
+    OffsetExpr.push_back(dwarf::DW_OP_deref);
+  return DIExpression::prependOpcodes(Expr, OffsetExpr,
+                                      PrependFlags & DIExpression::StackValue,
+                                      PrependFlags & DIExpression::EntryValue);
+}
+
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 LLVM_DUMP_METHOD
 void TargetRegisterInfo::dumpReg(Register Reg, unsigned SubRegIndex,
                                  const TargetRegisterInfo *TRI) {
   dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n";
 }
 #endif

llvm/lib/Target/AArch64/AArch64RegisterInfo.h

public:
   unsigned getLocalAddressRegister(const MachineFunction &MF) const;
   bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const;
 
   /// SrcRC and DstRC will be morphed into NewRC if this returns true
   bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
                       unsigned SubReg, const TargetRegisterClass *DstRC,
                       unsigned DstSubReg, const TargetRegisterClass *NewRC,
                       LiveIntervals &LIS) const override;
+
+  void getOffsetOpcodes(const StackOffset &Offset,
+                        SmallVectorImpl<uint64_t> &Ops) const override;
 };
 
 } // end namespace llvm
 
 #endif

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

 #include "MCTargetDesc/AArch64AddressingModes.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/CodeGen/TargetFrameLowering.h"
+#include "llvm/IR/DebugInfoMetadata.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/IR/Function.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetOptions.h"
 
 using namespace llvm;
 
 #define GET_REGINFO_TARGET_DESC
if (MI.getOpcode() == AArch64::STGloop) {
     MI.setDesc(TII->get(AArch64::STZGloop_wback));
     return MI.getOperand(1).getReg();
   } else {
     return MI.getMF()->getRegInfo().createVirtualRegister(
         &AArch64::GPR64RegClass);
   }
 }
 
+void AArch64RegisterInfo::getOffsetOpcodes(
+    const StackOffset &Offset, SmallVectorImpl<uint64_t> &Ops) const {
+  // The smallest scalable element supported by scaled SVE addressing
+  // modes are predicates, which are 2 scalable bytes in size. So the scalable
+  // byte offset must always be a multiple of 2.
+  assert(Offset.getScalable() % 2 == 0 && "Invalid frame offset");
+
+  // Add fixed-sized offset using existing DIExpression interface.
+  DIExpression::appendOffset(Ops, Offset.getFixed());
+
+  unsigned VG = getDwarfRegNum(AArch64::VG, true);
+  int64_t VGSized = Offset.getScalable() / 2;
+  if (VGSized > 0) {
+    Ops.push_back(dwarf::DW_OP_constu);
+    Ops.push_back(VGSized);
+    Ops.append({dwarf::DW_OP_bregx, VG, 0ULL});
+    Ops.push_back(dwarf::DW_OP_mul);
+    Ops.push_back(dwarf::DW_OP_plus);
+  } else if (VGSized < 0) {
+    Ops.push_back(dwarf::DW_OP_constu);
+    Ops.push_back(-VGSized);
+    Ops.append({dwarf::DW_OP_bregx, VG, 0ULL});
+    Ops.push_back(dwarf::DW_OP_mul);
+    Ops.push_back(dwarf::DW_OP_minus);
+  }
+}
+
 void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
                                               int SPAdj, unsigned FIOperandNum,
                                               RegScavenger *RS) const {
   assert(SPAdj == 0 && "Unexpected");
 
   MachineInstr &MI = *II;
   MachineBasicBlock &MBB = *MI.getParent();
   MachineFunction &MF = *MBB.getParent();
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   const AArch64InstrInfo *TII =
       MF.getSubtarget<AArch64Subtarget>().getInstrInfo();
   const AArch64FrameLowering *TFI = getFrameLowering(MF);
 
   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
   bool Tagged =
       MI.getOperand(FIOperandNum).getTargetFlags() & AArch64II::MO_TAGGED;
   Register FrameReg;
 
   // Special handling of dbg_value, stackmap patchpoint statepoint instructions.
-  if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
+  if (MI.getOpcode() == TargetOpcode::STACKMAP ||
       MI.getOpcode() == TargetOpcode::PATCHPOINT ||
       MI.getOpcode() == TargetOpcode::STATEPOINT) {
     StackOffset Offset =
         TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
                                         /*PreferFP=*/true,
                                         /*ForSimm=*/false);
     Offset += StackOffset::getFixed(MI.getOperand(FIOperandNum + 1).getImm());
     MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);

llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir

+# RUN: llc -o %t -filetype=obj -start-before=prologepilog %s
+# RUN: llvm-dwarfdump --name="value0" %t | FileCheck %s --check-prefix=CHECK0
+# RUN: llvm-dwarfdump --name="value1" %t | FileCheck %s --check-prefix=CHECK1
+# RUN: llvm-dwarfdump --name="value2" %t | FileCheck %s --check-prefix=CHECK2
+# RUN: llvm-dwarfdump --name="value3" %t | FileCheck %s --check-prefix=CHECK3
+# RUN: llvm-dwarfdump --name="value4" %t | FileCheck %s --check-prefix=CHECK4
+# RUN: llvm-dwarfdump --name="value5" %t | FileCheck %s --check-prefix=CHECK5
+
+# CHECK0: : DW_OP_breg31 WSP+8, DW_OP_lit16, DW_OP_plus)
+# CHECK0: DW_AT_type {{.*}}ty32
+#
+# CHECK1: : DW_OP_breg31 WSP+16)
+# CHECK1: DW_AT_type {{.*}}ty32
+#
+# CHECK2: : DW_OP_breg31 WSP+16, DW_OP_lit16, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus)
+# CHECK2: DW_AT_type {{.*}}svint32_t
+#
+# CHECK3: : DW_OP_breg31 WSP+16, DW_OP_lit8, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus)
+# CHECK3: DW_AT_type {{.*}}svint32_t
+#
+# CHECK4: : DW_OP_breg31 WSP+16, DW_OP_lit7, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus)
+# CHECK4: DW_AT_type {{.*}}svbool_t
+#
+# CHECK5: : DW_OP_breg31 WSP+16, DW_OP_lit6, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus)
+# CHECK5: DW_AT_type {{.*}}svbool_t
+
+--- |
+  ; ModuleID = 'bla.mir'
+  source_filename = "bla.mir"
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+
+  define void @foo() #0 !dbg !5 {
+  entry:
+    unreachable, !dbg !8
+  }
+
+  ; Function Attrs: nounwind readnone speculatable willreturn
+  declare void @llvm.dbg.value(metadata, metadata, metadata)
+
+  attributes #0 = { "target-features"="+sve" }
+
+  !llvm.dbg.cu = !{!0}
+  !llvm.debugify = !{!3, !3}
+  !llvm.module.flags = !{!4}
+
+  !0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
+  !1 = !DIFile(filename: "bla.mir", directory: "/")
+  !2 = !{}
+  !3 = !{i32 1}
+  !4 = !{i32 2, !"Debug Info Version", i32 3}
+  !5 = distinct !DISubprogram(name: "foo", linkageName: "foo", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !9)
+  !6 = !DISubroutineType(types: !2)
+  !7 = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_signed)
+  !8 = !DILocation(line: 1, column: 1, scope: !5)
+  !9 = !{!10, !11, !12, !13, !14, !15}
+  !10 = !DILocalVariable(name: "value0", scope: !5, file: !1, line: 1, type: !7)
+  !11 = !DILocalVariable(name: "value1", scope: !5, file: !1, line: 1, type: !7)
+  !12 = !DILocalVariable(name: "value2", scope: !5, file: !1, line: 1, type: !16)
+  !13 = !DILocalVariable(name: "value3", scope: !5, file: !1, line: 1, type: !16)
+  !14 = !DILocalVariable(name: "value4", scope: !5, file: !1, line: 1, type: !21)
+  !15 = !DILocalVariable(name: "value5", scope: !5, file: !1, line: 1, type: !21)
+  !16 = !DIDerivedType(tag: DW_TAG_typedef, name: "svint32_t", file: !1, line: 1, baseType: !17)
+  !17 = !DIDerivedType(tag: DW_TAG_typedef, name: "__SVInt32_t", file: !1, baseType: !18)
+  !18 = !DICompositeType(tag: DW_TAG_array_type, baseType: !7, flags: DIFlagVector, elements: !19)
+  !19 = !{!20}
+  !20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 2, DW_OP_bregx, 46, 0, DW_OP_mul, DW_OP_constu, 1, DW_OP_minus))
+  !21 = !DIDerivedType(tag: DW_TAG_typedef, name: "svbool_t", file: !1, line: 90, baseType: !22)
+  !22 = !DIDerivedType(tag: DW_TAG_typedef, name: "__SVBool_t", file: !1, baseType: !23)
+  !23 = !DICompositeType(tag: DW_TAG_array_type, baseType: !24, flags: DIFlagVector, elements: !25)
+  !24 = !DIBasicType(name: "unsigned char", size: 8, encoding: DW_ATE_unsigned_char)
+  !25 = !{!26}
+  !26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 1, DW_OP_bregx, 46, 0, DW_OP_mul, DW_OP_constu, 1, DW_OP_minus))
+
+
+...
+---
+name:            foo
+alignment:       4
+tracksRegLiveness: true
+liveins:
+  - { reg: '$z0' }
+  - { reg: '$z1' }
+  - { reg: '$p0' }
+  - { reg: '$p1' }
+  - { reg: '$x0' }
+  - { reg: '$x1' }
+frameInfo:
+  maxAlignment:    16
+  adjustsStack:    true
+  hasCalls:        true
+  maxCallFrameSize: 0
+  localFrameSize:  4
+stack:
+  - { id: 0, size: 8,  alignment: 8 }
+  - { id: 1, size: 8,  alignment: 8 }
+  - { id: 2, size: 16, alignment: 16, stack-id: sve-vec }
+  - { id: 3, size: 16, alignment: 16, stack-id: sve-vec }
+  - { id: 4, size: 2,  alignment: 2,  stack-id: sve-vec }
+  - { id: 5, size: 2,  alignment: 2,  stack-id: sve-vec }
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    liveins: $p0, $p1, $w0, $x1, $z0, $z1
+
+    ; Avoid stack slot scavenging.
+    $lr = IMPLICIT_DEF
+
+    STRXui killed renamable $x0, %stack.0, 0, debug-location !8
+    DBG_VALUE %stack.0, $noreg, !10, !DIExpression(DW_OP_constu, 16, DW_OP_plus, DW_OP_deref), debug-location !8
+    STRXui killed renamable $x1, %stack.1, 0, debug-location !8
+    DBG_VALUE %stack.1, $noreg, !11, !DIExpression(DW_OP_constu, 16, DW_OP_plus, DW_OP_deref), debug-location !8
+
+    renamable $p2 = PTRUE_S 31, debug-location !DILocation(line: 4, column: 1, scope: !5)
+    ST1W_IMM renamable $z0, renamable $p2, %stack.2, 0, debug-location !DILocation(line: 5, column: 1, scope: !5)
+    DBG_VALUE %stack.2, $noreg, !12, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 5, column: 1, scope: !5)
+    ST1W_IMM renamable $z1, killed renamable $p2, %stack.3, 0, debug-location !DILocation(line: 6, column: 1, scope: !5)
+    DBG_VALUE %stack.3, $noreg, !13, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 6, column: 1, scope: !5)
+
+    STR_PXI killed renamable $p0, %stack.4, 0, debug-location !DILocation(line: 2, column: 1, scope: !5)
+    DBG_VALUE %stack.4, $noreg, !14, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 2, column: 1, scope: !5)
+    STR_PXI killed renamable $p1, %stack.5, 0, debug-location !DILocation(line: 3, column: 1, scope: !5)
+    DBG_VALUE %stack.5, $noreg, !15, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 3, column: 1, scope: !5)
+
+    RET_ReallyLR implicit $z0, implicit $z1, debug-location !DILocation(line: 7, column: 1, scope: !5)
+
+...