[RISCV] Add GHC calling convention

[schwab]

Summary

This is a special calling convention to be used by the GHC compiler.

[schwab]

This is used by https://gitlab.haskell.org/ghc/ghc/-/merge_requests/4327.

[jrtc27]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1968

i32 works too, as with the fast calling convention. That way you can support RV32.

(Though maybe both should be asserting if they ever see an i64 on RV32 given that's not a legal type? Or just leave it up to the general legalisation/verification stuff)

1969

Do you have an explanation somewhere for why you've chosen these X and F registers for the calling convention? It'd also be useful to give their RISC-V ABI names here in the comments as the numbered registers aren't so easy to keep track of mentally.

2001

Shouldn't this be a hard error? Otherwise it'll fall back on the normal C calling convention like for Fast, no?

llvm/test/CodeGen/RISCV/ghc-cc.ll

2–4

Please make this match the other tests in here, ie:

• match the llc invocation style
• test both rv32 and rv64
• use update_llc_test_checks.py

[lenary]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1964–2003

Is this doable with the declarative Calling Convention system in LLVM (an example of this is in llvm/lib/Target/ARM/ARMCallingConv.td)

We haven't been able to do this for RISC-V's normal calling convention yet, but this convention seems a lot simpler, so I hope it should be doable.

[jrtc27]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1964–2003

We deliberately went with C++ rather than TableGen for Fast, as it's far more readable (and flexible).

[schwab]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2001

This will error out in the caller CCState::AnalyzeCallOperands.

[schwab]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1969

I have just allocated the caller-saved registers in sequence s1 .. s11, fs0 .. fs11

[schwab]

llvm/test/CodeGen/RISCV/ghc-cc.ll

2–4

How can I parameterize the types on the triple?

[jrtc27]

llvm/test/CodeGen/RISCV/ghc-cc.ll

2–4

Hm right you'd need i32. We pipe things through sed in our fork to s/\<iXLEN\>/i64/ etc but I don't think the upstream update_llc_test_checks.py likes that (though maybe it does these days?). You'd have to duplicate the file otherwise as is done for calling-conv-ilp32.ll and calling-conv-lp64.ll.

[schwab]

Handle rv32 and testcase for rv32 added.

[jrtc27]

What happens if you try and use a soft-float or single-float ABI with ghccc? Will GHC know to use integer registers instead, or will this cause errors that mean we need to validate the ABI+CC combination?

llvm/test/CodeGen/RISCV/ghc-cc-rv32.ll

1 ↗

(On Diff #300488)

Please use "ghccc" rather than "ghc-cc" in the names of these files to match the calling convention name (as is done with the fastcc tests).

1–2 ↗

(On Diff #300488)

Please use update_llc_test_checks.py for these.

[schwab]

The --target-abi isn't actually needed, only -mattr=+f,+d.

[schwab]

More error checking added

[luismarques]

Overall, LGTM. Two things, though:

1. Please fix the < %s issue before committing, otherwise the test will fail.
2. Having a test for the error conditions would really round off this patch. I don't think that needs to be a blocker for merging this, but it would be nice.

llvm/test/CodeGen/RISCV/ghccc-rv32.ll

2 ↗

(On Diff #300499)

This is missing the < %s at the end of the llc command options.

[schwab]

Retested with typo fixed.

[schwab]

Could someone please commit this for me?

[StephenFan]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1964–2003

In the CallingConvLower.h, the CCAssignFn is a function pointer that represent the function that deal with the calling convention, and this function can be used in many other places, for example, In globalisel's ValueHandler. So I think use the TableGen rather than C++ is more convenient.

[jrtc27]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1964–2003

If GlobalISel can’t work with what’s already there then it needs to be fixed, because the current code is rather complex and won’t be being converted any time soon, and as a downstream consumer of the backend who extensively adds to the calling convention that would cause serious headache (and depending on how the rewriting is done may not even support our use case without additional downstream changes to TableGen, something that would be a real pain to do). IMO GlobalISel as a new framework needs to adapt to fit the existing backends unless there is a good reason why it fundamentally cannot.

[schwab]

Could someone please commit this for me?

[luismarques]

In D89788#2413440, @schwab wrote:

Could someone please commit this for me?

I'll commit it. Thank you.

[luismarques]

In D89788#2414855, @luismarques wrote:

I'll commit it. Thank you.

The reason for me reverting the patch and re-applying it is that I had originally committed it without proper attribution. Sorry about that.

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
   Register FPReg = getFPReg(STI);
   Register SPReg = getSPReg(STI);
   Register BPReg = RISCVABI::getBPReg();
 
   // Debug location must be unknown since the first debug location is used
   // to determine the end of the prologue.
   DebugLoc DL;
 
+  // All calls are tail calls in GHC calling conv, and functions have no
+  // prologue/epilogue.
+  if (MF.getFunction().getCallingConv() == CallingConv::GHC)
+    return;
+
   // Emit prologue for shadow call stack.
   emitSCSPrologue(MF, MBB, MBBI, DL);
 
   // Since spillCalleeSavedRegisters may have inserted a libcall, skip past
   // any instructions marked as FrameSetup
   while (MBBI != MBB.end() && MBBI->getFlag(MachineInstr::FrameSetup))
     ++MBBI;
 

 void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
                                       MachineBasicBlock &MBB) const {
   const RISCVRegisterInfo *RI = STI.getRegisterInfo();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
   Register FPReg = getFPReg(STI);
   Register SPReg = getSPReg(STI);
 
+  // All calls are tail calls in GHC calling conv, and functions have no
+  // prologue/epilogue.
+  if (MF.getFunction().getCallingConv() == CallingConv::GHC)
+    return;
+
   // Get the insert location for the epilogue. If there were no terminators in
   // the block, get the last instruction.
   MachineBasicBlock::iterator MBBI = MBB.end();
   DebugLoc DL;
   if (!MBB.empty()) {
     MBBI = MBB.getFirstTerminator();
     if (MBBI == MBB.end())
       MBBI = MBB.getLastNonDebugInstr();

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op,
   SDLoc DL(Op);
   EVT Ty = Op.getValueType();
   GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
   int64_t Offset = N->getOffset();
   MVT XLenVT = Subtarget.getXLenVT();
 
   TLSModel::Model Model = getTargetMachine().getTLSModel(N->getGlobal());
 
+  if (DAG.getMachineFunction().getFunction().getCallingConv() ==
+      CallingConv::GHC)
+    report_fatal_error("In GHC calling convention TLS is not supported");
+
   SDValue Addr;
   switch (Model) {
   case TLSModel::LocalExec:
     Addr = getStaticTLSAddr(N, DAG, /*UseGOT=*/false);
     break;
   case TLSModel::InitialExec:
     Addr = getStaticTLSAddr(N, DAG, /*UseGOT=*/true);
     break;
if (LocVT == MVT::i64 || LocVT == MVT::f64) {
     unsigned Offset5 = State.AllocateStack(8, Align(8));
     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo));
     return false;
   }
 
   return true; // CC didn't match.
 }
 
+static bool CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
+       CCValAssign::LocInfo LocInfo,
+       ISD::ArgFlagsTy ArgFlags, CCState &State) {
+
+  if (LocVT == MVT::i64) {
+    // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, R7, SpLim
+    static const MCPhysReg GPRList[] = {
+      RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20,
+      RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24,
+      RISCV::X25, RISCV::X26, RISCV::X27};
+    if (unsigned Reg = State.AllocateReg(GPRList)) {
+      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+      return false;
+    }
+  }
+
+  if (LocVT == MVT::f32) {
+    // Pass in STG registers: F1, ..., F6
+    static const MCPhysReg FPR32List[] = {
+      RISCV::F8_F, RISCV::F9_F, RISCV::F18_F, RISCV::F19_F, RISCV::F20_F,
+      RISCV::F21_F};
+    if (unsigned Reg = State.AllocateReg(FPR32List)) {
+      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+      return false;
+    }
+  }
+
+  if (LocVT == MVT::f64) {
+    // Pass in STG registers: D1, ..., D6
+    static const MCPhysReg FPR64List[] = {
+      RISCV::F22_D, RISCV::F23_D, RISCV::F24_D, RISCV::F25_D, RISCV::F26_D,
+      RISCV::F27_D};
+    if (unsigned Reg = State.AllocateReg(FPR64List)) {
+      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
+      return false;
+    }
+  }
+
+  return true; // CC didn't match.
+}
+
 // Transform physical registers into virtual registers.
 SDValue RISCVTargetLowering::LowerFormalArguments(
     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
 
   switch (CallConv) {
   default:
     report_fatal_error("Unsupported calling convention");
   case CallingConv::C:
   case CallingConv::Fast:
+  case CallingConv::GHC:
     break;
   }
 
   MachineFunction &MF = DAG.getMachineFunction();
 
   const Function &Func = MF.getFunction();
   if (Func.hasFnAttribute("interrupt")) {
     if (!Func.arg_empty())
SDValue RISCVTargetLowering::LowerFormalArguments(
   std::vector<SDValue> OutChains;
 
   // Assign locations to all of the incoming arguments.
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
 
   if (CallConv == CallingConv::Fast)
     CCInfo.AnalyzeFormalArguments(Ins, CC_RISCV_FastCC);
+  else if (CallConv == CallingConv::GHC)
+    CCInfo.AnalyzeFormalArguments(Ins, CC_RISCV_GHC);
   else
     analyzeInputArgs(MF, CCInfo, Ins, /*IsRet=*/false);
 
   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
     CCValAssign &VA = ArgLocs[i];
     SDValue ArgValue;
     // Passing f64 on RV32D with a soft float ABI must be handled as a special
     // case.
SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
   MachineFunction &MF = DAG.getMachineFunction();
 
   // Analyze the operands of the call, assigning locations to each operand.
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
 
   if (CallConv == CallingConv::Fast)
     ArgCCInfo.AnalyzeCallOperands(Outs, CC_RISCV_FastCC);
+  else if (CallConv == CallingConv::GHC)
+    ArgCCInfo.AnalyzeCallOperands(Outs, CC_RISCV_GHC);
   else
     analyzeOutputArgs(MF, ArgCCInfo, Outs, /*IsRet=*/false, &CLI);
 
   // Check if it's really possible to do a tail call.
   if (IsTailCall)
     IsTailCall = isEligibleForTailCallOptimization(ArgCCInfo, CLI, MF, ArgLocs);
 
   if (IsTailCall)
RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
 
   // Info about the registers and stack slot.
   CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
                  *DAG.getContext());
 
   analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs, /*IsRet=*/true,
                     nullptr);
 
+  if (CallConv == CallingConv::GHC && !RVLocs.empty())
+    report_fatal_error("GHC functions return void only");
+
   SDValue Glue;
   SmallVector<SDValue, 4> RetOps(1, Chain);
 
   // Copy the result values into the output registers.
   for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) {
     SDValue Val = OutVals[i];
     CCValAssign &VA = RVLocs[i];
     assert(VA.isRegLoc() && "Can only return in registers!");

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

 
 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
     : RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
                            /*PC*/0, HwMode) {}
 
 const MCPhysReg *
 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
+  if (MF->getFunction().getCallingConv() == CallingConv::GHC)
+    return CSR_NoRegs_SaveList;
   if (MF->getFunction().hasFnAttribute("interrupt")) {
     if (Subtarget.hasStdExtD())
       return CSR_XLEN_F64_Interrupt_SaveList;
     if (Subtarget.hasStdExtF())
       return CSR_XLEN_F32_Interrupt_SaveList;
     return CSR_Interrupt_SaveList;
   }
 

 }
 
 Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   const TargetFrameLowering *TFI = getFrameLowering(MF);
   return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
 }
 
 const uint32_t *
 RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
-                                        CallingConv::ID /*CC*/) const {
+                                        CallingConv::ID CC) const {
   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
 
+  if (CC == CallingConv::GHC)
+    return CSR_NoRegs_RegMask;
   switch (Subtarget.getTargetABI()) {
   default:
     llvm_unreachable("Unrecognized ABI");
   case RISCVABI::ABI_ILP32:
   case RISCVABI::ABI_LP64:
     return CSR_ILP32_LP64_RegMask;
   case RISCVABI::ABI_ILP32F:
   case RISCVABI::ABI_LP64F:
     return CSR_ILP32F_LP64F_RegMask;
   case RISCVABI::ABI_ILP32D:
   case RISCVABI::ABI_LP64D:
     return CSR_ILP32D_LP64D_RegMask;
   }
 }

llvm/test/CodeGen/RISCV/ghc-cc.ll

+; RUN: llc -mtriple=riscv64-unknown-linux-gnu -mattr=+f,+d \
+; RUN:   --target-abi lp64d < %s \
+; RUN:   | FileCheck %s
+
+; Check the GHC call convention works (riscv64)
+
+@base  = external global i64 ; assigned to register: s1
+@sp    = external global i64 ; assigned to register: s2
+@hp    = external global i64 ; assigned to register: s3
+@r1    = external global i64 ; assigned to register: s4
+@r2    = external global i64 ; assigned to register: s5
+@r3    = external global i64 ; assigned to register: s6
+@r4    = external global i64 ; assigned to register: s7
+@r5    = external global i64 ; assigned to register: s8
+@r6    = external global i64 ; assigned to register: s9
+@r7    = external global i64 ; assigned to register: s10
+@splim = external global i64 ; assigned to register: s11
+
+@f1 = external global float  ; assigned to register: fs0
+@f2 = external global float  ; assigned to register: fs1
+@f3 = external global float  ; assigned to register: fs2
+@f4 = external global float  ; assigned to register: fs3
+@f5 = external global float  ; assigned to register: fs4
+@f6 = external global float  ; assigned to register: fs5
+
+@d1 = external global double ; assigned to register: fs6
+@d2 = external global double ; assigned to register: fs7
+@d3 = external global double ; assigned to register: fs8
+@d4 = external global double ; assigned to register: fs9
+@d5 = external global double ; assigned to register: fs10
+@d6 = external global double ; assigned to register: fs11
+
+define ghccc void @foo() nounwind {
+entry:
+  ; CHECK:      lui     {{a[0-9]}}, %hi(d6)
+  ; CHECK-NEXT: fld     fs11, %lo(d6)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(d5)
+  ; CHECK-NEXT: fld     fs10, %lo(d5)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(d4)
+  ; CHECK-NEXT: fld     fs9, %lo(d4)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(d3)
+  ; CHECK-NEXT: fld     fs8, %lo(d3)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(d2)
+  ; CHECK-NEXT: fld     fs7, %lo(d2)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(d1)
+  ; CHECK-NEXT: fld     fs6, %lo(d1)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(f6)
+  ; CHECK-NEXT: flw     fs5, %lo(f6)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(f5)
+  ; CHECK-NEXT: flw     fs4, %lo(f5)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(f4)
+  ; CHECK-NEXT: flw     fs3, %lo(f4)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(f3)
+  ; CHECK-NEXT: flw     fs2, %lo(f3)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(f2)
+  ; CHECK-NEXT: flw     fs1, %lo(f2)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(f1)
+  ; CHECK-NEXT: flw     fs0, %lo(f1)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(splim)
+  ; CHECK-NEXT: ld      s11, %lo(splim)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(r7)
+  ; CHECK-NEXT: ld      s10, %lo(r7)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(r6)
+  ; CHECK-NEXT: ld      s9, %lo(r6)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(r5)
+  ; CHECK-NEXT: ld      s8, %lo(r5)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(r4)
+  ; CHECK-NEXT: ld      s7, %lo(r4)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(r3)
+  ; CHECK-NEXT: ld      s6, %lo(r3)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(r2)
+  ; CHECK-NEXT: ld      s5, %lo(r2)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(r1)
+  ; CHECK-NEXT: ld      s4, %lo(r1)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(hp)
+  ; CHECK-NEXT: ld      s3, %lo(hp)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(sp)
+  ; CHECK-NEXT: ld      s2, %lo(sp)({{a[0-9]}})
+  ; CHECK-NEXT: lui     {{a[0-9]}}, %hi(base)
+  ; CHECK-NEXT: ld      s1, %lo(base)({{a[0-9]}})
+  %0  = load double, double* @d6
+  %1  = load double, double* @d5
+  %2  = load double, double* @d4
+  %3  = load double, double* @d3
+  %4  = load double, double* @d2
+  %5  = load double, double* @d1
+  %6  = load float, float* @f6
+  %7  = load float, float* @f5
+  %8  = load float, float* @f4
+  %9  = load float, float* @f3
+  %10 = load float, float* @f2
+  %11 = load float, float* @f1
+  %12 = load i64, i64* @splim
+  %13 = load i64, i64* @r7
+  %14 = load i64, i64* @r6
+  %15 = load i64, i64* @r5
+  %16 = load i64, i64* @r4
+  %17 = load i64, i64* @r3
+  %18 = load i64, i64* @r2
+  %19 = load i64, i64* @r1
+  %20 = load i64, i64* @hp
+  %21 = load i64, i64* @sp
+  %22 = load i64, i64* @base
+  ; CHECK: tail bar
+  tail call ghccc void @bar(i64 %22, i64 %21, i64 %20, i64 %19, i64 %18, i64 %17, i64 %16, i64 %15, i64 %14, i64 %13, i64 %12,
+                            float %11, float %10, float %9, float %8, float %7, float %6,
+                            double %5, double %4, double %3, double %2, double %1, double %0) nounwind
+  ret void
+}
+
+declare ghccc void @bar(i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64,
+                        float, float, float, float, float, float,
+                        double, double, double, double, double, double)