Excluding landing pads, a register that's live-in should be live-out of each of its predecessors. Expand the check for this to include allocatable registers, and registers with aliases.
We do a relatively relaxed check for registers with aliases: some register that aliases the register in question must be live-out of each predecessor. In some cases, it might make sense to try to do something more strict, but this is enough to catch a lot of interesting cases.
Currently guarded by a flag because a bunch of targets have at least one regression test failure with this and expensive checks enabled. In particular, there are failures for AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISC-V, SystemZ, and X86. I'd appreciate if people working with those targets would look into this.
SystemZ only fails on one MIR test, and I think that's a bug in the test, not the backend. The other backends appear to have at least one real bug.
There's a cluster of failures involving code failing to compute live-ins correctly when expanding atomic pseudo-instructions. This affects the ARM, Mips, and RISC-V backend. Might make sense to address them together, even though the code is separate.
For x86, one of the failing tests involves callbr; maybe related to D75098?
Complete list of failures, for reference:
Failing Tests (66):
LLVM :: CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir LLVM :: CodeGen/AMDGPU/constant-fold-imm-immreg.mir LLVM :: CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll LLVM :: CodeGen/AMDGPU/fold-immediate-operand-shrink.mir LLVM :: CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir LLVM :: CodeGen/AMDGPU/global_smrd_cfg.ll LLVM :: CodeGen/ARM/cmpxchg-O0.ll LLVM :: CodeGen/ARM/cmse-expand-bxns-ret.mir LLVM :: CodeGen/Hexagon/Atomics.ll LLVM :: CodeGen/Hexagon/aggr-licm.ll LLVM :: CodeGen/Hexagon/bit-extract-off.ll LLVM :: CodeGen/Hexagon/check-subregister-for-latency.ll LLVM :: CodeGen/Hexagon/concat-vectors-legalize.ll LLVM :: CodeGen/Hexagon/deflate.ll LLVM :: CodeGen/Hexagon/frame-offset-overflow.ll LLVM :: CodeGen/Hexagon/i128-bitop.ll LLVM :: CodeGen/Hexagon/packetize-impdef-1.ll LLVM :: CodeGen/Hexagon/reg-scav-imp-use-dbl-vec.ll LLVM :: CodeGen/Hexagon/reg-scavengebug-2.ll LLVM :: CodeGen/Hexagon/reg-scavengebug-4.ll LLVM :: CodeGen/Hexagon/swp-conv3x3-nested.ll LLVM :: CodeGen/Hexagon/swp-epilog-phi6.ll LLVM :: CodeGen/Hexagon/swp-epilog-phi7.ll LLVM :: CodeGen/Hexagon/swp-order-carried.ll LLVM :: CodeGen/Hexagon/swp-order-deps6.ll LLVM :: CodeGen/Hexagon/swp-reuse-phi-4.ll LLVM :: CodeGen/Hexagon/swp-reuse-phi-6.ll LLVM :: CodeGen/Hexagon/swp-sigma.ll LLVM :: CodeGen/Hexagon/v6-spill1.ll LLVM :: CodeGen/Hexagon/v60-vecpred-spill.ll LLVM :: CodeGen/Hexagon/v60Vasr.ll LLVM :: CodeGen/Hexagon/vect-regpairs.ll LLVM :: CodeGen/Hexagon/vect/vect-cst-v4i8.ll LLVM :: CodeGen/Hexagon/vect/vect-cst.ll LLVM :: CodeGen/Hexagon/vect/vect-vsplatb.ll LLVM :: CodeGen/Hexagon/vect/vect-xor.ll LLVM :: CodeGen/Hexagon/vmpa-halide-test.ll LLVM :: CodeGen/Mips/atomic-min-max.ll LLVM :: CodeGen/Mips/atomic.ll LLVM :: CodeGen/Mips/atomic64.ll LLVM :: CodeGen/Mips/atomicCmpSwapPW.ll LLVM :: CodeGen/Mips/micromips-atomic1.ll LLVM :: CodeGen/PowerPC/ctrloop-sums.ll LLVM :: CodeGen/PowerPC/ppcf128-freeze.mir LLVM :: CodeGen/PowerPC/select-i1-vs-i1.ll LLVM :: CodeGen/RISCV/atomic-cmpxchg-flag.ll LLVM :: CodeGen/RISCV/atomic-cmpxchg.ll LLVM :: CodeGen/RISCV/atomic-rmw.ll LLVM :: CodeGen/RISCV/shrinkwrap.ll LLVM :: CodeGen/Thumb/thumb-shrink-wrapping.ll LLVM :: CodeGen/Thumb2/LowOverheadLoops/vpt-blocks.mir LLVM :: CodeGen/X86/2009-07-15-CoalescerBug.ll LLVM :: CodeGen/X86/block-placement.mir LLVM :: CodeGen/X86/callbr-asm-outputs.ll LLVM :: CodeGen/X86/cfi-inserter-callee-save-register-2.mir LLVM :: CodeGen/X86/dbg-changes-codegen-branch-folding2.mir LLVM :: CodeGen/X86/icall-branch-funnel.ll LLVM :: CodeGen/X86/implicit-null-checks.mir LLVM :: CodeGen/X86/implicit-null-chk-reg-rewrite.mir LLVM :: CodeGen/X86/leaFixup32.mir LLVM :: CodeGen/X86/leaFixup64.mir LLVM :: CodeGen/X86/pr38952.mir LLVM :: CodeGen/X86/win_coreclr_chkstk_liveins.mir LLVM :: DebugInfo/MIR/ARM/subregister-full-piece.mir LLVM :: DebugInfo/MIR/X86/live-debug-values-reg-copy.mir LLVM :: DebugInfo/X86/live-debug-values-constprop.mir