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[RISCV] Add Clang Builtins for Accessing CSRs
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Authored by lenary on Dec 20 2019, 11:00 AM.



As of clang 9.0, the only way to access the RISC-V Control and Status Registers
is to use inline assembly, which is ugly and hinders optimisations.

This patch adds some Clang Builtins and LLVM Intrinsics to allow programmers
to access the CSRs without using inline assembly, which should therefore be

I hope to build a slightly nicer interface to this, to support the read-only or
write-only CSR operations (akin to the csrr, csrw, csrs and csrc
pseudo-instructions) via these builtins, which will eventually be available via

Event Timeline

lenary created this revision.Dec 20 2019, 11:00 AM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptDec 20 2019, 11:00 AM
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