[RISCV] Add RISCV-specific TargetTransformInfo

[lenary]

Summary

LLVM Allows Targets to provide information that guides optimisations
made to LLVM IR. This is done with callbacks on a TargetTransformInfo object.

This patch adds a TargetTransformInfo class for RISC-V. This will allow us to
implement RISC-V specific callbacks as they become necessary.

This commit also adds the getIntImmCost callbacks, and tests them with a simple
constant hoisting test.

[asb]

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

17

Don't you want to implement this in terms of getIntMatCost, as you introduced in D62857?

[lenary]

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

17

I felt that was:

• less clear;
• less easy to customise, for other LLVM IR instructions with constant arguments that might mean other things; and
• obscured the fact that getIntImmCost is an estimate, where the code that uses the result has fairly specific "thresholds" that trigger optimisation behaviour.

I felt these three points outweighed the abstraction benefits of calling getIntMatCost.

[MaskRay]

llvm/test/Transforms/ConstantHoisting/RISCV/lit.local.cfg

3

Delete the empty line... No need to copy it from X86 :)

[lenary]

• Address review feedback

[lenary]

I attempted to update this diff, but with a rebased branch arc didn't cope. Starting again.

llvm/lib/Target/RISCV/CMakeLists.txt

add_llvm_target(RISCVCodeGen
   RISCVISelDAGToDAG.cpp
   RISCVISelLowering.cpp
   RISCVMCInstLower.cpp
   RISCVMergeBaseOffset.cpp
   RISCVRegisterInfo.cpp
   RISCVSubtarget.cpp
   RISCVTargetMachine.cpp
   RISCVTargetObjectFile.cpp
+  RISCVTargetTransformInfo.cpp
   )
 
 add_subdirectory(AsmParser)
 add_subdirectory(Disassembler)
 add_subdirectory(MCTargetDesc)
 add_subdirectory(TargetInfo)
 add_subdirectory(Utils)

llvm/lib/Target/RISCV/LLVMBuild.txt

 has_asmparser = 1
 has_asmprinter = 1
 has_disassembler = 1
 
 [component_1]
 type = Library
 name = RISCVCodeGen
 parent = RISCV
-required_libraries = AsmPrinter Core CodeGen MC RISCVDesc
+required_libraries = Analysis AsmPrinter Core CodeGen MC RISCVDesc
   RISCVInfo RISCVUtils SelectionDAG Support Target
 add_to_library_groups = RISCV

llvm/lib/Target/RISCV/RISCVTargetMachine.h

const RISCVSubtarget *getSubtargetImpl(const Function &) const override {
     return &Subtarget;
   }
 
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
   TargetLoweringObjectFile *getObjFileLowering() const override {
     return TLOF.get();
   }
+
+  TargetTransformInfo getTargetTransformInfo(const Function &F) override;
 };
 }
 
 #endif

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

 //===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // Implements the info about RISCV target spec.
 //
 //===----------------------------------------------------------------------===//
 
-#include "RISCV.h"
 #include "RISCVTargetMachine.h"
+#include "RISCV.h"
 #include "RISCVTargetObjectFile.h"
+#include "RISCVTargetTransformInfo.h"
 #include "TargetInfo/RISCVTargetInfo.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/LegacyPassManager.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Target/TargetOptions.h"
 using namespace llvm;
RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
                         getEffectiveRelocModel(TT, RM),
                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
       TLOF(make_unique<RISCVELFTargetObjectFile>()),
       Subtarget(TT, CPU, FS, Options.MCOptions.getABIName(), *this) {
   initAsmInfo();
 }
 
+TargetTransformInfo
+RISCVTargetMachine::getTargetTransformInfo(const Function &F) {
+  return TargetTransformInfo(RISCVTTIImpl(this, F));
+}
+
 namespace {
 class RISCVPassConfig : public TargetPassConfig {
 public:
   RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
       : TargetPassConfig(TM, PM) {}
 
   RISCVTargetMachine &getRISCVTargetMachine() const {
     return getTM<RISCVTargetMachine>();

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

+//===- RISCVTargetTransformInfo.h - RISC-V specific TTI ---------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+/// This file a TargetTransformInfo::Concept conforming object specific to the
+/// RISC-V target machine. It uses the target's detailed information to
+/// provide more precise answers to certain TTI queries, while letting the
+/// target independent and default TTI implementations handle the rest.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H
+#define LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H
+
+#include "RISCVSubtarget.h"
+#include "RISCVTargetMachine.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/CodeGen/BasicTTIImpl.h"
+#include "llvm/IR/Function.h"
+
+namespace llvm {
+
+class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
+  using BaseT = BasicTTIImplBase<RISCVTTIImpl>;
+  using TTI = TargetTransformInfo;
+
+  friend BaseT;
+
+  const RISCVSubtarget *ST;
+  const RISCVTargetLowering *TLI;
+
+  const RISCVSubtarget *getST() const { return ST; }
+  const RISCVTargetLowering *getTLI() const { return TLI; }
+
+public:
+  explicit RISCVTTIImpl(const RISCVTargetMachine *TM, const Function &F)
+      : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
+        TLI(ST->getTargetLowering()) {}
+
+  using BaseT::getIntImmCost;
+  int getIntImmCost(int64_t Val);
+  int getIntImmCost(const APInt &Imm, Type *Ty);
+  int getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty);
+  int getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
+                    Type *Ty);
+};
+
+} // end namespace llvm
+
+#endif // LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H
 No newline at end of file

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

+//===-- RISCVTargetTransformInfo.cpp - RISC-V specific TTI ----------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "RISCVTargetTransformInfo.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
+#include "llvm/CodeGen/BasicTTIImpl.h"
+#include "llvm/CodeGen/TargetLowering.h"
+using namespace llvm;
+
+#define DEBUG_TYPE "riscvtti"
+
+int RISCVTTIImpl::getIntImmCost(int64_t Val) {
+  if (Val == 0)
+    return TTI::TCC_Free;
+
+  if (getTLI()->isLegalAddImmediate(Val))
+    return TTI::TCC_Free;
+
+  if (isInt<32>(Val))
+    return TTI::TCC_Basic;
+
+  return TTI::TCC_Expensive;
+}
+
+int RISCVTTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
+  assert(Ty->isIntegerTy());
+
+  return getIntImmCost(Imm.getSExtValue());
+}
+
+int RISCVTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
+                                Type *Ty) {
+  return getIntImmCost(Imm, Ty);
+}
+
+int RISCVTTIImpl::getIntImmCost(Intrinsic::ID IID, unsigned Idx,
+                                const APInt &Imm, Type *Ty) {
+  return getIntImmCost(Imm, Ty);
+}

llvm/test/Transforms/ConstantHoisting/RISCV/immediates.ll

+; RUN: opt -mtriple=riscv32-unknown-elf -S -consthoist < %s | FileCheck %s
+; RUN: opt -mtriple=riscv64-unknown-elf -S -consthoist < %s | FileCheck %s
+
+; Check that we don't hoist immediates with small values.
+define i64 @test1(i64 %a) nounwind {
+; CHECK-LABEL: test1
+; CHECK-NOT: %const = bitcast i64 2 to i64
+  %1 = mul i64 %a, 2
+  %2 = add i64 %1, 2
+  ret i64 %2
+}
+
+; Check that we don't hoist immediates with small values.
+define i64 @test2(i64 %a) nounwind {
+; CHECK-LABEL: test2
+; CHECK-NOT: %const = bitcast i64 2047 to i64
+  %1 = mul i64 %a, 2047
+  %2 = add i64 %1, 2047
+  ret i64 %2
+}
+
+; Check that we don't hoist immediates with large values.
+define i64 @test3(i64 %a) nounwind {
+; CHECK-LABEL: test3
+; CHECK-NOT: %const = bitcast i64 2147483647 to i64
+  %1 = mul i64 %a, 2147483647
+  %2 = add i64 %1, 2147483647
+  ret i64 %2
+}
+
+; Check that we hoist immediates with huge values
+define i64 @test4(i64 %a) nounwind {
+; CHECK-LABEL: test4
+; CHECK: %const = bitcast i64 2147483648 to i64
+  %1 = mul i64 %a, 2147483648
+  %2 = add i64 %1, 2147483648
+  ret i64 %2
+}
 No newline at end of file

llvm/test/Transforms/ConstantHoisting/RISCV/lit.local.cfg

+if not 'RISCV' in config.root.targets:
+    config.unsupported = True
+