[ARM] Add a batch of MVE integer instructions.

[simon_tatham]

Summary

This includes integer arithmetic of various kinds (add/sub/multiply,
saturating and not), and the VMOVs that load an immediate into all
lanes of a vector.

[simon_tatham]

Remastered patch to apply cleanly against current trunk.

[simon_tatham]

Updated to current trunk, and renamed instruction ids in line with new
consistent MVE_ prefix.

[ostannard]

llvm/lib/Target/ARM/ARMInstrMVE.td

1669

Bit 28 could be a parameter of MVE_VQxDMULH, and this could be a multiclass to avoid repetition of the types below. (Common pattern in this file).

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

3463

What does this mean?

llvm/test/MC/ARM/mve-integer.s

9

We should also test that invalid immediates are rejected.

llvm/test/MC/Disassembler/ARM/mve-integer.txt

6

Should these instructions have CHECK-NOMVE lines?

33

These ERROR check lines aren't used by and RUN lines.

[simon_tatham]

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

3463

Looks as if it was left in from some preliminary work in which the author wasn't sure what further range of instructions that decoder function would end up applying to. I'll take it out.

[simon_tatham]

Addressed all review comments. In particular, completely removed the mve.fp test run from the mve-integer.s test file, because it was only there due to copy and paste error (I split all these tests out of one far-too-big input file with a single set of run commands).

[simon_tatham]

Added the integer VMINA / VMAXA instructions to this patch, which were
mistakenly included in D62677 despite not being derived from the
latter patch's shared base class.

[ostannard]

LGTM

llvm/lib/Target/ARM/ARMInstrMVE.td

 def VMOVt132 : VMOVt1regtovec<"32", 0b0, (ins MVEVectorIndex32:$Idx)> {
   let Inst{22} = 0b0;
   let Inst{6-5} = 0b00;
   let Predicates = [HasFPRegsV8_1M];
 }
 
 // end of mve_bit instructions
 
+// start of MVE Integer instructions
+
+class MVE_int<string iname, string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), NoItinerary,
+          iname, suffix, "$Qd, $Qn, $Qm", vpred_r, "", pattern> {
+  bits<4> Qd;
+  bits<4> Qn;
+  bits<4> Qm;
+
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = size;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{7} = Qn{3};
+  let Inst{6} = 0b1;
+  let Inst{5} = Qm{3};
+  let Inst{3-1} = Qm{2-0};
+}
+
+class VMULt1<string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_int<"vmul", suffix, size, pattern> {
+
+  let Inst{28} = 0b0;
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-8} = 0b01001;
+  let Inst{4} = 0b1;
+  let Inst{0} = 0b0;
+}
+
+def VMULt1i8  : VMULt1<"i8", 0b00>;
+def VMULt1i16 : VMULt1<"i16", 0b01>;
+def VMULt1i32 : VMULt1<"i32", 0b10>;
+
+class VQDMULH<string iname, string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_int<iname, suffix, size, pattern> {
+
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-8} = 0b01011;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+class VQDMULHt1<string suffix, bits<2> size, list<dag> pattern=[]>
+  : VQDMULH<"vqdmulh", suffix, size, pattern> {
+  let Inst{28} = 0b0;
+}
+
+class VQDMULHt2<string suffix, bits<2> size, list<dag> pattern=[]>
+  : VQDMULH<"vqrdmulh", suffix, size, pattern> {
+  let Inst{28} = 0b1;
+}
+
+def VQDMULHt1i8  : VQDMULHt1<"s8", 0b00>;
+def VQDMULHt1i16 : VQDMULHt1<"s16", 0b01>;
+def VQDMULHt1i32 : VQDMULHt1<"s32", 0b10>;
+
+def VQRDMULHt2i8  : VQDMULHt2<"s8", 0b00>;
+def VQRDMULHt2i16 : VQDMULHt2<"s16", 0b01>;
+def VQRDMULHt2i32 : VQDMULHt2<"s32", 0b10>;
+
+class VADDSUBt1<string iname, string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_int<iname, suffix, size, pattern> {
+
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-8} = 0b01000;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+class VSUBt1<string suffix, bits<2> size, list<dag> pattern=[]>
+  : VADDSUBt1<"vsub", suffix, size, pattern> {
+  let Inst{28} = 0b1;
+}
+
+class VADDt1<string suffix, bits<2> size, list<dag> pattern=[]>
+  : VADDSUBt1<"vadd", suffix, size, pattern> {
+  let Inst{28} = 0b0;
+}
+
+def VSUBt1i8  : VSUBt1<"i8", 0b00>;
+def VSUBt1i16 : VSUBt1<"i16", 0b01>;
+def VSUBt1i32 : VSUBt1<"i32", 0b10>;
+
+def VADDt1i8  : VADDt1<"i8", 0b00>;
+def VADDt1i16 : VADDt1<"i16", 0b01>;
+def VADDt1i32 : VADDt1<"i32", 0b10>;
+
+class VQADDVQSUBt1<string iname, string suffix, bit U, bits<2> size,
+                  list<dag> pattern=[]>
+  : MVE_int<iname, suffix, size, pattern> {
+
+  let Inst{28} = U;
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-10} = 0b000;
+  let Inst{8} = 0b0;
+  let Inst{4} = 0b1;
+  let Inst{0} = 0b0;
+}
+
+class VQSUBt1<string suffix, bit U, bits<2> size,
+              list<dag> pattern=[]>
+  : VQADDVQSUBt1<"vqsub", suffix, U, size, pattern> {
+  let Inst{9} = 0b1;
+}
+
+class VQADDt1<string suffix, bit U, bits<2> size,
+              list<dag> pattern=[]>
+  : VQADDVQSUBt1<"vqadd", suffix, U, size, pattern> {
+  let Inst{9} = 0b0;
+}
+def VQSUBt1s8  : VQSUBt1<"s8", 0b0, 0b00>;
+def VQSUBt1s16 : VQSUBt1<"s16", 0b0, 0b01>;
+def VQSUBt1s32 : VQSUBt1<"s32", 0b0, 0b10>;
+def VQSUBt1u8  : VQSUBt1<"u8", 0b1, 0b00>;
+def VQSUBt1u16 : VQSUBt1<"u16", 0b1, 0b01>;
+def VQSUBt1u32 : VQSUBt1<"u32", 0b1, 0b10>;
+
+def VQADDt1s8  : VQADDt1<"s8", 0b0, 0b00>;
+def VQADDt1s16 : VQADDt1<"s16", 0b0, 0b01>;
+def VQADDt1s32 : VQADDt1<"s32", 0b0, 0b10>;
+def VQADDt1u8  : VQADDt1<"u8", 0b1, 0b00>;
+def VQADDt1u16 : VQADDt1<"u16", 0b1, 0b01>;
+def VQADDt1u32 : VQADDt1<"u32", 0b1, 0b10>;
+
+class VABDt1<string suffix, bit U, bits<2> size,
+           list<dag> pattern=[]>
+  : MVE_int<"vabd", suffix, size, pattern> {
+
+  let Inst{28} = U;
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-8} = 0b00111;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def VABDt1s8  : VABDt1<"s8", 0b0, 0b00>;
+def VABDt1s16 : VABDt1<"s16", 0b0, 0b01>;
+def VABDt1s32 : VABDt1<"s32", 0b0, 0b10>;
+def VABDt1u8  : VABDt1<"u8", 0b1, 0b00>;
+def VABDt1u16 : VABDt1<"u16", 0b1, 0b01>;
+def VABDt1u32 : VABDt1<"u32", 0b1, 0b10>;
+
+class VRHADDt1<string suffix, bit U, bits<2> size,
+               list<dag> pattern=[]>
+  : MVE_int<"vrhadd", suffix, size, pattern> {
+
+  let Inst{28} = U;
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-8} = 0b00001;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def VRHADDt1s8  : VRHADDt1<"s8", 0b0, 0b00>;
+def VRHADDt1s16 : VRHADDt1<"s16", 0b0, 0b01>;
+def VRHADDt1s32 : VRHADDt1<"s32", 0b0, 0b10>;
+def VRHADDt1u8  : VRHADDt1<"u8", 0b1, 0b00>;
+def VRHADDt1u16 : VRHADDt1<"u16", 0b1, 0b01>;
+def VRHADDt1u32 : VRHADDt1<"u32", 0b1, 0b10>;
+
+class VHADDVHSUBt1<string iname, string suffix, bit U, bits<2> size,
+                   list<dag> pattern=[]>
+  : MVE_int<iname, suffix, size, pattern> {
+
+  let Inst{28} = U;
+  let Inst{25-23} = 0b110;
+  let Inst{16} = 0b0;
+  let Inst{12-10} = 0b000;
+  let Inst{8} = 0b0;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+class VHSUBt1<string suffix, bit U, bits<2> size,
+              list<dag> pattern=[]>
+  : VHADDVHSUBt1<"vhsub", suffix, U, size, pattern> {
+
+  let Inst{9} = 0b1;
+}
+
+class VHADDt1<string suffix, bit U, bits<2> size,
+              list<dag> pattern=[]>
+  : VHADDVHSUBt1<"vhadd", suffix, U, size, pattern> {
+
+  let Inst{9} = 0b0;
+}
+
+def VHSUBt1s8  : VHSUBt1<"s8", 0b0, 0b00>;
+def VHSUBt1s16 : VHSUBt1<"s16", 0b0, 0b01>;
+def VHSUBt1s32 : VHSUBt1<"s32", 0b0, 0b10>;
+def VHSUBt1u8  : VHSUBt1<"u8", 0b1, 0b00>;
+def VHSUBt1u16 : VHSUBt1<"u16", 0b1, 0b01>;
+def VHSUBt1u32 : VHSUBt1<"u32", 0b1, 0b10>;
+
+def VHADDt1s8  : VHADDt1<"s8", 0b0, 0b00>;
+def VHADDt1s16 : VHADDt1<"s16", 0b0, 0b01>;
+def VHADDt1s32 : VHADDt1<"s32", 0b0, 0b10>;
+def VHADDt1u8  : VHADDt1<"u8", 0b1, 0b00>;
+def VHADDt1u16 : VHADDt1<"u16", 0b1, 0b01>;
+def VHADDt1u32 : VHADDt1<"u32", 0b1, 0b10>;
+
+class VDUPt1<string suffix, bit B, bit E, list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd), (ins rGPR:$Rt), NoItinerary,
+          "vdup", suffix, "$Qd, $Rt", vpred_r, "", pattern> {
+  bits<4> Qd;
+  bits<4> Rt;
+
+  let Inst{28} = 0b0;
+  let Inst{25-23} = 0b101;
+  let Inst{22} = B;
+  let Inst{21-20} = 0b10;
+  let Inst{19-17} = Qd{2-0};
+  let Inst{16} = 0b0;
+  let Inst{15-12} = Rt;
+  let Inst{11-8} = 0b1011;
+  let Inst{7} = Qd{3};
+  let Inst{6} = 0b0;
+  let Inst{5} = E;
+  let Inst{4-0} = 0b10000;
+}
+
+def VDUPt132 : VDUPt1<"32", 0b0, 0b0>;
+def VDUPt116 : VDUPt1<"16", 0b0, 0b1>;
+def VDUPt18  : VDUPt1<"8", 0b1, 0b0>;
+
+class MVEIntSingleSrc<string iname, string suffix, bits<2> size,
+                         list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qm), NoItinerary,
+          iname, suffix, "$Qd, $Qm", vpred_r, "", pattern> {
+  bits<4> Qd;
+  bits<4> Qm;
+
+  let Inst{22} = Qd{3};
+  let Inst{19-18} = size{1-0};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{5} = Qm{3};
+  let Inst{3-1} = Qm{2-0};
+}
+
+class VCLSVCLZt1<string iname, string suffix, bits<2> size,
+                 bit bit_7, list<dag> pattern=[]>
+  : MVEIntSingleSrc<iname, suffix, size, pattern> {
+
+  let Inst{28} = 0b1;
+  let Inst{25-23} = 0b111;
+  let Inst{21-20} = 0b11;
+  let Inst{17-16} = 0b00;
+  let Inst{12-8} = 0b00100;
+  let Inst{7} = bit_7;
+  let Inst{6} = 0b1;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def VCLSt1s8  : VCLSVCLZt1<"vcls", "s8", 0b00, 0b0>;
+def VCLSt1s16 : VCLSVCLZt1<"vcls", "s16", 0b01, 0b0>;
+def VCLSt1s32 : VCLSVCLZt1<"vcls", "s32", 0b10, 0b0>;
+
+def VCLZt1s8  : VCLSVCLZt1<"vclz", "i8", 0b00, 0b1>;
+def VCLZt1s16 : VCLSVCLZt1<"vclz", "i16", 0b01, 0b1>;
+def VCLZt1s32 : VCLSVCLZt1<"vclz", "i32", 0b10, 0b1>;
+
+class VNEGVABSt1<string iname, string suffix, bits<2> size, bit bit_7,
+             list<dag> pattern=[]>
+  : MVEIntSingleSrc<iname, suffix, size, pattern> {
+
+  let Inst{28} = 0b1;
+  let Inst{25-23} = 0b111;
+  let Inst{21-20} = 0b11;
+  let Inst{17-16} = 0b01;
+  let Inst{12-8} = 0b00011;
+  let Inst{7} = bit_7;
+  let Inst{6} = 0b1;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def VNEGt1s8  : VNEGVABSt1<"vneg", "s8", 0b00, 0b1>;
+def VNEGt1s16 : VNEGVABSt1<"vneg", "s16", 0b01, 0b1>;
+def VNEGt1s32 : VNEGVABSt1<"vneg", "s32", 0b10, 0b1>;
+
+def VABSt1s8  : VNEGVABSt1<"vabs", "s8", 0b00, 0b0>;
+def VABSt1s16 : VNEGVABSt1<"vabs", "s16", 0b01, 0b0>;
+def VABSt1s32 : VNEGVABSt1<"vabs", "s32", 0b10, 0b0>;
+
+class VQNEGVQABSt1<string iname, string suffix, bits<2> size,
+                   bit bit_7, list<dag> pattern=[]>
+  : MVEIntSingleSrc<iname, suffix, size, pattern> {
+
+  let Inst{28} = 0b1;
+  let Inst{25-23} = 0b111;
+  let Inst{21-20} = 0b11;
+  let Inst{17-16} = 0b00;
+  let Inst{12-8} = 0b00111;
+  let Inst{7} = bit_7;
+  let Inst{6} = 0b1;
+  let Inst{4} = 0b0;
+  let Inst{0} = 0b0;
+}
+
+def VQNEGt1s8  : VQNEGVQABSt1<"vqneg", "s8", 0b00, 0b1>;
+def VQNEGt1s16 : VQNEGVQABSt1<"vqneg", "s16", 0b01, 0b1>;
+def VQNEGt1s32 : VQNEGVQABSt1<"vqneg", "s32", 0b10, 0b1>;
+
+def VQABSt1s8  : VQNEGVQABSt1<"vqabs", "s8", 0b00, 0b0>;
+def VQABSt1s16 : VQNEGVQABSt1<"vqabs", "s16", 0b01, 0b0>;
+def VQABSt1s32 : VQNEGVQABSt1<"vqabs", "s32", 0b10, 0b0>;
+
+class MVE_mod_imm<string iname, string suffix, bits<4> cmode, bit op,
+                  dag iops, list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd), iops, NoItinerary, iname, suffix, "$Qd, $imm",
+          vpred_r, "", pattern> {
+  bits<13> imm;
+  bits<4> Qd;
+
+  let Inst{28} = imm{7};
+  let Inst{25-23} = 0b111;
+  let Inst{22} = Qd{3};
+  let Inst{21-19} = 0b000;
+  let Inst{18-16} = imm{6-4};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12} = 0b0;
+  let Inst{11-8} = cmode{3-0};
+  let Inst{7-6} = 0b01;
+  let Inst{5} = op;
+  let Inst{4} = 0b1;
+  let Inst{3-0} = imm{3-0};
+
+  let DecoderMethod = "DecodeMveModImmInstruction";
+}
+
+let isReMaterializable = 1 in {
+let isAsCheapAsAMove = 1 in {
+def VMOVimmi8  : MVE_mod_imm<"vmov", "i8",  {1,1,1,0}, 0b0, (ins nImmSplatI8:$imm)>;
+def VMOVimmi16 : MVE_mod_imm<"vmov", "i16", {1,0,?,0}, 0b0, (ins nImmSplatI16:$imm)> {
+  let Inst{9} = imm{9};
+}
+def VMOVimmi32 : MVE_mod_imm<"vmov", "i32", {?,?,?,?}, 0b0, (ins nImmVMOVI32:$imm)> {
+  let Inst{11-8} = imm{11-8};
+}
+def VMOVimmi64 : MVE_mod_imm<"vmov", "i64", {1,1,1,0}, 0b1, (ins nImmSplatI64:$imm)>;
+def VMOVimmf32 : MVE_mod_imm<"vmov", "f32", {1,1,1,1}, 0b0, (ins nImmVMOVF32:$imm)>;
+} // let isAsCheapAsAMove = 1
+
+def VMVNimmi16 : MVE_mod_imm<"vmvn", "i16", {1,0,?,0}, 0b1, (ins nImmSplatI16:$imm)> {
+  let Inst{9} = imm{9};
+}
+def VMVNimmi32 : MVE_mod_imm<"vmvn", "i32", {?,?,?,?}, 0b1, (ins nImmVMOVI32:$imm)> {
+  let Inst{11-8} = imm{11-8};
+}
+} // let isReMaterializable = 1
+
+// end of MVE Integer instructions
+
 class t2VPT<string suffix, bits<2> size, dag iops, string asm, list<dag> pattern=[]>
   : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
   bits<3> fc;
   bits<4> Mk;
   bits<3> Qn;
 
   let Inst{31-23} = 0b111111100;
   let Inst{22} = Mk{3};

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
   // First, split out any predication code. Ignore mnemonics we know aren't
   // predicated but do have a carry-set and so weren't caught above.
   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
       Mnemonic != "sbcs" && Mnemonic != "rscs" &&
        !(hasMVE() &&
          (Mnemonic.startswith("vmine") || Mnemonic.startswith("vshl") ||
-          Mnemonic.startswith("vmvne") || Mnemonic.startswith("vorne")))) {
+          Mnemonic.startswith("vmvne") || Mnemonic.startswith("vorne") ||
+          (Mnemonic.startswith("vnege") && !Mnemonic.startswith("vnegeq")) ||
+          Mnemonic.startswith("vnegt") || Mnemonic.startswith("vq")))) {
     unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
     if (CC != ~0U) {
       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
       PredicationCode = CC;
     }
   }
 
   // Next, determine if we have a carry setting bit. We explicitly ignore all
if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands) &&
       Operands.erase(Operands.begin());
       SMLoc MLoc = SMLoc::getFromPointer(NameLoc.getPointer());
       SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
                                          Mnemonic.size() - 1 + CarrySetting);
       Operands.insert(Operands.begin(),
                       ARMOperand::CreateVPTPred(ARMVCC::None, PLoc));
       Operands.insert(Operands.begin(),
                       ARMOperand::CreateToken(StringRef("vmovlt"), MLoc));
+    }
+    // For vmov and vcmp, as mentioned earlier, we did not add the vector
+    // predication code, since these may contain operands that require
+    // special parsing.  So now we have to see if they require vector
+    // predication and replace the scalar one with the vector predication
+    // operand if that is the case.
+    else if (Mnemonic == "vmov" || Mnemonic.startswith("vcmp")) {
+      if (!shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
+        Operands.erase(Operands.begin() + 1);
+        SMLoc PLoc = SMLoc::getFromPointer(NameLoc.getPointer() +
+                                          Mnemonic.size() + CarrySetting);
+        Operands.insert(Operands.begin() + 1,
+                        ARMOperand::CreateVPTPred(
+                            ARMVCC::VPTCodes(VPTPredicationCode), PLoc));
+      }
     } else if (CanAcceptVPTPredicationCode) {
       // For all other instructions, make sure only one of the two
       // predication operands is left behind, depending on whether we should
       // use the vector predication.
       if (shouldOmitVectorPredicateOperand(Mnemonic, Operands)) {
         if (CanAcceptPredicationCode)
           Operands.erase(Operands.begin() + 2);
         else

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
                                uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeMveModImmInstruction(MCInst &Inst,unsigned Val,
+                               uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder);
case ARM::VBICiv4i32:
       break;
     default:
       break;
   }
 
   return S;
 }
 
+static DecodeStatus
+DecodeMveModImmInstruction(MCInst &Inst, unsigned Insn,
+                           uint64_t Address, const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
+                 fieldFromInstruction(Insn, 13, 3));
+  unsigned cmode = fieldFromInstruction(Insn, 8, 4);
+  unsigned imm = fieldFromInstruction(Insn, 0, 4);
+  imm |= fieldFromInstruction(Insn, 16, 3) << 4;
+  imm |= fieldFromInstruction(Insn, 28, 1) << 7;
+  imm |= cmode                             << 8;
+  imm |= fieldFromInstruction(Insn, 5, 1)  << 12;
+
+  if (cmode == 0xF && Inst.getOpcode() == ARM::VMVNimmi32)
+    return MCDisassembler::Fail;
+
+  if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::createImm(imm));
+
+  // Might be more than vmov immediate.
+
+  Inst.addOperand(MCOperand::createImm(ARMVCC::None));
+  Inst.addOperand(MCOperand::createReg(0));
+  Inst.addOperand(MCOperand::createImm(0));
+
+  return S;
+}
+
 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
                                         uint64_t Address, const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rd = fieldFromInstruction(Insn, 12, 4);
   Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
   unsigned Rm = fieldFromInstruction(Insn, 0, 4);
   Rm |= fieldFromInstruction(Insn, 5, 1) << 4;

llvm/test/MC/ARM/mve-integer.s

+# RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding  < %s \
+# RUN:   | FileCheck --check-prefix=CHECK-NOFP %s
+# RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding  < %s \
+# RUN:   | FileCheck --check-prefix=CHECK %s
+
+# CHECK: vmul.i8 q0, q0, q3  @ encoding: [0x00,0xef,0x56,0x09]
+# CHECK-NOFP: vmul.i8 q0, q0, q3  @ encoding: [0x00,0xef,0x56,0x09]
+vmul.i8 q0, q0, q3
+
+# CHECK: vmul.i16 q6, q0, q3  @ encoding: [0x10,0xef,0x56,0xc9]
+# CHECK-NOFP: vmul.i16 q6, q0, q3  @ encoding: [0x10,0xef,0x56,0xc9]
+vmul.i16 q6, q0, q3
+
+# CHECK: vmul.i32 q7, q3, q6  @ encoding: [0x26,0xef,0x5c,0xe9]
+# CHECK-NOFP: vmul.i32 q7, q3, q6  @ encoding: [0x26,0xef,0x5c,0xe9]
+vmul.i32 q7, q3, q6
+
+# CHECK: vqrdmulh.s8 q0, q5, q5  @ encoding: [0x0a,0xff,0x4a,0x0b]
+# CHECK-NOFP: vqrdmulh.s8 q0, q5, q5  @ encoding: [0x0a,0xff,0x4a,0x0b]
+vqrdmulh.s8 q0, q5, q5
+
+# CHECK: vqrdmulh.s16 q1, q4, q2  @ encoding: [0x18,0xff,0x44,0x2b]
+# CHECK-NOFP: vqrdmulh.s16 q1, q4, q2  @ encoding: [0x18,0xff,0x44,0x2b]
+vqrdmulh.s16 q1, q4, q2
+
+# CHECK: vqrdmulh.s32 q0, q5, q0  @ encoding: [0x2a,0xff,0x40,0x0b]
+# CHECK-NOFP: vqrdmulh.s32 q0, q5, q0  @ encoding: [0x2a,0xff,0x40,0x0b]
+vqrdmulh.s32 q0, q5, q0
+
+# CHECK: vqdmulh.s8 q0, q4, q5  @ encoding: [0x08,0xef,0x4a,0x0b]
+# CHECK-NOFP: vqdmulh.s8 q0, q4, q5  @ encoding: [0x08,0xef,0x4a,0x0b]
+vqdmulh.s8 q0, q4, q5
+
+# CHECK: vqdmulh.s16 q6, q4, q0  @ encoding: [0x18,0xef,0x40,0xcb]
+# CHECK-NOFP: vqdmulh.s16 q6, q4, q0  @ encoding: [0x18,0xef,0x40,0xcb]
+vqdmulh.s16 q6, q4, q0
+
+# CHECK: vqdmulh.s32 q5, q0, q6  @ encoding: [0x20,0xef,0x4c,0xab]
+# CHECK-NOFP: vqdmulh.s32 q5, q0, q6  @ encoding: [0x20,0xef,0x4c,0xab]
+vqdmulh.s32 q5, q0, q6
+
+# CHECK: vsub.i8 q3, q2, q5  @ encoding: [0x04,0xff,0x4a,0x68]
+# CHECK-NOFP: vsub.i8 q3, q2, q5  @ encoding: [0x04,0xff,0x4a,0x68]
+vsub.i8 q3, q2, q5
+
+# CHECK: vsub.i16 q0, q3, q6  @ encoding: [0x16,0xff,0x4c,0x08]
+# CHECK-NOFP: vsub.i16 q0, q3, q6  @ encoding: [0x16,0xff,0x4c,0x08]
+vsub.i16 q0, q3, q6
+
+# CHECK: vsub.i32 q0, q0, q6  @ encoding: [0x20,0xff,0x4c,0x08]
+# CHECK-NOFP: vsub.i32 q0, q0, q6  @ encoding: [0x20,0xff,0x4c,0x08]
+vsub.i32 q0, q0, q6
+
+# CHECK: vadd.i8 q0, q2, q2  @ encoding: [0x04,0xef,0x44,0x08]
+# CHECK-NOFP: vadd.i8 q0, q2, q2  @ encoding: [0x04,0xef,0x44,0x08]
+vadd.i8 q0, q2, q2
+
+# CHECK: vadd.i16 q2, q2, q1  @ encoding: [0x14,0xef,0x42,0x48]
+# CHECK-NOFP: vadd.i16 q2, q2, q1  @ encoding: [0x14,0xef,0x42,0x48]
+vadd.i16 q2, q2, q1
+
+# CHECK: vadd.i32 q0, q0, q6  @ encoding: [0x20,0xef,0x4c,0x08]
+# CHECK-NOFP: vadd.i32 q0, q0, q6  @ encoding: [0x20,0xef,0x4c,0x08]
+vadd.i32 q0, q0, q6
+
+# CHECK: vqsub.s8 q1, q6, q0  @ encoding: [0x0c,0xef,0x50,0x22]
+# CHECK-NOFP: vqsub.s8 q1, q6, q0  @ encoding: [0x0c,0xef,0x50,0x22]
+vqsub.s8 q1, q6, q0
+
+# CHECK: vqsub.s16 q0, q6, q1  @ encoding: [0x1c,0xef,0x52,0x02]
+# CHECK-NOFP: vqsub.s16 q0, q6, q1  @ encoding: [0x1c,0xef,0x52,0x02]
+vqsub.s16 q0, q6, q1
+
+# CHECK: vqsub.s32 q0, q0, q5  @ encoding: [0x20,0xef,0x5a,0x02]
+# CHECK-NOFP: vqsub.s32 q0, q0, q5  @ encoding: [0x20,0xef,0x5a,0x02]
+vqsub.s32 q0, q0, q5
+
+# CHECK: vqsub.u8 q0, q2, q6  @ encoding: [0x04,0xff,0x5c,0x02]
+# CHECK-NOFP: vqsub.u8 q0, q2, q6  @ encoding: [0x04,0xff,0x5c,0x02]
+vqsub.u8 q0, q2, q6
+
+# CHECK: vqsub.u16 q0, q7, q1  @ encoding: [0x1e,0xff,0x52,0x02]
+# CHECK-NOFP: vqsub.u16 q0, q7, q1  @ encoding: [0x1e,0xff,0x52,0x02]
+vqsub.u16 q0, q7, q1
+
+# CHECK: vqsub.u32 q1, q4, q7  @ encoding: [0x28,0xff,0x5e,0x22]
+# CHECK-NOFP: vqsub.u32 q1, q4, q7  @ encoding: [0x28,0xff,0x5e,0x22]
+vqsub.u32 q1, q4, q7
+
+# CHECK: vqadd.s8 q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x00]
+# CHECK-NOFP: vqadd.s8 q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x00]
+vqadd.s8 q0, q1, q2
+
+# CHECK: vqadd.s8 q0, q4, q6  @ encoding: [0x08,0xef,0x5c,0x00]
+# CHECK-NOFP: vqadd.s8 q0, q4, q6  @ encoding: [0x08,0xef,0x5c,0x00]
+vqadd.s8 q0, q4, q6
+
+# CHECK: vqadd.s16 q0, q5, q5  @ encoding: [0x1a,0xef,0x5a,0x00]
+# CHECK-NOFP: vqadd.s16 q0, q5, q5  @ encoding: [0x1a,0xef,0x5a,0x00]
+vqadd.s16 q0, q5, q5
+
+# CHECK: vqadd.s32 q0, q0, q4  @ encoding: [0x20,0xef,0x58,0x00]
+# CHECK-NOFP: vqadd.s32 q0, q0, q4  @ encoding: [0x20,0xef,0x58,0x00]
+vqadd.s32 q0, q0, q4
+
+# CHECK: vqadd.u8 q0, q4, q2  @ encoding: [0x08,0xff,0x54,0x00]
+# CHECK-NOFP: vqadd.u8 q0, q4, q2  @ encoding: [0x08,0xff,0x54,0x00]
+vqadd.u8 q0, q4, q2
+
+# CHECK: vqadd.u16 q4, q6, q6  @ encoding: [0x1c,0xff,0x5c,0x80]
+# CHECK-NOFP: vqadd.u16 q4, q6, q6  @ encoding: [0x1c,0xff,0x5c,0x80]
+vqadd.u16 q4, q6, q6
+
+# CHECK: vqadd.u32 q0, q1, q2  @ encoding: [0x22,0xff,0x54,0x00]
+# CHECK-NOFP: vqadd.u32 q0, q1, q2  @ encoding: [0x22,0xff,0x54,0x00]
+vqadd.u32 q0, q1, q2
+
+# CHECK: vabd.s8 q0, q0, q2  @ encoding: [0x00,0xef,0x44,0x07]
+# CHECK-NOFP: vabd.s8 q0, q0, q2  @ encoding: [0x00,0xef,0x44,0x07]
+vabd.s8 q0, q0, q2
+
+# CHECK: vabd.s16 q1, q5, q4  @ encoding: [0x1a,0xef,0x48,0x27]
+# CHECK-NOFP: vabd.s16 q1, q5, q4  @ encoding: [0x1a,0xef,0x48,0x27]
+vabd.s16 q1, q5, q4
+
+# CHECK: vabd.s32 q2, q3, q2  @ encoding: [0x26,0xef,0x44,0x47]
+# CHECK-NOFP: vabd.s32 q2, q3, q2  @ encoding: [0x26,0xef,0x44,0x47]
+vabd.s32 q2, q3, q2
+
+# CHECK: vabd.u8 q1, q6, q4  @ encoding: [0x0c,0xff,0x48,0x27]
+# CHECK-NOFP: vabd.u8 q1, q6, q4  @ encoding: [0x0c,0xff,0x48,0x27]
+vabd.u8 q1, q6, q4
+
+# CHECK: vabd.u16 q0, q6, q2  @ encoding: [0x1c,0xff,0x44,0x07]
+# CHECK-NOFP: vabd.u16 q0, q6, q2  @ encoding: [0x1c,0xff,0x44,0x07]
+vabd.u16 q0, q6, q2
+
+# CHECK: vabd.u32 q0, q7, q4  @ encoding: [0x2e,0xff,0x48,0x07]
+# CHECK-NOFP: vabd.u32 q0, q7, q4  @ encoding: [0x2e,0xff,0x48,0x07]
+vabd.u32 q0, q7, q4
+
+# CHECK: vrhadd.s8 q0, q1, q1  @ encoding: [0x02,0xef,0x42,0x01]
+# CHECK-NOFP: vrhadd.s8 q0, q1, q1  @ encoding: [0x02,0xef,0x42,0x01]
+vrhadd.s8 q0, q1, q1
+
+# CHECK: vrhadd.s16 q0, q1, q0  @ encoding: [0x12,0xef,0x40,0x01]
+# CHECK-NOFP: vrhadd.s16 q0, q1, q0  @ encoding: [0x12,0xef,0x40,0x01]
+vrhadd.s16 q0, q1, q0
+
+# CHECK: vrhadd.s32 q0, q4, q1  @ encoding: [0x28,0xef,0x42,0x01]
+# CHECK-NOFP: vrhadd.s32 q0, q4, q1  @ encoding: [0x28,0xef,0x42,0x01]
+vrhadd.s32 q0, q4, q1
+
+# CHECK: vrhadd.u8 q1, q0, q6  @ encoding: [0x00,0xff,0x4c,0x21]
+# CHECK-NOFP: vrhadd.u8 q1, q0, q6  @ encoding: [0x00,0xff,0x4c,0x21]
+vrhadd.u8 q1, q0, q6
+
+# CHECK: vrhadd.u16 q2, q2, q5  @ encoding: [0x14,0xff,0x4a,0x41]
+# CHECK-NOFP: vrhadd.u16 q2, q2, q5  @ encoding: [0x14,0xff,0x4a,0x41]
+vrhadd.u16 q2, q2, q5
+
+# CHECK: vrhadd.u32 q2, q3, q0  @ encoding: [0x26,0xff,0x40,0x41]
+# CHECK-NOFP: vrhadd.u32 q2, q3, q0  @ encoding: [0x26,0xff,0x40,0x41]
+vrhadd.u32 q2, q3, q0
+
+# CHECK: vhsub.s8 q0, q0, q2  @ encoding: [0x00,0xef,0x44,0x02]
+# CHECK-NOFP: vhsub.s8 q0, q0, q2  @ encoding: [0x00,0xef,0x44,0x02]
+vhsub.s8 q0, q0, q2
+
+# CHECK: vhsub.s16 q1, q3, q1  @ encoding: [0x16,0xef,0x42,0x22]
+# CHECK-NOFP: vhsub.s16 q1, q3, q1  @ encoding: [0x16,0xef,0x42,0x22]
+vhsub.s16 q1, q3, q1
+
+# CHECK: vhsub.s32 q0, q2, q5  @ encoding: [0x24,0xef,0x4a,0x02]
+# CHECK-NOFP: vhsub.s32 q0, q2, q5  @ encoding: [0x24,0xef,0x4a,0x02]
+vhsub.s32 q0, q2, q5
+
+# CHECK: vhsub.u8 q0, q4, q2  @ encoding: [0x08,0xff,0x44,0x02]
+# CHECK-NOFP: vhsub.u8 q0, q4, q2  @ encoding: [0x08,0xff,0x44,0x02]
+vhsub.u8 q0, q4, q2
+
+# CHECK: vhsub.u16 q0, q7, q5  @ encoding: [0x1e,0xff,0x4a,0x02]
+# CHECK-NOFP: vhsub.u16 q0, q7, q5  @ encoding: [0x1e,0xff,0x4a,0x02]
+vhsub.u16 q0, q7, q5
+
+# CHECK: vhsub.u32 q2, q6, q4  @ encoding: [0x2c,0xff,0x48,0x42]
+# CHECK-NOFP: vhsub.u32 q2, q6, q4  @ encoding: [0x2c,0xff,0x48,0x42]
+vhsub.u32 q2, q6, q4
+
+# CHECK: vhadd.s8 q0, q7, q0  @ encoding: [0x0e,0xef,0x40,0x00]
+# CHECK-NOFP: vhadd.s8 q0, q7, q0  @ encoding: [0x0e,0xef,0x40,0x00]
+vhadd.s8 q0, q7, q0
+
+# CHECK: vhadd.s16 q4, q0, q2  @ encoding: [0x10,0xef,0x44,0x80]
+# CHECK-NOFP: vhadd.s16 q4, q0, q2  @ encoding: [0x10,0xef,0x44,0x80]
+vhadd.s16 q4, q0, q2
+
+# CHECK: vhadd.s32 q0, q3, q1  @ encoding: [0x26,0xef,0x42,0x00]
+# CHECK-NOFP: vhadd.s32 q0, q3, q1  @ encoding: [0x26,0xef,0x42,0x00]
+vhadd.s32 q0, q3, q1
+
+# CHECK: vhadd.u8 q3, q0, q3  @ encoding: [0x00,0xff,0x46,0x60]
+# CHECK-NOFP: vhadd.u8 q3, q0, q3  @ encoding: [0x00,0xff,0x46,0x60]
+vhadd.u8 q3, q0, q3
+
+# CHECK: vhadd.u16 q0, q1, q3  @ encoding: [0x12,0xff,0x46,0x00]
+# CHECK-NOFP: vhadd.u16 q0, q1, q3  @ encoding: [0x12,0xff,0x46,0x00]
+vhadd.u16 q0, q1, q3
+
+# CHECK: vhadd.u32 q0, q1, q3  @ encoding: [0x22,0xff,0x46,0x00]
+# CHECK-NOFP: vhadd.u32 q0, q1, q3  @ encoding: [0x22,0xff,0x46,0x00]
+vhadd.u32 q0, q1, q3
+
+# CHECK: vdup.8 q6, r8  @ encoding: [0xec,0xee,0x10,0x8b]
+# CHECK-NOFP: vdup.8 q6, r8  @ encoding: [0xec,0xee,0x10,0x8b]
+vdup.8 q6, r8
+
+# CHECK: vdup.16 q7, lr  @ encoding: [0xae,0xee,0x30,0xeb]
+# CHECK-NOFP: vdup.16 q7, lr  @ encoding: [0xae,0xee,0x30,0xeb]
+vdup.16 q7, lr
+
+# CHECK: vdup.32 q1, r9  @ encoding: [0xa2,0xee,0x10,0x9b]
+# CHECK-NOFP: vdup.32 q1, r9  @ encoding: [0xa2,0xee,0x10,0x9b]
+vdup.32 q1, r9
+
+# CHECK: vpte.i8 eq, q0, q0
+# CHECK-NOFP: vpte.i8 eq, q0, q0
+# CHECK: vdupt.16 q0, r1  @ encoding: [0xa0,0xee,0x30,0x1b]
+# CHECK-NOFP: vdupt.16 q0, r1  @ encoding: [0xa0,0xee,0x30,0x1b]
+# CHECK: vdupe.16 q0, r1  @ encoding: [0xa0,0xee,0x30,0x1b]
+# CHECK-NOFP: vdupe.16 q0, r1  @ encoding: [0xa0,0xee,0x30,0x1b]
+vpte.i8 eq, q0, q0
+vdupt.16 q0, r1
+vdupe.16 q0, r1
+
+# CHECK: vcls.s8 q2, q1  @ encoding: [0xb0,0xff,0x42,0x44]
+# CHECK-NOFP: vcls.s8 q2, q1  @ encoding: [0xb0,0xff,0x42,0x44]
+vcls.s8 q2, q1
+
+# CHECK: vcls.s16 q0, q4  @ encoding: [0xb4,0xff,0x48,0x04]
+# CHECK-NOFP: vcls.s16 q0, q4  @ encoding: [0xb4,0xff,0x48,0x04]
+vcls.s16 q0, q4
+
+# CHECK: vcls.s32 q0, q0  @ encoding: [0xb8,0xff,0x40,0x04]
+# CHECK-NOFP: vcls.s32 q0, q0  @ encoding: [0xb8,0xff,0x40,0x04]
+vcls.s32 q0, q0
+
+# CHECK: vclz.i8 q0, q7  @ encoding: [0xb0,0xff,0xce,0x04]
+# CHECK-NOFP: vclz.i8 q0, q7  @ encoding: [0xb0,0xff,0xce,0x04]
+vclz.i8 q0, q7
+
+# CHECK: vclz.i16 q4, q7  @ encoding: [0xb4,0xff,0xce,0x84]
+# CHECK-NOFP: vclz.i16 q4, q7  @ encoding: [0xb4,0xff,0xce,0x84]
+vclz.i16 q4, q7
+
+# CHECK: vclz.i32 q7, q5  @ encoding: [0xb8,0xff,0xca,0xe4]
+# CHECK-NOFP: vclz.i32 q7, q5  @ encoding: [0xb8,0xff,0xca,0xe4]
+vclz.i32 q7, q5
+
+# CHECK: vneg.s8 q1, q0  @ encoding: [0xb1,0xff,0xc0,0x23]
+# CHECK-NOFP: vneg.s8 q1, q0  @ encoding: [0xb1,0xff,0xc0,0x23]
+vneg.s8 q1, q0
+
+# CHECK: vneg.s16 q0, q1  @ encoding: [0xb5,0xff,0xc2,0x03]
+# CHECK-NOFP: vneg.s16 q0, q1  @ encoding: [0xb5,0xff,0xc2,0x03]
+vneg.s16 q0, q1
+
+# CHECK: vneg.s32 q7, q2  @ encoding: [0xb9,0xff,0xc4,0xe3]
+# CHECK-NOFP: vneg.s32 q7, q2  @ encoding: [0xb9,0xff,0xc4,0xe3]
+vneg.s32 q7, q2
+
+# CHECK: vabs.s8 q1, q1  @ encoding: [0xb1,0xff,0x42,0x23]
+# CHECK-NOFP: vabs.s8 q1, q1  @ encoding: [0xb1,0xff,0x42,0x23]
+vabs.s8 q1, q1
+
+# CHECK: vabs.s16 q0, q2  @ encoding: [0xb5,0xff,0x44,0x03]
+# CHECK-NOFP: vabs.s16 q0, q2  @ encoding: [0xb5,0xff,0x44,0x03]
+vabs.s16 q0, q2
+
+# CHECK: vabs.s32 q0, q7  @ encoding: [0xb9,0xff,0x4e,0x03]
+# CHECK-NOFP: vabs.s32 q0, q7  @ encoding: [0xb9,0xff,0x4e,0x03]
+vabs.s32 q0, q7
+
+# CHECK: vqneg.s8 q0, q0  @ encoding: [0xb0,0xff,0xc0,0x07]
+# CHECK-NOFP: vqneg.s8 q0, q0  @ encoding: [0xb0,0xff,0xc0,0x07]
+vqneg.s8 q0, q0
+
+# CHECK: vqneg.s16 q6, q2  @ encoding: [0xb4,0xff,0xc4,0xc7]
+# CHECK-NOFP: vqneg.s16 q6, q2  @ encoding: [0xb4,0xff,0xc4,0xc7]
+vqneg.s16 q6, q2
+
+# CHECK: vqneg.s32 q7, q2  @ encoding: [0xb8,0xff,0xc4,0xe7]
+# CHECK-NOFP: vqneg.s32 q7, q2  @ encoding: [0xb8,0xff,0xc4,0xe7]
+vqneg.s32 q7, q2
+
+# CHECK: vqabs.s8 q2, q4  @ encoding: [0xb0,0xff,0x48,0x47]
+# CHECK-NOFP: vqabs.s8 q2, q4  @ encoding: [0xb0,0xff,0x48,0x47]
+vqabs.s8 q2, q4
+
+# CHECK: vqabs.s16 q0, q2  @ encoding: [0xb4,0xff,0x44,0x07]
+# CHECK-NOFP: vqabs.s16 q0, q2  @ encoding: [0xb4,0xff,0x44,0x07]
+vqabs.s16 q0, q2
+
+# CHECK: vqabs.s32 q0, q5  @ encoding: [0xb8,0xff,0x4a,0x07]
+# CHECK-NOFP: vqabs.s32 q0, q5  @ encoding: [0xb8,0xff,0x4a,0x07]
+vqabs.s32 q0, q5
+
+vpste
+vnegt.s8 q0, q1
+vnege.s8 q0, q1
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vnegt.s8 q0, q1 @ encoding: [0xb1,0xff,0xc2,0x03]
+# CHECK-NOFP: vnegt.s8 q0, q1 @ encoding: [0xb1,0xff,0xc2,0x03]
+# CHECK: vnege.s8 q0, q1 @ encoding: [0xb1,0xff,0xc2,0x03]
+# CHECK-NOFP: vnege.s8 q0, q1 @ encoding: [0xb1,0xff,0xc2,0x03]
+
+vpst
+vqaddt.s16 q0, q1, q2
+# CHECK: vpst @ encoding: [0x71,0xfe,0x4d,0x0f]
+# CHECK-NOFP: vpst @ encoding: [0x71,0xfe,0x4d,0x0f]
+# CHECK: vqaddt.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x00]
+# CHECK-NOFP: vqaddt.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x00]
+
+vpste
+vqnegt.s8 q0, q1
+vqnege.s16 q0, q1
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vqnegt.s8 q0, q1 @ encoding: [0xb0,0xff,0xc2,0x07]
+# CHECK-NOFP: vqnegt.s8 q0, q1 @ encoding: [0xb0,0xff,0xc2,0x07]
+# CHECK: vqnege.s16 q0, q1 @ encoding: [0xb4,0xff,0xc2,0x07]
+# CHECK-NOFP: vqnege.s16 q0, q1 @ encoding: [0xb4,0xff,0xc2,0x07]

llvm/test/MC/Disassembler/ARM/mve-integer.txt

+# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
+# RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
+
+# CHECK: vmul.i8 q0, q0, q3  @ encoding: [0x00,0xef,0x56,0x09]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xef,0x56,0x09]
+
+# CHECK: vmul.i16 q6, q0, q3  @ encoding: [0x10,0xef,0x56,0xc9]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xef,0x56,0xc9]
+
+# CHECK: vmul.i32 q7, q3, q6  @ encoding: [0x26,0xef,0x5c,0xe9]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xef,0x5c,0xe9]
+
+# CHECK: vqrdmulh.s8 q0, q5, q5  @ encoding: [0x0a,0xff,0x4a,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0a,0xff,0x4a,0x0b]
+
+# CHECK: vqrdmulh.s16 q1, q4, q2  @ encoding: [0x18,0xff,0x44,0x2b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xff,0x44,0x2b]
+
+# CHECK: vqrdmulh.s32 q0, q5, q0  @ encoding: [0x2a,0xff,0x40,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xff,0x40,0x0b]
+
+# CHECK: vqdmulh.s8 q0, q4, q5  @ encoding: [0x08,0xef,0x4a,0x0b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xef,0x4a,0x0b]
+
+# CHECK: vqdmulh.s16 q6, q4, q0  @ encoding: [0x18,0xef,0x40,0xcb]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xef,0x40,0xcb]
+
+# CHECK: vqdmulh.s32 q5, q0, q6  @ encoding: [0x20,0xef,0x4c,0xab]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xef,0x4c,0xab]
+
+# CHECK: vsub.i8 q3, q2, q5  @ encoding: [0x04,0xff,0x4a,0x68]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xff,0x4a,0x68]
+
+# CHECK: vsub.i16 q0, q3, q6  @ encoding: [0x16,0xff,0x4c,0x08]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xff,0x4c,0x08]
+
+# CHECK: vsub.i32 q0, q0, q6  @ encoding: [0x20,0xff,0x4c,0x08]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xff,0x4c,0x08]
+
+# CHECK: vadd.i8 q0, q2, q2  @ encoding: [0x04,0xef,0x44,0x08]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xef,0x44,0x08]
+
+# CHECK: vadd.i16 q2, q2, q1  @ encoding: [0x14,0xef,0x42,0x48]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xef,0x42,0x48]
+
+# CHECK: vadd.i32 q0, q0, q6  @ encoding: [0x20,0xef,0x4c,0x08]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xef,0x4c,0x08]
+
+# CHECK: vqsub.s8 q1, q6, q0  @ encoding: [0x0c,0xef,0x50,0x22]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xef,0x50,0x22]
+
+# CHECK: vqsub.s16 q0, q6, q1  @ encoding: [0x1c,0xef,0x52,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1c,0xef,0x52,0x02]
+
+# CHECK: vqsub.s32 q0, q0, q5  @ encoding: [0x20,0xef,0x5a,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xef,0x5a,0x02]
+
+# CHECK: vqsub.u8 q0, q2, q6  @ encoding: [0x04,0xff,0x5c,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xff,0x5c,0x02]
+
+# CHECK: vqsub.u16 q0, q7, q1  @ encoding: [0x1e,0xff,0x52,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1e,0xff,0x52,0x02]
+
+# CHECK: vqsub.u32 q1, q4, q7  @ encoding: [0x28,0xff,0x5e,0x22]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xff,0x5e,0x22]
+
+# CHECK: vqadd.s8 q0, q4, q6  @ encoding: [0x08,0xef,0x5c,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xef,0x5c,0x00]
+
+# CHECK: vqadd.s16 q0, q5, q5  @ encoding: [0x1a,0xef,0x5a,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xef,0x5a,0x00]
+
+# CHECK: vqadd.s32 q0, q0, q4  @ encoding: [0x20,0xef,0x58,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xef,0x58,0x00]
+
+# CHECK: vqadd.u8 q0, q4, q2  @ encoding: [0x08,0xff,0x54,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xff,0x54,0x00]
+
+# CHECK: vqadd.u16 q4, q6, q6  @ encoding: [0x1c,0xff,0x5c,0x80]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1c,0xff,0x5c,0x80]
+
+# CHECK: vqadd.u32 q0, q1, q2  @ encoding: [0x22,0xff,0x54,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xff,0x54,0x00]
+
+# CHECK: vabd.s8 q0, q0, q2  @ encoding: [0x00,0xef,0x44,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xef,0x44,0x07]
+
+# CHECK: vabd.s16 q1, q5, q4  @ encoding: [0x1a,0xef,0x48,0x27]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xef,0x48,0x27]
+
+# CHECK: vabd.s32 q2, q3, q2  @ encoding: [0x26,0xef,0x44,0x47]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xef,0x44,0x47]
+
+# CHECK: vabd.u8 q1, q6, q4  @ encoding: [0x0c,0xff,0x48,0x27]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xff,0x48,0x27]
+
+# CHECK: vabd.u16 q0, q6, q2  @ encoding: [0x1c,0xff,0x44,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1c,0xff,0x44,0x07]
+
+# CHECK: vabd.u32 q0, q7, q4  @ encoding: [0x2e,0xff,0x48,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2e,0xff,0x48,0x07]
+
+# CHECK: vrhadd.s8 q0, q1, q1  @ encoding: [0x02,0xef,0x42,0x01]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xef,0x42,0x01]
+
+# CHECK: vrhadd.s16 q0, q1, q0  @ encoding: [0x12,0xef,0x40,0x01]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xef,0x40,0x01]
+
+# CHECK: vrhadd.s32 q0, q4, q1  @ encoding: [0x28,0xef,0x42,0x01]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xef,0x42,0x01]
+
+# CHECK: vrhadd.u8 q1, q0, q6  @ encoding: [0x00,0xff,0x4c,0x21]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xff,0x4c,0x21]
+
+# CHECK: vrhadd.u16 q2, q2, q5  @ encoding: [0x14,0xff,0x4a,0x41]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xff,0x4a,0x41]
+
+# CHECK: vrhadd.u32 q2, q3, q0  @ encoding: [0x26,0xff,0x40,0x41]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xff,0x40,0x41]
+
+# CHECK: vhsub.s8 q0, q0, q2  @ encoding: [0x00,0xef,0x44,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xef,0x44,0x02]
+
+# CHECK: vhsub.s16 q1, q3, q1  @ encoding: [0x16,0xef,0x42,0x22]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xef,0x42,0x22]
+
+# CHECK: vhsub.s32 q0, q2, q5  @ encoding: [0x24,0xef,0x4a,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xef,0x4a,0x02]
+
+# CHECK: vhsub.u8 q0, q4, q2  @ encoding: [0x08,0xff,0x44,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xff,0x44,0x02]
+
+# CHECK: vhsub.u16 q0, q7, q5  @ encoding: [0x1e,0xff,0x4a,0x02]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1e,0xff,0x4a,0x02]
+
+# CHECK: vhsub.u32 q2, q6, q4  @ encoding: [0x2c,0xff,0x48,0x42]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2c,0xff,0x48,0x42]
+
+# CHECK: vhadd.s8 q0, q7, q0  @ encoding: [0x0e,0xef,0x40,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0e,0xef,0x40,0x00]
+
+# CHECK: vhadd.s16 q4, q0, q2  @ encoding: [0x10,0xef,0x44,0x80]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xef,0x44,0x80]
+
+# CHECK: vhadd.s32 q0, q3, q1  @ encoding: [0x26,0xef,0x42,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xef,0x42,0x00]
+
+# CHECK: vhadd.u8 q3, q0, q3  @ encoding: [0x00,0xff,0x46,0x60]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xff,0x46,0x60]
+
+# CHECK: vhadd.u16 q0, q1, q3  @ encoding: [0x12,0xff,0x46,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xff,0x46,0x00]
+
+# CHECK: vhadd.u32 q0, q1, q3  @ encoding: [0x22,0xff,0x46,0x00]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xff,0x46,0x00]
+
+# CHECK: vdup.8 q6, r8  @ encoding: [0xec,0xee,0x10,0x8b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xec,0xee,0x10,0x8b]
+
+# CHECK: vdup.16 q7, lr  @ encoding: [0xae,0xee,0x30,0xeb]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xae,0xee,0x30,0xeb]
+
+# CHECK: vdup.32 q1, r9  @ encoding: [0xa2,0xee,0x10,0x9b]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa2,0xee,0x10,0x9b]
+
+# CHECK: vpte.i8 eq, q0, q0 @ encoding: [0x41,0xfe,0x00,0x8f]
+# CHECK-NOMVE: [[@LINE+5]]:2: warning: invalid instruction encoding
+# CHECK: vdupt.16 q0, r1  @ encoding: [0xa0,0xee,0x30,0x1b]
+# CHECK-NOMVE: [[@LINE+4]]:2: warning: invalid instruction encoding
+# CHECK: vdupe.16 q0, r1  @ encoding: [0xa0,0xee,0x30,0x1b]
+# CHECK-NOMVE: [[@LINE+3]]:2: warning: invalid instruction encoding
+[0x41,0xfe,0x00,0x8f]
+[0xa0,0xee,0x30,0x1b]
+[0xa0,0xee,0x30,0x1b]
+
+# CHECK: vcls.s8 q2, q1  @ encoding: [0xb0,0xff,0x42,0x44]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xff,0x42,0x44]
+
+# CHECK: vcls.s16 q0, q4  @ encoding: [0xb4,0xff,0x48,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xff,0x48,0x04]
+
+# CHECK: vcls.s32 q0, q0  @ encoding: [0xb8,0xff,0x40,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb8,0xff,0x40,0x04]
+
+# CHECK: vclz.i8 q0, q7  @ encoding: [0xb0,0xff,0xce,0x04]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xff,0xce,0x04]
+
+# CHECK: vclz.i16 q4, q7  @ encoding: [0xb4,0xff,0xce,0x84]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xff,0xce,0x84]
+
+# CHECK: vclz.i32 q7, q5  @ encoding: [0xb8,0xff,0xca,0xe4]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb8,0xff,0xca,0xe4]
+
+# CHECK: vneg.s8 q1, q0  @ encoding: [0xb1,0xff,0xc0,0x23]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb1,0xff,0xc0,0x23]
+
+# CHECK: vneg.s16 q0, q1  @ encoding: [0xb5,0xff,0xc2,0x03]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb5,0xff,0xc2,0x03]
+
+# CHECK: vneg.s32 q7, q2  @ encoding: [0xb9,0xff,0xc4,0xe3]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb9,0xff,0xc4,0xe3]
+
+# CHECK: vabs.s8 q1, q1  @ encoding: [0xb1,0xff,0x42,0x23]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb1,0xff,0x42,0x23]
+
+# CHECK: vabs.s16 q0, q2  @ encoding: [0xb5,0xff,0x44,0x03]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb5,0xff,0x44,0x03]
+
+# CHECK: vabs.s32 q0, q7  @ encoding: [0xb9,0xff,0x4e,0x03]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb9,0xff,0x4e,0x03]
+
+# CHECK: vqneg.s8 q0, q0  @ encoding: [0xb0,0xff,0xc0,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xff,0xc0,0x07]
+
+# CHECK: vqneg.s16 q6, q2  @ encoding: [0xb4,0xff,0xc4,0xc7]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xff,0xc4,0xc7]
+
+# CHECK: vqneg.s32 q7, q2  @ encoding: [0xb8,0xff,0xc4,0xe7]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb8,0xff,0xc4,0xe7]
+
+# CHECK: vqabs.s8 q2, q4  @ encoding: [0xb0,0xff,0x48,0x47]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb0,0xff,0x48,0x47]
+
+# CHECK: vqabs.s16 q0, q2  @ encoding: [0xb4,0xff,0x44,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb4,0xff,0x44,0x07]
+
+# CHECK: vqabs.s32 q0, q5  @ encoding: [0xb8,0xff,0x4a,0x07]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xb8,0xff,0x4a,0x07]