samparker (Sam Parker)
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User Since
May 11 2015, 7:59 AM (162 w, 2 d)

Recent Activity

Today

samparker added inline comments to D48128: [ARM] Parallel DSP IR Pass.
Thu, Jun 21, 3:35 AM
samparker added a comment to D48128: [ARM] Parallel DSP IR Pass.

Hi Sjoerd,

Thu, Jun 21, 3:22 AM

Yesterday

samparker accepted D48335: [DAG] Fix and-mask folding when narrowing loads..

LGTM. Thanks.

Wed, Jun 20, 12:36 AM

Tue, Jun 19

samparker added a comment to D47730: [SelectionDAG]Reduce masked data movement chains and memory access widths pt3.

I am not suggesting that I will ask you to refactor by the way! I just want to spend some more time looking at these functions and having a play with your other two patches.

Tue, Jun 19, 5:32 AM · Restricted Project
samparker added a comment to D47730: [SelectionDAG]Reduce masked data movement chains and memory access widths pt3.

Hi Diogo,

Tue, Jun 19, 5:29 AM · Restricted Project
samparker added a comment to D48278: [SelectionDAG]Reduce masked data movement chains and memory access widths pt2.

Hi Diogo,

Tue, Jun 19, 4:11 AM
samparker added inline comments to D46749: [SelectionDAG]Reduce masked data movement chains and memory access widths.
Tue, Jun 19, 2:55 AM
samparker added a comment to D46749: [SelectionDAG]Reduce masked data movement chains and memory access widths.

Hi Diogo,

Tue, Jun 19, 2:40 AM
samparker added a comment to D48128: [ARM] Parallel DSP IR Pass.

Hi Sjoerd,

Tue, Jun 19, 1:03 AM
samparker abandoned D48270: [ARM] Check for unaligned access via bitcasts.

Many thanks Eli!

Tue, Jun 19, 12:59 AM

Mon, Jun 18

samparker created D48270: [ARM] Check for unaligned access via bitcasts.
Mon, Jun 18, 1:49 AM

Thu, Jun 14

samparker added inline comments to D48128: [ARM] Parallel DSP IR Pass.
Thu, Jun 14, 2:15 AM

Wed, Jun 13

samparker added a comment to D48128: [ARM] Parallel DSP IR Pass.

Hi Sjoerd,

Wed, Jun 13, 8:59 AM

Mon, Jun 11

samparker added inline comments to D47716: [AArch64][SVE] Asm: Support for saturating INC/DEC (32bit scalar) instructions..
Mon, Jun 11, 2:11 AM

Fri, Jun 8

samparker added inline comments to D45439: [IRCE] Use NUW flag for indvar.
Fri, Jun 8, 2:25 AM
samparker added inline comments to D47730: [SelectionDAG]Reduce masked data movement chains and memory access widths pt3.
Fri, Jun 8, 2:12 AM · Restricted Project

Thu, Jun 7

samparker updated the diff for D47878: [DAGCombiner] Fix for PR37667.

Thanks for the feedback. I've removed my new test and updated the existed one. Also modified the code style.

Thu, Jun 7, 8:35 AM
samparker added a comment to D46749: [SelectionDAG]Reduce masked data movement chains and memory access widths.

Hi Diogo,

Thu, Jun 7, 8:02 AM
samparker added a comment to D46749: [SelectionDAG]Reduce masked data movement chains and memory access widths.

Hi Diogo,

Thu, Jun 7, 5:28 AM
samparker created D47878: [DAGCombiner] Fix for PR37667.
Thu, Jun 7, 5:15 AM

May 21 2018

samparker added a comment to D46749: [SelectionDAG]Reduce masked data movement chains and memory access widths.

Hi Diogo,

May 21 2018, 4:03 AM

May 16 2018

samparker accepted D46860: [IRCE] Fix miscompile with range checks against negative values.

LGTM.

May 16 2018, 3:11 AM

May 10 2018

samparker accepted D46591: [AArch64] Fix performPostLD1Combine to check for constant lane index..

LGTM, thanks!

May 10 2018, 12:49 AM

May 9 2018

samparker added inline comments to D46591: [AArch64] Fix performPostLD1Combine to check for constant lane index..
May 9 2018, 2:14 AM

May 4 2018

samparker accepted rL331508: [IRCE] Fix misuse of dyn_cast which leads to UB.

LGTM, thanks Max!

May 4 2018, 1:05 AM

May 2 2018

samparker accepted D46269: [AArch64][SVE] Asm: Support for non-temporal, contiguous LDNT1/STNT1 load/store instructions..

LGTM, cheers.

May 2 2018, 1:38 AM

May 1 2018

samparker accepted D46270: [AArch64][SVE] Asm: Support for LDR/STR fill and spill instructions..

I had missed that the output operands where not the same, indeed it's not convenient and readability is also a valid reason.

May 1 2018, 8:47 AM
samparker added a comment to D46270: [AArch64][SVE] Asm: Support for LDR/STR fill and spill instructions..

Hi Sander,

May 1 2018, 1:48 AM

Apr 30 2018

samparker added a comment to D46121: [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+scalar) store instructions..

Ah, thanks for clearing that up for me.

Apr 30 2018, 5:24 AM
samparker added a comment to D46121: [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+scalar) store instructions..

Ok, for my sanity, I don't think the document descriptions match up, do you agree? The useful link you pointed me to only shows Xm as the scalar index, but 5.2.2 of the PDF supplement shows that the index can be scaled with LSL.

Apr 30 2018, 2:34 AM
samparker added a comment to D46121: [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+scalar) store instructions..

Thanks!

Apr 30 2018, 2:20 AM
samparker added a comment to D46121: [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+scalar) store instructions..

Hi Sander,

Apr 30 2018, 1:58 AM

Apr 27 2018

samparker accepted D46122: [AArch64][AsmParser] NFC: Cleanup of addOperands functions.

Great stuff, LGTM.

Apr 27 2018, 12:58 AM

Apr 18 2018

samparker added inline comments to D45617: [IRCE] Only check for NSW on equality predicates.
Apr 18 2018, 6:52 AM
samparker accepted D45687: [AArch64][AsmParser] NFC: Cleanup parsing of scalar registers..

Hi Sander,

Apr 18 2018, 1:33 AM

Apr 17 2018

samparker accepted D45724: [ARM] Add some missing FP16 VSEL test cases.

I think you're fine to commit tests without review.

Apr 17 2018, 8:10 AM

Apr 16 2018

samparker added inline comments to D45439: [IRCE] Use NUW flag for indvar.
Apr 16 2018, 2:52 AM

Apr 13 2018

samparker accepted D44675: [ARM] Codegen FP16 vmaxnm/vminnm scalar instructions.

LGTM, cheers!

Apr 13 2018, 8:32 AM
samparker updated the diff for D45439: [IRCE] Use NUW flag for indvar.

Now that we're only looking for nsw with equality predicates, we should now be able to use nuw as well as nsw. HasNoSignedWrap has been renamed and queries hasNoSelfWrap, while still attempting to also search for nsw.

Apr 13 2018, 6:19 AM
samparker added a dependent revision for D45617: [IRCE] Only check for NSW on equality predicates: D45439: [IRCE] Use NUW flag for indvar.
Apr 13 2018, 5:57 AM
samparker added a dependency for D45439: [IRCE] Use NUW flag for indvar: D45617: [IRCE] Only check for NSW on equality predicates.
Apr 13 2018, 5:57 AM
samparker created D45617: [IRCE] Only check for NSW on equality predicates.
Apr 13 2018, 4:33 AM
samparker added a comment to D45439: [IRCE] Use NUW flag for indvar.

Sure Max, thanks for doing the testing.

Apr 13 2018, 4:00 AM
samparker added a comment to D44675: [ARM] Codegen FP16 vmaxnm/vminnm scalar instructions.

Hi Sjoerd,

Apr 13 2018, 12:12 AM

Apr 12 2018

samparker added a comment to D45439: [IRCE] Use NUW flag for indvar.

After starting and playing around for the day, I've got to the root question of: why do we do the wrap checks anyway? Aren't the following range checks in the IsIncreasing/Decreasing blocks enough?

Apr 12 2018, 7:46 AM
samparker added inline comments to D44675: [ARM] Codegen FP16 vmaxnm/vminnm scalar instructions.
Apr 12 2018, 1:52 AM
samparker added a comment to D45439: [IRCE] Use NUW flag for indvar.

Hi Max,

Apr 12 2018, 12:54 AM

Apr 10 2018

samparker added inline comments to D45439: [IRCE] Use NUW flag for indvar.
Apr 10 2018, 9:03 AM
samparker added inline comments to D45439: [IRCE] Use NUW flag for indvar.
Apr 10 2018, 6:55 AM
samparker updated the diff for D45439: [IRCE] Use NUW flag for indvar.

Split the helper function out to D45481 and rebased.

Apr 10 2018, 3:36 AM
samparker created D45481: [IRCE] isKnownNonNegative helper.
Apr 10 2018, 3:20 AM
samparker added inline comments to D45439: [IRCE] Use NUW flag for indvar.
Apr 10 2018, 1:08 AM

Apr 9 2018

samparker added a reviewer for D45439: [IRCE] Use NUW flag for indvar: sanjoy.
Apr 9 2018, 7:38 AM
samparker created D45439: [IRCE] Use NUW flag for indvar.
Apr 9 2018, 6:48 AM
samparker added a comment to D41350: [DAGCombine] Improve ReduceLoadWidth for SRL.

Thanks. Yes, I will do.

Apr 9 2018, 12:43 AM

Apr 6 2018

samparker updated subscribers of D41350: [DAGCombine] Improve ReduceLoadWidth for SRL.
Apr 6 2018, 8:02 AM
samparker updated the diff for D41350: [DAGCombine] Improve ReduceLoadWidth for SRL.

The trunc_i64_mask_srl test has been added. This example showed that I had a typo in my patch, I was checking the user of N and not 'N0'! So I've also renamed some variables to reduce the chance of possible confusion again.

Apr 6 2018, 7:59 AM
samparker reopened D41350: [DAGCombine] Improve ReduceLoadWidth for SRL.

I kindly got a reproducer from @nemanjai so now I've, hopefully, sorted out the issue that was causing big endian stage two builders to fail.

Apr 6 2018, 7:55 AM
samparker accepted D45362: [IRCE] Relax restriction on collected range checks.

Hi Max,

Apr 6 2018, 5:16 AM

Apr 4 2018

samparker added a comment to D41953: [LoopUnroll] Unroll and Jam.

Hi Dave,

Apr 4 2018, 2:38 AM
samparker accepted D45209: [LoopInterchange] Add stats counter for number of interchanged loops..

LGTM

Apr 4 2018, 1:33 AM
samparker accepted D44573: [AArch64] Add patterns matching (fabs (fsub x y)) to (fabd x y).

LGTM.

Apr 4 2018, 12:36 AM

Apr 3 2018

samparker added a comment to D44402: [DAGCombiner] Fold (zext (and/or/xor (shl/shr (load x), cst), cst)).

Sorry for the delay, LGTM. Thanks.

Apr 3 2018, 9:13 AM

Mar 26 2018

samparker added inline comments to D44402: [DAGCombiner] Fold (zext (and/or/xor (shl/shr (load x), cst), cst)).
Mar 26 2018, 8:02 AM
samparker added inline comments to D44776: [IRCE] Enable decreasing loops of variable bounds.
Mar 26 2018, 3:37 AM
samparker added a comment to rL328480: [IRCE] Enable increasing loops of variable bounds.

Review: https://reviews.llvm.org/D44515

Mar 26 2018, 2:54 AM
samparker added a comment to D41953: [LoopUnroll] Unroll and Jam.

Hi Dave,

Mar 26 2018, 2:46 AM
samparker accepted D44818: [LoopUnroll] Fix dangling pointers in SCEV.

Makes sense, LGTM.

Mar 26 2018, 2:38 AM
samparker closed D44515: [IRCE] Change min value safety check.

Committed in https://reviews.llvm.org/rL328480

Mar 26 2018, 2:33 AM

Mar 22 2018

samparker created D44776: [IRCE] Enable decreasing loops of variable bounds.
Mar 22 2018, 4:01 AM
samparker added a comment to D44515: [IRCE] Change min value safety check.

Thanks for the review and your help. I'll make the changes and commit at the start of next week. I'll also prepare the patch for the decreasing case.

Mar 22 2018, 1:28 AM

Mar 21 2018

samparker updated the diff for D44515: [IRCE] Change min value safety check.

Hi Max,

Mar 21 2018, 3:14 AM

Mar 20 2018

samparker added a comment to D44675: [ARM] Codegen FP16 vmaxnm/vminnm scalar instructions.

Hi Sjoerd,

Mar 20 2018, 10:15 AM
samparker updated the diff for D44515: [IRCE] Change min value safety check.

Slight format change and added AvailableAtLoopEntry check in CannotBeMinInLoop.

Mar 20 2018, 9:30 AM
samparker updated the diff for D44515: [IRCE] Change min value safety check.

Thanks Max, I've now:

  • corrected the loop guard logic, including using the entry instead of backedge guard.
  • extracted the bound checking into one function, merging the Max check into it.
Mar 20 2018, 8:03 AM
samparker added inline comments to D44515: [IRCE] Change min value safety check.
Mar 20 2018, 4:55 AM
samparker added inline comments to D44515: [IRCE] Change min value safety check.
Mar 20 2018, 3:40 AM

Mar 19 2018

samparker updated the diff for D44515: [IRCE] Change min value safety check.

I've replaced SumCanReachMax with SumCannotBeMaxInLoop, which uses similar logic to the new CannotBeMinInLoop, querying SCEV's LoopBackedgeGuardedBy. These two updated checks are need together to get this to work. Other changes:

  • Removed whitespace.
  • re-inserted the range metadata into test.
  • bracket style changes
Mar 19 2018, 8:10 AM

Mar 16 2018

samparker updated the diff for D44515: [IRCE] Change min value safety check.

Thanks for the comments, I've made these changes:

  • CanBeMin has now been replaced with CannotBeMinInLoop.
  • The function arguments have been renamed and reordered.
  • KnownNonNegative check removed.
  • debug comments removed.
Mar 16 2018, 6:57 AM
samparker added inline comments to D44515: [IRCE] Change min value safety check.
Mar 16 2018, 6:10 AM

Mar 15 2018

samparker accepted D44518: [ARM] FP16 codegen support for VSEL.

Hi Sjoerd, this LGTM.

Mar 15 2018, 8:04 AM
samparker updated the diff for D44515: [IRCE] Change min value safety check.

Added forgotten test.

Mar 15 2018, 6:03 AM
samparker created D44515: [IRCE] Change min value safety check.
Mar 15 2018, 5:58 AM
samparker accepted D44490: [AArch64] Implement getArithmeticReductionCost.

I'm happy to see this! LGTM with just one small comment, no need to re-review. Thanks!

Mar 15 2018, 2:23 AM
samparker accepted D44402: [DAGCombiner] Fold (zext (and/or/xor (shl/shr (load x), cst), cst)).

Thanks, LGTM.

Mar 15 2018, 2:08 AM

Mar 13 2018

samparker added inline comments to D44402: [DAGCombiner] Fold (zext (and/or/xor (shl/shr (load x), cst), cst)).
Mar 13 2018, 2:39 AM

Mar 12 2018

samparker added a comment to D44098: [ARM] Relax condition for PerformSHLSimplify.

Could you provide me with an example to illustrate your concern please? I keep going around in circles and I just see either the number of instructions or register pressure being reduced. Could the codegen of my new tests be improved?

Mar 12 2018, 7:57 AM

Mar 8 2018

samparker added a comment to D43876: [LoopUnroll] Peel off iterations if it makes conditions true/false..

Yes, this is a really nice approach for lower constant bounds. My transform selects a region of conditionally executed blocks and then attempts to hoist conditional statements into the head block of that region. Currently I can find loop unrolled induction variable idioms as well as finding a connected path of conditional values. From there I can produce a fast path free of compares and branches, as well as leaving the original code as a fallback. I also split and remove selects because performing conditional moves is still expensive on our small cores as well as the increased register pressure they create.

Mar 8 2018, 1:58 AM
samparker added a comment to D43876: [LoopUnroll] Peel off iterations if it makes conditions true/false..

Just FYI, I am also currently working on a pass to handle slightly more generic cases within the loop body, such like:

Mar 8 2018, 1:09 AM

Mar 7 2018

samparker added inline comments to D44098: [ARM] Relax condition for PerformSHLSimplify.
Mar 7 2018, 6:24 AM
samparker updated the diff for D44098: [ARM] Relax condition for PerformSHLSimplify.

Hi John,

Mar 7 2018, 6:23 AM
samparker added a comment to D44098: [ARM] Relax condition for PerformSHLSimplify.

Thanks John, I'll try those changes.

Mar 7 2018, 12:40 AM

Mar 6 2018

samparker updated the diff for D44097: [ARM] Fix for PR36577.

Fixed typo.

Mar 6 2018, 1:34 AM
samparker added inline comments to D44043: [DAGCombine] Remove AND in SETCC if we can prove they are unneeded.
Mar 6 2018, 1:28 AM

Mar 5 2018

samparker added a reviewer for D44097: [ARM] Fix for PR36577: john.brawn.
Mar 5 2018, 8:57 AM
samparker added a dependency for D44098: [ARM] Relax condition for PerformSHLSimplify: D44097: [ARM] Fix for PR36577.
Mar 5 2018, 8:57 AM
samparker added a dependent revision for D44097: [ARM] Fix for PR36577: D44098: [ARM] Relax condition for PerformSHLSimplify.
Mar 5 2018, 8:57 AM
samparker created D44098: [ARM] Relax condition for PerformSHLSimplify.
Mar 5 2018, 8:57 AM
samparker created D44097: [ARM] Fix for PR36577.
Mar 5 2018, 8:50 AM

Feb 23 2018

samparker accepted D42970: [ARM] Fix codegen for VLD3/VLD4/VST3/VST4 with WB.

LGTM, thanks.

Feb 23 2018, 4:58 AM