samparker (Sam Parker)
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User Since
May 11 2015, 7:59 AM (170 w, 6 d)

Recent Activity

Thu, Aug 16

samparker accepted D50846: [ARM][NFC] ARMCodeGenPrepare: some refactoring and algorithm description..

Thanks for putting the time into this, just one nit before its committed please.

Thu, Aug 16, 8:51 AM
samparker closed D50067: [ARM] Handle signed icmps in ARMCodeGenPrepare.

Fixed and recommitted in r339858.

Thu, Aug 16, 5:06 AM
samparker updated the diff for D50432: [DAGCombiner] Reduce load widths of shifted masks.

Re-adjusted ShAmt for big endian targets.

Thu, Aug 16, 3:44 AM
samparker added inline comments to D50432: [DAGCombiner] Reduce load widths of shifted masks.
Thu, Aug 16, 3:09 AM
samparker updated the diff for D50067: [ARM] Handle signed icmps in ARMCodeGenPrepare.

Thanks for reverting. The issue was that I was assuming that the instruction operands mapped to arguments for CallInsts. Will be recommitting.

Thu, Aug 16, 2:09 AM

Wed, Aug 15

samparker created D50769: [ARM] Typesize lower bound for ARMCodeGenPrepare.
Wed, Aug 15, 5:15 AM
samparker created D50762: [ARM] Ignore GEPs in ARMCodeGenPrepare.
Wed, Aug 15, 3:56 AM
samparker created D50759: [ARM] Allow zext in ARMCodeGenPrepare.
Wed, Aug 15, 2:59 AM
samparker created D50758: [ARM] Allow bitcasts in ARMCodeGenPrepare.
Wed, Aug 15, 2:05 AM
samparker updated the diff for D50067: [ARM] Handle signed icmps in ARMCodeGenPrepare.

Rebased.

Wed, Aug 15, 1:09 AM
samparker updated the diff for D50067: [ARM] Handle signed icmps in ARMCodeGenPrepare.

Changed test regexesess

Wed, Aug 15, 12:46 AM

Tue, Aug 14

samparker updated the diff for D50054: [ARM] Allow pointer values in ARMCodeGenPrepare.

Removed the unnecessary isa<Instruction> checks and updated the test to actually test.

Tue, Aug 14, 8:01 AM
samparker added inline comments to D50054: [ARM] Allow pointer values in ARMCodeGenPrepare.
Tue, Aug 14, 7:49 AM
samparker retitled D50054: [ARM] Allow pointer values in ARMCodeGenPrepare from [ARM] Ignore pointer values in ARMCodeGenPrepare to [ARM] Allow pointer values in ARMCodeGenPrepare.
Tue, Aug 14, 7:47 AM
samparker updated the diff for D50067: [ARM] Handle signed icmps in ARMCodeGenPrepare.

Rebased.

Tue, Aug 14, 7:21 AM
samparker updated the diff for D50054: [ARM] Allow pointer values in ARMCodeGenPrepare.

Rebased and fixed the handling of undef values. I've also moved the tests around so we have a standalone file for the call tests. Also added a small piece of control to decide whether we bother to promote or not: if we find nothing but sources, sinks and the icmp, then we don't bother doing anything.

Tue, Aug 14, 7:02 AM
samparker added inline comments to D50432: [DAGCombiner] Reduce load widths of shifted masks.
Tue, Aug 14, 5:13 AM
samparker updated the diff for D50432: [DAGCombiner] Reduce load widths of shifted masks.

Rebased and updated changes to the x86 codegen tests.

Tue, Aug 14, 5:12 AM
samparker added a reviewer for D50432: [DAGCombiner] Reduce load widths of shifted masks: john.brawn.
Tue, Aug 14, 1:20 AM
samparker accepted D50667: [ARM] Make PerformSHLSimplify add nodes to the DAG worklist correctly..

Thanks for fixing this, LGTM.

Tue, Aug 14, 12:16 AM

Fri, Aug 10

samparker updated the diff for D50518: [ARM] Disallow zexts in ARMCodeGenPrepare.
  • Removed commented out code
  • Added some TODOs
  • Expanded the description of what a source and sink are
Fri, Aug 10, 5:50 AM
samparker added inline comments to D50518: [ARM] Disallow zexts in ARMCodeGenPrepare.
Fri, Aug 10, 3:12 AM

Thu, Aug 9

samparker created D50518: [ARM] Disallow zexts in ARMCodeGenPrepare.
Thu, Aug 9, 9:17 AM
samparker accepted D50454: [ARM] FP16: codegen support for VTRN.

LGTM

Thu, Aug 9, 3:56 AM
samparker updated the diff for D50432: [DAGCombiner] Reduce load widths of shifted masks.

Moved arguments to occupy a single line.

Thu, Aug 9, 12:47 AM

Wed, Aug 8

samparker accepted D50427: [ARM] FP16: codegen support for VEXT.

LGTM

Wed, Aug 8, 5:01 AM
samparker accepted D50030: [ARM] Adjust AND immediates to make them cheaper to select..

Thanks for the extra tests, LGTM.

Wed, Aug 8, 4:51 AM
samparker updated the diff for D50079: [ARM] arm.codegen.zeroext intrinsics.

To try to make it clear that these are not user facing intrinsics, I've renamed them to arm.codegen.zeroext

Wed, Aug 8, 3:58 AM
samparker accepted D50329: [ARM] FP16: vector vmov and vdup support.

Ok, from your reply on the other ticket - LGTM.

Wed, Aug 8, 3:51 AM
samparker created D50432: [DAGCombiner] Reduce load widths of shifted masks.
Wed, Aug 8, 3:43 AM
samparker accepted D50326: [ARM] FP16: vector VMUL variants.

Cheers, shufflevector always confuses me. LGTM.

Wed, Aug 8, 3:03 AM
samparker accepted D50393: [ARM] FP16: support vector INT_TO_FP and FP_TO_INT.

LGTM

Wed, Aug 8, 1:37 AM
samparker added inline comments to D50329: [ARM] FP16: vector vmov and vdup support.
Wed, Aug 8, 1:30 AM
samparker added inline comments to D50326: [ARM] FP16: vector VMUL variants.
Wed, Aug 8, 1:17 AM

Thu, Aug 2

samparker added a comment to D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.

So this started life in the DAGCombiner and issues around the implementation were raised and that it would be useful to have earlier in the pipeline. But it seems that it hasn't really be thought, or discussion, about how this would fit well in the existing passes... I think DAG combine has always been the right place for this because we're trying to reuse values - something that DAGs are good for. In DAGCombiner::visitANDLike, we already handle ANDs with SRL operands and the motivating example can be addressed with very little effort:

Thu, Aug 2, 8:00 AM

Wed, Aug 1

samparker added a comment to D50079: [ARM] arm.codegen.zeroext intrinsics.

And what would I need to do about testing for a generic intrinsic? Add to BitCode/compatibility-6.0.ll test and just keep this codegen one too?

Wed, Aug 1, 3:46 AM
samparker added inline comments to D50030: [ARM] Adjust AND immediates to make them cheaper to select..
Wed, Aug 1, 3:33 AM
samparker added a comment to D50079: [ARM] arm.codegen.zeroext intrinsics.

Yes exactly, I would like to use these for loops. In ARMCodeGenPrepare I need to insert truncs to keep the IR legal, although I've already proved that the value is already zero extended. In those cases I want to use these intrinsics to carry that knowledge through. So it's not trying to work around the lack of info of target specific nodes. Another idea I wondered about was adding flags to instructions, but that seems far more intrusive.

Wed, Aug 1, 2:43 AM

Tue, Jul 31

samparker created D50079: [ARM] arm.codegen.zeroext intrinsics.
Tue, Jul 31, 9:54 AM
samparker created D50067: [ARM] Handle signed icmps in ARMCodeGenPrepare.
Tue, Jul 31, 7:36 AM
samparker created D50054: [ARM] Allow pointer values in ARMCodeGenPrepare.
Tue, Jul 31, 5:35 AM
samparker added a comment to D50030: [ARM] Adjust AND immediates to make them cheaper to select..

Hi Eli,

Tue, Jul 31, 5:13 AM

Wed, Jul 25

samparker accepted D49585: [ARM] Prefer lsls+lsrs over lsls+ands or lsrs+ands in Thumb1..

This LGTM. I don't think there's a problem with solving this niche in the backend.

Wed, Jul 25, 2:27 AM
samparker retitled D49239: [ARM]{WIP] SADD16 support in ParallelDSP from [ARM] SADD16 support in ParallelDSP to [ARM]{WIP] SADD16 support in ParallelDSP.
Wed, Jul 25, 1:10 AM

Tue, Jul 24

samparker added a comment to D49239: [ARM]{WIP] SADD16 support in ParallelDSP.

Is it such a bad idea? Sure, I would like to check whether the sel intrinsic has been used or not, but what happens in the case of inline assembly? The AAPCS is also vague, I'm not sure what a 'public interface' is in terms of an LLVM module. I'd like to have an option which is the user can be explicit in saying its fine to use these instructions.

Tue, Jul 24, 5:32 AM

Mon, Jul 23

samparker updated the diff for D49239: [ARM]{WIP] SADD16 support in ParallelDSP.

Added tests for:

  • non load operand to the add,
  • immediate operand to the add,
  • volatile store
  • non-consecutive loads
Mon, Jul 23, 9:10 AM
samparker updated the diff for D49239: [ARM]{WIP] SADD16 support in ParallelDSP.

Performed a rebase and added a test from a manually unrolled example. I've also added an option to control the use of the GE writing flags - really I think this should go as a subtarget feature so this can be used across this pass and ARMCodeGenPrepare.

Mon, Jul 23, 8:35 AM
samparker added inline comments to D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.
Mon, Jul 23, 7:13 AM
samparker updated the diff for D48832: [ARM] ARMCodeGenPrepare backend pass.

Added another test

Mon, Jul 23, 5:07 AM
samparker updated the diff for D48832: [ARM] ARMCodeGenPrepare backend pass.

Now disabled at -O0

Mon, Jul 23, 3:40 AM
samparker added inline comments to D49585: [ARM] Prefer lsls+lsrs over lsls+ands or lsrs+ands in Thumb1..
Mon, Jul 23, 2:47 AM

Jul 20 2018

samparker added a comment to D49585: [ARM] Prefer lsls+lsrs over lsls+ands or lsrs+ands in Thumb1..

I did some work for Thumb-2 last year in a similar vain during the combine phase, in PerformSHLSimplify, but this (unsurprisingly) doesn't handle lshr. I didn't find any headaches from changing the canonical form in those cases, so probably would be worth having it there.

Jul 20 2018, 3:31 AM
samparker updated subscribers of D32530: [SVE][IR] Scalable Vector IR Type.
Jul 20 2018, 2:41 AM
samparker added a comment to D49229: [AggressiveInstCombine] Fold redundant masking operations of shifted value.

All of your test cases are rooted at an or, so it makes sense to search up from there. Why not start with searching just from or (and xors?) and then add the search from more operators in later patches?

Jul 20 2018, 2:33 AM

Jul 19 2018

samparker accepted D49444: [DAG] Avoid Node Update assertion due to AND simplification.

LGTM, thanks!

Jul 19 2018, 12:49 AM

Jul 18 2018

samparker abandoned D49380: [ARM] Remove some code from PerformCMOVCombine.

Ok, thanks for the clarification. I'll have a look in instcombine.

Jul 18 2018, 8:39 AM
samparker updated the diff for D48832: [ARM] ARMCodeGenPrepare backend pass.

Fixed support for handling switch instructions and added another test.

Jul 18 2018, 8:26 AM
samparker added a comment to D49444: [DAG] Avoid Node Update assertion due to AND simplification.

This looks like an odd solution to me, I haven't seen TokenFactors used like that before. Isn't it okay for the AND to be folded? Why not just check that the AND hasn't be folded into a constant before trying to update its, now non-existent, operands?

Jul 18 2018, 4:55 AM
samparker updated the diff for D48832: [ARM] ARMCodeGenPrepare backend pass.

Fixed a couple of bugs around the truncating of values into the root users. Also added explicit checks to reject signed compares.

Jul 18 2018, 4:04 AM

Jul 17 2018

samparker updated the diff for D48832: [ARM] ARMCodeGenPrepare backend pass.

Now explicitly stating what values and opcodes we support. Also added some debug code around and removed the ShouldIgnore function.

Jul 17 2018, 8:06 AM
samparker updated the diff for D48832: [ARM] ARMCodeGenPrepare backend pass.

Moved a couple of functions into lambdas and added a couple of checks to reject ConstantExprs.

Jul 17 2018, 6:53 AM
samparker updated the diff for D48832: [ARM] ARMCodeGenPrepare backend pass.
  • Fixed the really bad typo that was allowing wrapping instructions, quite confused that this wasn't caught by my existing tests... so added more of them.
  • Added more type checking so we can catch the i64 issue
  • Added a couple more tests to show the current limitation too
Jul 17 2018, 4:03 AM
samparker added a comment to D49380: [ARM] Remove some code from PerformCMOVCombine.

I'm happy to move it somewhere general, but where would be suitable, InstCombine?

Jul 17 2018, 1:23 AM

Jul 16 2018

samparker created D49380: [ARM] Remove some code from PerformCMOVCombine.
Jul 16 2018, 8:22 AM
samparker updated the diff for D48832: [ARM] ARMCodeGenPrepare backend pass.

Hi Sjoerd,

Jul 16 2018, 5:59 AM

Jul 12 2018

samparker added a comment to D49239: [ARM]{WIP] SADD16 support in ParallelDSP.

I appreciate the tests here are a little lacking, I will add something for:

  • volatile stores,
  • non-consecutive stores,
  • adding a constant,
  • decrementing indvar,
  • a test from manually unrolled piece of source.
Jul 12 2018, 8:37 AM
samparker added reviewers for D49239: [ARM]{WIP] SADD16 support in ParallelDSP: john.brawn, dmgreen.
Jul 12 2018, 8:29 AM
samparker added a dependent revision for D49020: [ARM] ParallelDSP reorganisation: D49239: [ARM]{WIP] SADD16 support in ParallelDSP.
Jul 12 2018, 8:07 AM
samparker added a dependency for D49239: [ARM]{WIP] SADD16 support in ParallelDSP: D49020: [ARM] ParallelDSP reorganisation.
Jul 12 2018, 8:07 AM
samparker created D49239: [ARM]{WIP] SADD16 support in ParallelDSP.
Jul 12 2018, 8:07 AM
samparker added a comment to D48832: [ARM] ARMCodeGenPrepare backend pass.

Many thanks for those!

Jul 12 2018, 2:57 AM

Jul 11 2018

samparker removed a reviewer for D33935: Allow rematerialization of ARM Thumb MOVi8 instruction in some contexts: samparker.
Jul 11 2018, 7:12 AM
samparker removed a reviewer for D35481: Fix documentation of MachineInstr::getNumOperands: samparker.
Jul 11 2018, 7:12 AM
samparker abandoned D48972: [ARM][NFC] ParallelDSP tweaks.

Merging changes into D49020 since it was easier to do with a rebase.

Jul 11 2018, 7:11 AM
samparker updated the diff for D49020: [ARM] ParallelDSP reorganisation.

Combined changes from D48972 and performed a rebase.

Jul 11 2018, 7:10 AM
samparker accepted D49125: [ARM] ParallelDSP: multiple reduction stmts in loop.

Cheers!

Jul 11 2018, 3:52 AM
samparker updated the diff for D48832: [ARM] ARMCodeGenPrepare backend pass.

Added comments to describe the purpose of some of the tests.

Jul 11 2018, 3:44 AM

Jul 10 2018

samparker added a comment to D49125: [ARM] ParallelDSP: multiple reduction stmts in loop.

I still think you're overcomplicating things here... Keeping the ReadOnly flag, you can then just check what's writing to memory in the rest of the block:

Jul 10 2018, 9:44 AM
samparker added inline comments to D49125: [ARM] ParallelDSP: multiple reduction stmts in loop.
Jul 10 2018, 3:22 AM
samparker accepted D48907: [ARM] Treat cmn immediates as legal in isLegalICmpImmediate..

LGTM, thanks.

Jul 10 2018, 2:49 AM

Jul 6 2018

samparker updated the diff for D49020: [ARM] ParallelDSP reorganisation.

Added loop to destroy the MACCandidates.

Jul 6 2018, 6:42 AM
samparker added inline comments to D49020: [ARM] ParallelDSP reorganisation.
Jul 6 2018, 6:32 AM
samparker added a dependency for D49020: [ARM] ParallelDSP reorganisation: D48972: [ARM][NFC] ParallelDSP tweaks.
Jul 6 2018, 4:55 AM
samparker added a dependent revision for D48972: [ARM][NFC] ParallelDSP tweaks: D49020: [ARM] ParallelDSP reorganisation.
Jul 6 2018, 4:55 AM
samparker created D49020: [ARM] ParallelDSP reorganisation.
Jul 6 2018, 4:55 AM
samparker accepted D48922: [AArch64] Armv8.4-A: TLB support.

LGTM

Jul 6 2018, 2:23 AM
samparker updated the diff for D48972: [ARM][NFC] ParallelDSP tweaks.

Renamed BinOpSequence to BinOpChain and replaced MACCandidates with Candidates in the Alias functions.

Jul 6 2018, 1:00 AM
samparker accepted D48918: [AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction.

Okay, looks fine and like ISB :) Thanks for also adding a bit of 8.3 in there too!

Jul 6 2018, 12:50 AM
samparker updated the diff for D48832: [ARM] ARMCodeGenPrepare backend pass.

Cheers John! Moved, removed or localised variables and implemented getAnalysisUsage.

Jul 6 2018, 12:13 AM
samparker added inline comments to D48907: [ARM] Treat cmn immediates as legal in isLegalICmpImmediate..
Jul 6 2018, 12:00 AM

Jul 5 2018

samparker accepted D48971: [ARM] ParallelDSP: added statistics, NFC..

LGTM.

Jul 5 2018, 11:39 PM
samparker created D48972: [ARM][NFC] ParallelDSP tweaks.
Jul 5 2018, 7:38 AM
samparker accepted D48278: [SelectionDAG] Fold redundant masking operations of shifted value.

LGTM. For future reference, and before committing, arm and aarch64 tests live in different codegen directories so please separate the test into the two sub-directories. Thanks!

Jul 5 2018, 1:24 AM
samparker accepted D48944: [ARM] ParallelDSP: only support i16 loads for now..

LGTM

Jul 5 2018, 12:59 AM

Jul 4 2018

samparker accepted D48926: [AArch64] Armv8.4-A: Flag manipulation instructions.

LGTM

Jul 4 2018, 3:05 AM
samparker added inline comments to D48907: [ARM] Treat cmn immediates as legal in isLegalICmpImmediate..
Jul 4 2018, 2:37 AM

Jul 3 2018

samparker added inline comments to D48872: [ARM][NFC] Refactor sequential access for DSP.
Jul 3 2018, 5:36 AM
samparker created D48872: [ARM][NFC] Refactor sequential access for DSP.
Jul 3 2018, 4:19 AM
samparker updated the diff for D48832: [ARM] ARMCodeGenPrepare backend pass.

Changes:

  • fixed typos,
  • changed the names and default setting of the options, the generation of uadd and usub are now disabled by default.
  • moved icmp handling code out of isSigned and into isPromotedResultSafe.
  • added another target to test the default command line options.
Jul 3 2018, 3:25 AM
samparker added inline comments to D48832: [ARM] ARMCodeGenPrepare backend pass.
Jul 3 2018, 3:19 AM