- User Since
- May 11 2015, 7:59 AM (197 w, 2 d)
Fri, Feb 15
Thu, Feb 14
Updated the test labels. The AND that is used to convert the trunc still becomes a uxtb, so we just need to check that there's one after the division.
Wed, Feb 13
Tue, Feb 12
Mon, Feb 11
Fri, Feb 8
I've opted for putting the pattern in ARMInstrInfo once everything has been included. Also added encodings to the test to ensure we're now using the correct movw.
Well, I'll still have the problem that tSUBrr is defined in the other file =/
Before I put this in ISelDAGToDAG, is there a way to reference machine instructions from across different tablegen files..?
Thu, Feb 7
Thanks to you both.
Will do. Thanks for the review!
Added doxygen comment.
Removed the setter and instead changed the subtarget map key.
Wed, Feb 6
updated member description
Added method setOptMinSize which is set in getSubtargetImpl.
Ah yes, good point! I'll make the change.
Tue, Feb 5
Made some simplifications:
- reset isProfitableChain.
- reset FinalizeChain so that the tail is added to the chain again.
- removed the CollapseUnrolled option because with the reset in changes, it wasn't really interesting.
Mon, Feb 4
Fri, Feb 1
I like that idea, I think moving the logic into ARMISelLowering would be good as we already use similar logic there too.
Thu, Jan 31
LGTM with one comment.
It looks like APInt doesn't function the way I expected, nor in the way that the other authors of this area would have expected. I've posted a query: http://lists.llvm.org/pipermail/llvm-dev/2019-January/129781.html
Wed, Jan 30
Some tests to follow...
Tue, Jan 29
Mon, Jan 28
Changed the builtins to use W instead of LL. I've also updated the tests, adding a test for rbitl.
Thu, Jan 24
Wed, Jan 23
Tue, Jan 22
Cheers, added some comments and removed whitespace.
Thanks for your suggestion Eli, that works for me.
Jan 18 2019
Updated wsr, rsr and rbit
Jan 17 2019
Jan 16 2019
Jan 15 2019
Removed changes to the complexity.ll test.
Changed the method of creating the final shl.
Jan 14 2019
Thanks. Yes, I think this is to do with the way I try to insert the new shl node, the DAG is just returning the existing node hence we only have one shl node. Should have a patch up tomorrow.
Could you please describe more accurately what you are expecting to see? I'm failing to see the issue.
Jan 11 2019
Changed the default value for the command line option 'EnableBackedgeIndexing' to false.
some renaming, renamed post inc bits to 'index'.
- Added a command line option to 'EnableBackedgePostIncs'.
- Added a command line option to enable narrowing the search space by collapsing unrolled code.
- The TTI hook now accepts the loop so that the target can make a more informed decision on when it 'shouldFavorBackedgePostIncs'.
- LSRInstance contains a boolean 'FavorBackedgePostInc' which is equal to EnableBackedgePostIncs && shouldFavorBackedgePostIncs.
- When FavorBackedgePostIncs: > Generate the new constant offsets. > In RateRegister, the LoopCost is now set to 0 if the step recurrence is equal to the base offset of the parent formula. > IsProfitableChain has a higher limit > The last expression in the IVChain is not added to IVIncSet so it's a target for optimising.
Jan 9 2019
Thanks Eli, I've updated the test case and set isDead.
Jan 7 2019
The mir test isn't producing the IT block, and I'm unsure why and how to get this to work. That's why I've only included the first test which is to check the IT block.
- corrected original teq test
- added mir test
Jan 3 2019
Dec 31 2018
Dec 21 2018
Dec 19 2018
Dec 12 2018
I've moved the logic under the control of a new TTI flag as it seems that the current shouldFavourPostInc is trying to achieve different things. Hopefully I've also addressed Gil's comments.
Dec 11 2018
Okay, thanks. We're also seeing some regressions, so I know I've got some tuning to do. Do you have any idea of the characteristics of your regressions? At the moment I'm thinking:
- That the costs that I've added here are overly simplistic, for one I think I need to add a setup cost.
- It's also probably not worth doing when we know that the loop iteration count is low.
- In the current state, we also see code size regressions whereas your previous work helps us reduce code size. It may mean that I'll need a different flag to enable this change, but it also maybe a symptom of the performance regressions.
Dec 6 2018
Nov 30 2018
Ah, ok, I don't think they're being generated. I will have a look at GenerateConstantOffsetsImpl. Thanks!
Nov 29 2018
@qcolombet maybe you could suggest the areas in LSR which will enable to help produce these post inc loads? What we have with the default complexity is:
Nov 28 2018
Great to see those other test changes! LGTM with the few minor comments, no need to re-review. cheers!
Thanks for the explanation, LGTM!
Thanks for taking a look and for the value renamer tip! The test case has now been renamed and reduced.
Nov 27 2018
My point was that, even though this extra work and as you mentioned in the comments, the test case isn't generating optimum code. We could introduce a subs node to remove the unnecessary cmp, making the sub opaque and improving codegen. Unless there's a reason why we couldn't do this?
Nov 26 2018
Nov 23 2018