[ARM] add new LLVM addressing modes for v8.1-M and MVE.

[simon_tatham]

Summary

There's a new mode for the BF instruction, and another three for MVE
vector loads, which take a 7-bit immediate offset scaled by 1, 2 or 4.

[t.p.northover]

This should probably be combined with the first patch that uses these addressing modes so that it can be tested.

llvm/lib/Target/ARM/ARMInstrFormats.td

112

Why no T2?

[simon_tatham]

llvm/lib/Target/ARM/ARMInstrFormats.td

112

I think just because there's no BF in any other instruction set to need to distinguish it from. I can add "T2" in the name anyway if you prefer.

[ostannard]

llvm/lib/Target/ARM/ARMInstrFormats.td

112

Do we actually need an AddrMode for BF? All of the uses of them I've seen are for loads and stores, and I don't think we have any AddrModes for existing branches.

[simon_tatham]

In D60701#1466821, @t.p.northover wrote:

This should probably be combined with the first patch that uses these addressing modes so that it can be tested.

Fair enough. I've folded it into the new D62680.

llvm/lib/Target/ARM/ARMInstrFormats.td

 def AddrModeT2_i12  : AddrMode<11>;
 def AddrModeT2_i8   : AddrMode<12>;
 def AddrModeT2_so   : AddrMode<13>;
 def AddrModeT2_pc   : AddrMode<14>;
 def AddrModeT2_i8s4 : AddrMode<15>;
 def AddrMode_i12    : AddrMode<16>;
 def AddrMode5FP16   : AddrMode<17>;
 def AddrModeT2_ldrex : AddrMode<18>;
+def AddrMode_bf     : AddrMode<19>;
+def AddrModeT2_i7s4 : AddrMode<20>;
+def AddrModeT2_i7s2 : AddrMode<21>;
+def AddrModeT2_i7   : AddrMode<22>;
 
 // Load / store index mode.
 class IndexMode<bits<2> val> {
   bits<2> Value = val;
 }
 def IndexModeNone : IndexMode<0>;
 def IndexModePre  : IndexMode<1>;
 def IndexModePost : IndexMode<2>;

llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h

enum AddrMode {
     AddrModeT2_i12  = 11,
     AddrModeT2_i8   = 12,
     AddrModeT2_so   = 13,
     AddrModeT2_pc   = 14, // +/- i12 for pc relative data
     AddrModeT2_i8s4 = 15, // i8 * 4
     AddrMode_i12    = 16,
     AddrMode5FP16   = 17,  // i8 * 2
     AddrModeT2_ldrex = 18, // i8 * 4, with unscaled offset in MCInst
+    AddrMode_bf     = 19,
+    AddrModeT2_i7s4 = 20, // i7 * 4
+    AddrModeT2_i7s2 = 21, // i7 * 2
+    AddrModeT2_i7   = 22, // i7 * 1
   };
 
   inline static const char *AddrModeToString(AddrMode addrmode) {
     switch (addrmode) {
     case AddrModeNone:    return "AddrModeNone";
     case AddrMode1:       return "AddrMode1";
     case AddrMode2:       return "AddrMode2";
     case AddrMode3:       return "AddrMode3";
     case AddrMode4:       return "AddrMode4";
     case AddrMode5:       return "AddrMode5";
     case AddrMode5FP16:   return "AddrMode5FP16";
     case AddrMode6:       return "AddrMode6";
     case AddrModeT1_1:    return "AddrModeT1_1";
     case AddrModeT1_2:    return "AddrModeT1_2";
     case AddrModeT1_4:    return "AddrModeT1_4";
     case AddrModeT1_s:    return "AddrModeT1_s";
     case AddrModeT2_i12:  return "AddrModeT2_i12";
     case AddrModeT2_i8:   return "AddrModeT2_i8";
     case AddrModeT2_so:   return "AddrModeT2_so";
     case AddrModeT2_pc:   return "AddrModeT2_pc";
     case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
     case AddrMode_i12:    return "AddrMode_i12";
     case AddrModeT2_ldrex:return "AddrModeT2_ldrex";
+    case AddrMode_bf:     return "AddrMode_bf";
+    case AddrModeT2_i7s4: return "AddrModeT2_i7s4";
+    case AddrModeT2_i7s2: return "AddrModeT2_i7s2";
+    case AddrModeT2_i7:   return "AddrModeT2_i7";
     }
   }
 
   /// Target Operand Flag enum.
   enum TOF {
     //===------------------------------------------------------------------===//
     // ARM Specific MachineOperand flags.
 

llvm/lib/Target/ARM/Thumb2InstrInfo.cpp

if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
       NumBits = 8;
       Scale = 2;
       Offset += InstrOffs * 2;
       assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
       if (Offset < 0) {
         Offset = -Offset;
         isSub = true;
       }
+    } else if (AddrMode == ARMII::AddrModeT2_i7s4 ||
+               AddrMode == ARMII::AddrModeT2_i7s2 ||
+               AddrMode == ARMII::AddrModeT2_i7) {
+      Offset += MI.getOperand(FrameRegIdx + 1).getImm();
+      NumBits = 7;
+      unsigned OffsetMask = 0x0;
+      switch (AddrMode) {
+      case ARMII::AddrModeT2_i7s4: NumBits += 2; OffsetMask = 0x3; break;
+      case ARMII::AddrModeT2_i7s2: NumBits += 1; OffsetMask = 0x1; break;
+      }
+      // MCInst operand expects already scaled value.
+      Scale = 1;
+      assert((Offset & OffsetMask) == 0 && "Can't encode this offset!");
     } else if (AddrMode == ARMII::AddrModeT2_i8s4) {
       Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
-      NumBits = 10; // 8 bits scaled by 4
+      NumBits = 8 + 2;
       // MCInst operand expects already scaled value.
       Scale = 1;
       assert((Offset & 3) == 0 && "Can't encode this offset!");
     } else if (AddrMode == ARMII::AddrModeT2_ldrex) {
       Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
       NumBits = 8; // 8 bits scaled by 4
       Scale = 4;
       assert((Offset & 3) == 0 && "Can't encode this offset!");