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[ARM] add new LLVM addressing modes for v8.1-M and MVE.
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Authored by simon_tatham on Apr 15 2019, 5:58 AM.



There's a new mode for the BF instruction, and another three for MVE
vector loads, which take a 7-bit immediate offset scaled by 1, 2 or 4.

Event Timeline

simon_tatham created this revision.Apr 15 2019, 5:58 AM

This should probably be combined with the first patch that uses these addressing modes so that it can be tested.


Why no T2?

simon_tatham added inline comments.Apr 16 2019, 1:57 AM

I think just because there's no BF in any other instruction set to need to distinguish it from. I can add "T2" in the name anyway if you prefer.

ostannard added inline comments.

Do we actually need an AddrMode for BF? All of the uses of them I've seen are for loads and stores, and I don't think we have any AddrModes for existing branches.