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[ARM] implement 8.1-M instructions at the MC level.
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Authored by simon_tatham on Apr 15 2019, 6:00 AM.

Details

Summary

This commit adds the entire 8.1-M and MVE instruction set.

Most of the new instructions are MVE; those all live in a new tablegen
source file ARMInstrMVE.td. A few FP but non-MVE instructions are
added in ARMInstrVFP.td (VSCCLRM, and loads/stores/moves of a couple
of VFP system registers), and a few non-MVE and non-FP instructions in
ARMInstrThumb2.td (CLRM, the BF and LOL families, and CSEL).

The most complicated thing in the MVE instructions is that a lot of
them take a standard cluster of extra operations to support VPT
predication. Those are defined in ARMInstrFormats.td, under the names
'vpred_n' and 'vpred_r', with a comment explaining what they do.

A change to existing instructions in ARMInstrThumb2.td: tighten up bit
15 of the encodings of lots of normal data processing instructions
like shifted ORR. 8.1-M has reused some of the UNPREDICTABLE space in
those encodings, so now those bits have to be hard requirements.

As well as that, there's a load of supporting stuff in the C++,
supporting new formatting details (AsmPrinter), new register classes
and so on.

Event Timeline

simon_tatham created this revision.Apr 15 2019, 6:00 AM

I think this needs splitting up further. There are a lot of novelties in the assembly syntax with this new instruction set, and it's made the patch huge.

SjoerdMeijer added inline comments.Thu, May 2, 3:32 AM
llvm/lib/Target/ARM/ARMRegisterInfo.td
200

Hi Simon, I started looking into this too. I will leave some drive-by comments of a few things I spotted.
Don't think I understand the comments here, i.e. I don't see why we talk about instruction encondings while we are describing registers here.

207

Reading the ARM ARM, I don't think we need this register description. In fact, it's unused in the code at the moment, so if it turns out we need something like this it can be added later.