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[ARM] Add MVE vector bit-operations (register inputs).

Authored by simon_tatham on Jun 19 2019, 9:43 AM.

Description

[ARM] Add MVE vector bit-operations (register inputs).

This includes all the obvious bitwise operations (AND, OR, BIC, ORN,
MVN) in register-to-register forms, and the immediate forms of
AND/OR/BIC/ORN; byte-order reverse instructions; and the VMOVs that
access a single lane of a vector.

Some of those VMOVs (specifically, the ones that access a 32-bit lane)
share an encoding with existing instructions that were disassembled as
accessing half of a d-register (e.g. vmov.32 r0, d1[0]), but in
8.1-M they're now written as accessing a quarter of a q-register (e.g.
vmov.32 r0, q0[2]). The older syntax is still accepted by the
assembler.

Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover

Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62673

llvm-svn: 363838

Details

Committed
simon_tathamJun 19 2019, 9:43 AM
Differential Revision
D62673: [ARM] Add MVE vector bit-operations (register inputs).
Parents
rG54252b8243e3: [AArch64] Improve jump tables testing (NFC)
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