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[ARM] Add remaining miscellaneous MVE instructions.
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Authored by simon_tatham on May 30 2019, 8:23 AM.

Details

Summary

This final batch includes the tail-predicated versions of the
low-overhead loop instructions (LETP); the VPSEL instruction to select
between two vector registers based on the predicate mask without
having to open a VPT block; and VPNOT which complements the predicate
mask in place.

Diff Detail

Repository
rL LLVM

Event Timeline

simon_tatham created this revision.May 30 2019, 8:23 AM

Remastered patch to apply cleanly against current trunk.

miyuki added a subscriber: miyuki.Jun 11 2019, 5:54 AM

Updated instruction spellings in line with intended consistent MVE practice, and also reworked the WLSTP/DLSTP and LETP/LCTP definitions to remove pointless !if from the base classes. (In particular, the instructions that don't have a label field in the encoding now don't have one in their Tablegen defs either.)

ostannard added inline comments.
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
7748 ↗(On Diff #206183)

It would be better to do these as checks on the operands, rather than the whole instruction.

llvm/test/MC/ARM/mve-misc.s
2 ↗(On Diff #206183)

If nothing is expected to vary between the FP and no-FP cases, the check lines can be merged, and the errors checked for both cases.

17 ↗(On Diff #206183)

Are these instructions expected to work with label operands now (in which case that should be tested), or is that coming in a later patch?

simon_tatham marked 3 inline comments as done.Jun 25 2019, 2:27 AM
simon_tatham added inline comments.
llvm/test/MC/ARM/mve-misc.s
17 ↗(On Diff #206183)

Yes, they are; tests added.

Addressed all review comments.

This revision is now accepted and ready to land.Jun 25 2019, 2:55 AM
This revision was automatically updated to reflect the committed changes.