[ARM] Add MVE vector instructions that take a scalar input.

[simon_tatham]

Summary

This adds the MVE_qDest_rSrc superclass and all its instances.
Instructions in this category take a scalar register (or register
pair) as one of the inputs, and combine it with each lane of the other
vector input.

[simon_tatham]

Remastered patch to apply cleanly against current trunk.

[simon_tatham]

Renamed instruction records in line with the intended MVE naming policy. Also generally tidied up while I was going along, by creating multiclasses and merging pairs of base classes where it saved space.

[ostannard]

llvm/lib/Target/ARM/ARMInstrMVE.td

2693

Rm should be 4 bits.

2720

Rm should be 4 bits.

llvm/test/MC/ARM/mve-qdest-rsrc.s

484

Maybe not one for this patch, but you shoyld be able to add a DiagnosticString to the RegisterClass to get a better diagnostic here.

[simon_tatham]

Revised the VIDUP immediate operand handling so as to draw a distinction between the general concept 'power of 2 which is encoded as a left-shift count in the instruction', and the specific case used in VIDUP which takes a fixed range of inputs and has a custom DiagnosticString as you suggested that explains what it's used for.

Also, while I was adding custom DiagnosticStrings, I realised there could usefully be one on the even- and odd-numbered GPR classes. So I've added those too, which meant changing a couple of existing test files.

Finally, fixed those bits<5> Rx fields, and a couple of others I spotted in a more thorough search (including one in the previous patch, ahem).

[ostannard]

LGTM

llvm/lib/Target/ARM/ARMInstrInfo.td

 def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
     int32_t v = N->getZExtValue();
     return v == 8 || v == 16 || v == 24; }],
     rot_imm_XFORM> {
   let PrintMethod = "printRotImmOperand";
   let ParserMatchClass = RotImmAsmOperand;
 }
 
+// Power-of-two operand for MVE VIDUP and friends, which encode
+// {1,2,4,8} as its log to base 2, i.e. as {0,1,2,3} respectively
+def MVE_VIDUP_imm_asmoperand : AsmOperandClass {
+  let Name = "VIDUP_imm";
+  let PredicateMethod = "isPowerTwoInRange<1,8>";
+  let RenderMethod = "addPowerTwoOperands";
+  let DiagnosticString = "vector increment immediate must be 1, 2, 4 or 8";
+}
+def MVE_VIDUP_imm : Operand<i32> {
+  let EncoderMethod = "getPowerTwoOpValue";
+  let DecoderMethod = "DecodePowerTwoOperand<0,3>";
+  let ParserMatchClass = MVE_VIDUP_imm_asmoperand;
+}
+
 // Vector indexing
 class MVEVectorIndexOperand<int NumLanes> : AsmOperandClass {
   let Name = "MVEVectorIndex"#NumLanes;
   let RenderMethod = "addMVEVectorIndexOperands";
   let PredicateMethod = "isVectorIndexInRange<"#NumLanes#">";
 }
 
 class MVEVectorIndex<int NumLanes> : Operand<i32> {

llvm/lib/Target/ARM/ARMInstrMVE.td

def MVE_VMOV_to_lane : MVE_VMOV_lane_direction {
   let cstr = "$Qd = $Qd_src";
 }
 
 class MVE_VMOV_lane<string suffix, bit U, dag indexop,
                     MVE_VMOV_lane_direction dir>
   : MVE_VMOV_lane_base<dir.oops, !con(dir.iops, indexop), NoItinerary,
                        "vmov", suffix, dir.ops, dir.cstr, []> {
   bits<4> Qd;
-  bits<5> Rt;
+  bits<4> Rt;
 
   let Inst{31-24} = 0b11101110;
   let Inst{23} = U;
   let Inst{20} = dir.bit_20;
   let Inst{19-17} = Qd{2-0};
   let Inst{15-12} = Rt{3-0};
   let Inst{11-8} = 0b1011;
   let Inst{7} = Qd{3};
multiclass MVE_VQDMULL_halves<string suffix, bit size> {
   def th : MVE_VQDMULL<"vqdmullt", suffix, size, 0b1>;
 }
 
 defm MVE_VQDMULLs16 : MVE_VQDMULL_halves<"s16", 0b0>;
 defm MVE_VQDMULLs32 : MVE_VQDMULL_halves<"s32", 0b1>;
 
 // end of mve_qDest_qSrc
 
+// start of mve_qDest_rSrc
+
+class MVE_qr_base<dag oops, dag iops, InstrItinClass itin, string iname,
+                  string suffix, string ops, vpred_ops vpred, string cstr,
+                  list<dag> pattern=[]>
+   : MVE_p<oops, iops, NoItinerary, iname, suffix, ops, vpred, cstr, pattern> {
+  bits<4> Qd;
+  bits<4> Qn;
+  bits<4> Rm;
+
+  let Inst{25-23} = 0b100;
+  let Inst{22} = Qd{3};
+  let Inst{19-17} = Qn{2-0};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{11-9} = 0b111;
+  let Inst{7} = Qn{3};
+  let Inst{6} = 0b1;
+  let Inst{4} = 0b0;
+  let Inst{3-0} = Rm{3-0};
+}
+
+class MVE_qDest_rSrc<string iname, string suffix, list<dag> pattern=[]>
+  : MVE_qr_base<(outs MQPR:$Qd), (ins MQPR:$Qn, rGPR:$Rm),
+          NoItinerary, iname, suffix, "$Qd, $Qn, $Rm", vpred_r, "",
+           pattern>;
+
+class MVE_qDestSrc_rSrc<string iname, string suffix, list<dag> pattern=[]>
+  : MVE_qr_base<(outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qn, rGPR:$Rm),
+          NoItinerary, iname, suffix, "$Qd, $Qn, $Rm", vpred_n, "$Qd = $Qd_src",
+           pattern>;
+
+class MVE_qDest_single_rSrc<string iname, string suffix, list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qd_src, rGPR:$Rm), NoItinerary, iname,
+          suffix, "$Qd, $Rm", vpred_n, "$Qd = $Qd_src", pattern> {
+  bits<4> Qd;
+  bits<4> Rm;
+
+  let Inst{22} = Qd{3};
+  let Inst{15-13} = Qd{2-0};
+  let Inst{3-0} = Rm{3-0};
+}
+
+class MVE_VADDSUB_qr<string iname, string suffix, bits<2> size,
+                     bit bit_5, bit bit_12, bit bit_16,
+                     bit bit_28, list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = bit_28;
+  let Inst{21-20} = size;
+  let Inst{16} = bit_16;
+  let Inst{12} = bit_12;
+  let Inst{8} = 0b1;
+  let Inst{5} = bit_5;
+}
+
+multiclass MVE_VADDSUB_qr_sizes<string iname, string suffix,
+                                bit bit_5, bit bit_12, bit bit_16,
+                                bit bit_28, list<dag> pattern=[]> {
+  def "8"  : MVE_VADDSUB_qr<iname, suffix#"8",  0b00,
+                            bit_5, bit_12, bit_16, bit_28>;
+  def "16" : MVE_VADDSUB_qr<iname, suffix#"16", 0b01,
+                            bit_5, bit_12, bit_16, bit_28>;
+  def "32" : MVE_VADDSUB_qr<iname, suffix#"32", 0b10,
+                            bit_5, bit_12, bit_16, bit_28>;
+}
+
+defm MVE_VADD_qr_i  : MVE_VADDSUB_qr_sizes<"vadd",  "i", 0b0, 0b0, 0b1, 0b0>;
+defm MVE_VQADD_qr_s : MVE_VADDSUB_qr_sizes<"vqadd", "s", 0b1, 0b0, 0b0, 0b0>;
+defm MVE_VQADD_qr_u : MVE_VADDSUB_qr_sizes<"vqadd", "u", 0b1, 0b0, 0b0, 0b1>;
+
+defm MVE_VSUB_qr_i  : MVE_VADDSUB_qr_sizes<"vsub",  "i", 0b0, 0b1, 0b1, 0b0>;
+defm MVE_VQSUB_qr_s : MVE_VADDSUB_qr_sizes<"vqsub", "s", 0b1, 0b1, 0b0, 0b0>;
+defm MVE_VQSUB_qr_u : MVE_VADDSUB_qr_sizes<"vqsub", "u", 0b1, 0b1, 0b0, 0b1>;
+
+class MVE_VQDMULL_qr<string iname, string suffix, bit size,
+                     bit T, list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = size;
+  let Inst{21-20} = 0b11;
+  let Inst{16} = 0b0;
+  let Inst{12} = T;
+  let Inst{8} = 0b1;
+  let Inst{5} = 0b1;
+}
+
+multiclass MVE_VQDMULL_qr_halves<string suffix, bit size> {
+  def bh : MVE_VQDMULL_qr<"vqdmullb", suffix, size, 0b0>;
+  def th : MVE_VQDMULL_qr<"vqdmullt", suffix, size, 0b1>;
+}
+
+defm MVE_VQDMULL_qr_s16 : MVE_VQDMULL_qr_halves<"s16", 0b0>;
+defm MVE_VQDMULL_qr_s32 : MVE_VQDMULL_qr_halves<"s32", 0b1>;
+
+class MVE_VxADDSUB_qr<string iname, string suffix,
+                      bit bit_28, bits<2> bits_21_20, bit subtract,
+                      list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = bit_28;
+  let Inst{21-20} = bits_21_20;
+  let Inst{16} = 0b0;
+  let Inst{12} = subtract;
+  let Inst{8} = 0b1;
+  let Inst{5} = 0b0;
+}
+
+def MVE_VHADD_qr_s8   : MVE_VxADDSUB_qr<"vhadd", "s8",  0b0, 0b00, 0b0>;
+def MVE_VHADD_qr_s16  : MVE_VxADDSUB_qr<"vhadd", "s16", 0b0, 0b01, 0b0>;
+def MVE_VHADD_qr_s32  : MVE_VxADDSUB_qr<"vhadd", "s32", 0b0, 0b10, 0b0>;
+def MVE_VHADD_qr_u8   : MVE_VxADDSUB_qr<"vhadd", "u8",  0b1, 0b00, 0b0>;
+def MVE_VHADD_qr_u16  : MVE_VxADDSUB_qr<"vhadd", "u16", 0b1, 0b01, 0b0>;
+def MVE_VHADD_qr_u32  : MVE_VxADDSUB_qr<"vhadd", "u32", 0b1, 0b10, 0b0>;
+
+def MVE_VHSUB_qr_s8   : MVE_VxADDSUB_qr<"vhsub", "s8",  0b0, 0b00, 0b1>;
+def MVE_VHSUB_qr_s16  : MVE_VxADDSUB_qr<"vhsub", "s16", 0b0, 0b01, 0b1>;
+def MVE_VHSUB_qr_s32  : MVE_VxADDSUB_qr<"vhsub", "s32", 0b0, 0b10, 0b1>;
+def MVE_VHSUB_qr_u8   : MVE_VxADDSUB_qr<"vhsub", "u8",  0b1, 0b00, 0b1>;
+def MVE_VHSUB_qr_u16  : MVE_VxADDSUB_qr<"vhsub", "u16", 0b1, 0b01, 0b1>;
+def MVE_VHSUB_qr_u32  : MVE_VxADDSUB_qr<"vhsub", "u32", 0b1, 0b10, 0b1>;
+
+let Predicates = [HasMVEFloat] in {
+  def MVE_VADD_qr_f32 : MVE_VxADDSUB_qr<"vadd",  "f32", 0b0, 0b11, 0b0>;
+  def MVE_VADD_qr_f16 : MVE_VxADDSUB_qr<"vadd",  "f16", 0b1, 0b11, 0b0>;
+
+  def MVE_VSUB_qr_f32 : MVE_VxADDSUB_qr<"vsub",  "f32", 0b0, 0b11, 0b1>;
+  def MVE_VSUB_qr_f16 : MVE_VxADDSUB_qr<"vsub",  "f16", 0b1, 0b11, 0b1>;
+}
+
+class MVE_VxSHL_qr<string iname, string suffix, bit U, bits<2> size,
+                   bit bit_7, bit bit_17, list<dag> pattern=[]>
+  : MVE_qDest_single_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = U;
+  let Inst{25-23} = 0b100;
+  let Inst{21-20} = 0b11;
+  let Inst{19-18} = size;
+  let Inst{17} = bit_17;
+  let Inst{16} = 0b1;
+  let Inst{12-8} = 0b11110;
+  let Inst{7} = bit_7;
+  let Inst{6-4} = 0b110;
+}
+
+multiclass MVE_VxSHL_qr_types<string iname, bit bit_7, bit bit_17> {
+  def s8  : MVE_VxSHL_qr<iname, "s8", 0b0, 0b00, bit_7, bit_17>;
+  def s16 : MVE_VxSHL_qr<iname, "s16", 0b0, 0b01, bit_7, bit_17>;
+  def s32 : MVE_VxSHL_qr<iname, "s32", 0b0, 0b10, bit_7, bit_17>;
+  def u8  : MVE_VxSHL_qr<iname, "u8", 0b1, 0b00, bit_7, bit_17>;
+  def u16 : MVE_VxSHL_qr<iname, "u16", 0b1, 0b01, bit_7, bit_17>;
+  def u32 : MVE_VxSHL_qr<iname, "u32", 0b1, 0b10, bit_7, bit_17>;
+}
+
+defm MVE_VSHL_qr   : MVE_VxSHL_qr_types<"vshl",   0b0, 0b0>;
+defm MVE_VRSHL_qr  : MVE_VxSHL_qr_types<"vrshl",  0b0, 0b1>;
+defm MVE_VQSHL_qr  : MVE_VxSHL_qr_types<"vqshl",  0b1, 0b0>;
+defm MVE_VQRSHL_qr : MVE_VxSHL_qr_types<"vqrshl", 0b1, 0b1>;
+
+class MVE_VBRSR<string iname, string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = 0b1;
+  let Inst{21-20} = size;
+  let Inst{16} = 0b1;
+  let Inst{12} = 0b1;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b1;
+}
+
+def MVE_VBRSR8  : MVE_VBRSR<"vbrsr", "8", 0b00>;
+def MVE_VBRSR16 : MVE_VBRSR<"vbrsr", "16", 0b01>;
+def MVE_VBRSR32 : MVE_VBRSR<"vbrsr", "32", 0b10>;
+
+class MVE_VMUL_qr_int<string iname, string suffix,
+                      bits<2> size, list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = 0b0;
+  let Inst{21-20} = size;
+  let Inst{16} = 0b1;
+  let Inst{12} = 0b1;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b1;
+}
+
+def MVE_VMUL_qr_i8  : MVE_VMUL_qr_int<"vmul", "i8",  0b00>;
+def MVE_VMUL_qr_i16 : MVE_VMUL_qr_int<"vmul", "i16", 0b01>;
+def MVE_VMUL_qr_i32 : MVE_VMUL_qr_int<"vmul", "i32", 0b10>;
+
+class MVE_VxxMUL_qr<string iname, string suffix,
+                    bit bit_28, bits<2> bits_21_20, list<dag> pattern=[]>
+  : MVE_qDest_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = bit_28;
+  let Inst{21-20} = bits_21_20;
+  let Inst{16} = 0b1;
+  let Inst{12} = 0b0;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b1;
+}
+
+def MVE_VQDMULH_qr_s8   : MVE_VxxMUL_qr<"vqdmulh",  "s8",  0b0, 0b00>;
+def MVE_VQDMULH_qr_s16  : MVE_VxxMUL_qr<"vqdmulh",  "s16", 0b0, 0b01>;
+def MVE_VQDMULH_qr_s32  : MVE_VxxMUL_qr<"vqdmulh",  "s32", 0b0, 0b10>;
+
+def MVE_VQRDMULH_qr_s8  : MVE_VxxMUL_qr<"vqrdmulh", "s8",  0b1, 0b00>;
+def MVE_VQRDMULH_qr_s16 : MVE_VxxMUL_qr<"vqrdmulh", "s16", 0b1, 0b01>;
+def MVE_VQRDMULH_qr_s32 : MVE_VxxMUL_qr<"vqrdmulh", "s32", 0b1, 0b10>;
+
+let Predicates = [HasMVEFloat] in {
+  def MVE_VMUL_qr_f16   : MVE_VxxMUL_qr<"vmul", "f16", 0b1, 0b11>;
+  def MVE_VMUL_qr_f32   : MVE_VxxMUL_qr<"vmul", "f32", 0b0, 0b11>;
+}
+
+class MVE_VFMAMLA_qr<string iname, string suffix,
+                   bit bit_28, bits<2> bits_21_20, bit S,
+                   list<dag> pattern=[]>
+  : MVE_qDestSrc_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = bit_28;
+  let Inst{21-20} = bits_21_20;
+  let Inst{16} = 0b1;
+  let Inst{12} = S;
+  let Inst{8} = 0b0;
+  let Inst{5} = 0b0;
+}
+
+def MVE_VMLA_qr_s8     : MVE_VFMAMLA_qr<"vmla",  "s8",  0b0, 0b00, 0b0>;
+def MVE_VMLA_qr_s16    : MVE_VFMAMLA_qr<"vmla",  "s16", 0b0, 0b01, 0b0>;
+def MVE_VMLA_qr_s32    : MVE_VFMAMLA_qr<"vmla",  "s32", 0b0, 0b10, 0b0>;
+def MVE_VMLA_qr_u8     : MVE_VFMAMLA_qr<"vmla",  "u8",  0b1, 0b00, 0b0>;
+def MVE_VMLA_qr_u16    : MVE_VFMAMLA_qr<"vmla",  "u16", 0b1, 0b01, 0b0>;
+def MVE_VMLA_qr_u32    : MVE_VFMAMLA_qr<"vmla",  "u32", 0b1, 0b10, 0b0>;
+
+def MVE_VMLAS_qr_s8    : MVE_VFMAMLA_qr<"vmlas", "s8",  0b0, 0b00, 0b1>;
+def MVE_VMLAS_qr_s16   : MVE_VFMAMLA_qr<"vmlas", "s16", 0b0, 0b01, 0b1>;
+def MVE_VMLAS_qr_s32   : MVE_VFMAMLA_qr<"vmlas", "s32", 0b0, 0b10, 0b1>;
+def MVE_VMLAS_qr_u8    : MVE_VFMAMLA_qr<"vmlas", "u8",  0b1, 0b00, 0b1>;
+def MVE_VMLAS_qr_u16   : MVE_VFMAMLA_qr<"vmlas", "u16", 0b1, 0b01, 0b1>;
+def MVE_VMLAS_qr_u32   : MVE_VFMAMLA_qr<"vmlas", "u32", 0b1, 0b10, 0b1>;
+
+let Predicates = [HasMVEFloat] in {
+  def MVE_VFMA_qr_f16  : MVE_VFMAMLA_qr<"vfma",  "f16", 0b1, 0b11, 0b0>;
+  def MVE_VFMA_qr_f32  : MVE_VFMAMLA_qr<"vfma",  "f32", 0b0, 0b11, 0b0>;
+  def MVE_VFMA_qr_Sf16 : MVE_VFMAMLA_qr<"vfmas", "f16", 0b1, 0b11, 0b1>;
+  def MVE_VFMA_qr_Sf32 : MVE_VFMAMLA_qr<"vfmas", "f32", 0b0, 0b11, 0b1>;
+}
+
+class MVE_VQDMLAH_qr<string iname, string suffix, bit U, bits<2> size,
+                     bit bit_5, bit bit_12, list<dag> pattern=[]>
+  : MVE_qDestSrc_rSrc<iname, suffix, pattern> {
+
+  let Inst{28} = U;
+  let Inst{21-20} = size;
+  let Inst{16} = 0b0;
+  let Inst{12} = bit_12;
+  let Inst{8} = 0b0;
+  let Inst{5} = bit_5;
+}
+
+multiclass MVE_VQDMLAH_qr_types<string iname, bit bit_5, bit bit_12> {
+  def s8  : MVE_VQDMLAH_qr<iname, "s8",  0b0, 0b00, bit_5, bit_12>;
+  def s16 : MVE_VQDMLAH_qr<iname, "s16", 0b0, 0b01, bit_5, bit_12>;
+  def s32 : MVE_VQDMLAH_qr<iname, "s32", 0b0, 0b10, bit_5, bit_12>;
+  def u8  : MVE_VQDMLAH_qr<iname, "u8",  0b1, 0b00, bit_5, bit_12>;
+  def u16 : MVE_VQDMLAH_qr<iname, "u16", 0b1, 0b01, bit_5, bit_12>;
+  def u32 : MVE_VQDMLAH_qr<iname, "u32", 0b1, 0b10, bit_5, bit_12>;
+}
+
+defm MVE_VQDMLAH_qr   : MVE_VQDMLAH_qr_types<"vqdmlah",   0b1, 0b0>;
+defm MVE_VQRDMLAH_qr  : MVE_VQDMLAH_qr_types<"vqrdmlah",  0b0, 0b0>;
+defm MVE_VQDMLASH_qr  : MVE_VQDMLAH_qr_types<"vqdmlash",  0b1, 0b1>;
+defm MVE_VQRDMLASH_qr : MVE_VQDMLAH_qr_types<"vqrdmlash", 0b0, 0b1>;
+
+class MVE_VxDUP<string iname, string suffix, bits<2> size, bit bit_12,
+              list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd, tGPREven:$Rn),
+          (ins tGPREven:$Rn_src, MVE_VIDUP_imm:$imm), NoItinerary,
+          iname, suffix, "$Qd, $Rn, $imm", vpred_r, "$Rn = $Rn_src",
+          pattern> {
+  bits<4> Qd;
+  bits<4> Rn;
+  bits<2> imm;
+
+  let Inst{28} = 0b0;
+  let Inst{25-23} = 0b100;
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = size;
+  let Inst{19-17} = Rn{3-1};
+  let Inst{16} = 0b1;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12} = bit_12;
+  let Inst{11-8} = 0b1111;
+  let Inst{7} = imm{1};
+  let Inst{6-1} = 0b110111;
+  let Inst{0} = imm{0};
+}
+
+def MVE_VIDUPu8  : MVE_VxDUP<"vidup", "u8",  0b00, 0b0>;
+def MVE_VIDUPu16 : MVE_VxDUP<"vidup", "u16", 0b01, 0b0>;
+def MVE_VIDUPu32 : MVE_VxDUP<"vidup", "u32", 0b10, 0b0>;
+
+def MVE_VDDUPu8  : MVE_VxDUP<"vddup", "u8",  0b00, 0b1>;
+def MVE_VDDUPu16 : MVE_VxDUP<"vddup", "u16", 0b01, 0b1>;
+def MVE_VDDUPu32 : MVE_VxDUP<"vddup", "u32", 0b10, 0b1>;
+
+class MVE_VxWDUP<string iname, string suffix, bits<2> size, bit bit_12,
+                 list<dag> pattern=[]>
+  : MVE_p<(outs MQPR:$Qd, tGPREven:$Rn),
+          (ins tGPREven:$Rn_src, tGPROdd:$Rm, MVE_VIDUP_imm:$imm), NoItinerary,
+          iname, suffix, "$Qd, $Rn, $Rm, $imm", vpred_r, "$Rn = $Rn_src",
+          pattern> {
+  bits<4> Qd;
+  bits<4> Rm;
+  bits<4> Rn;
+  bits<2> imm;
+
+  let Inst{28} = 0b0;
+  let Inst{25-23} = 0b100;
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = size;
+  let Inst{19-17} = Rn{3-1};
+  let Inst{16} = 0b1;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12} = bit_12;
+  let Inst{11-8} = 0b1111;
+  let Inst{7} = imm{1};
+  let Inst{6-4} = 0b110;
+  let Inst{3-1} = Rm{3-1};
+  let Inst{0} = imm{0};
+}
+
+def MVE_VIWDUPu8  : MVE_VxWDUP<"viwdup", "u8",  0b00, 0b0>;
+def MVE_VIWDUPu16 : MVE_VxWDUP<"viwdup", "u16", 0b01, 0b0>;
+def MVE_VIWDUPu32 : MVE_VxWDUP<"viwdup", "u32", 0b10, 0b0>;
+
+def MVE_VDWDUPu8  : MVE_VxWDUP<"vdwdup", "u8",  0b00, 0b1>;
+def MVE_VDWDUPu16 : MVE_VxWDUP<"vdwdup", "u16", 0b01, 0b1>;
+def MVE_VDWDUPu32 : MVE_VxWDUP<"vdwdup", "u32", 0b10, 0b1>;
+
+class MVE_VCTP<string suffix, bits<2> size, list<dag> pattern=[]>
+  : MVE_p<(outs VCCR:$P0), (ins rGPR:$Rn), NoItinerary, "vctp", suffix,
+          "$Rn", vpred_n, "", pattern> {
+  bits<4> Rn;
+
+  let Inst{28-27} = 0b10;
+  let Inst{26-22} = 0b00000;
+  let Inst{21-20} = size;
+  let Inst{19-16} = Rn{3-0};
+  let Inst{15-11} = 0b11101;
+  let Inst{10-0}  = 0b00000000001;
+  let Unpredictable{10-0} = 0b11111111111;
+
+  let Constraints = "";
+  let DecoderMethod = "DecodeMveVCTP";
+}
+
+def MVE_VCTP8  : MVE_VCTP<"8",  0b00>;
+def MVE_VCTP16 : MVE_VCTP<"16", 0b01>;
+def MVE_VCTP32 : MVE_VCTP<"32", 0b10>;
+def MVE_VCTP64 : MVE_VCTP<"64", 0b11>;
+
+// end of mve_qDest_rSrc
+
 class MVE_VPT<string suffix, bits<2> size, dag iops, string asm, list<dag> pattern=[]>
   : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
   bits<3> fc;
   bits<4> Mk;
   bits<3> Qn;
 
   let Inst{31-23} = 0b111111100;
   let Inst{22} = Mk{3};

llvm/lib/Target/ARM/ARMRegisterInfo.td

def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> {
   }];
 }
 
 def tGPROdd : RegisterClass<"ARM", [i32], 32, (add R1, R3, R5, R7, R9, R11)> {
   let AltOrders = [(and tGPROdd, tGPR)];
   let AltOrderSelect = [{
       return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
   }];
+  let DiagnosticString =
+    "operand must be an odd-numbered register in range [r1,r11]";
 }
 
 def tGPREven : RegisterClass<"ARM", [i32], 32, (add R0, R2, R4, R6, R8, R10, R12, LR)> {
   let AltOrders = [(and tGPREven, tGPR)];
   let AltOrderSelect = [{
       return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
   }];
+  let DiagnosticString = "operand must be an even-numbered register";
 }
 
 // Condition code registers.
 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
   let CopyCost = -1;  // Don't allow copying of status registers.
   let isAllocatable = 0;
 }
 

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

return Kind == k_ShiftedRegister &&
                RegShiftedReg.ShiftReg);
   }
   bool isRegShiftedImm() const {
     return Kind == k_ShiftedImmediate &&
            ARMMCRegisterClasses[ARM::GPRRegClassID].contains(
                RegShiftedImm.SrcReg);
   }
   bool isRotImm() const { return Kind == k_RotateImmediate; }
+
+  template<unsigned Min, unsigned Max>
+  bool isPowerTwoInRange() const {
+    if (!isImm()) return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+    return Value > 0 && countPopulation((uint64_t)Value) == 1 &&
+           Value >= Min && Value <= Max;
+  }
   bool isModImm() const { return Kind == k_ModifiedImmediate; }
 
   bool isModImmNot() const {
     if (!isImm()) return false;
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     if (!CE) return false;
     int64_t Value = CE->getValue();
     return ARM_AM::getSOImmVal(~Value) != -1;
StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
   // predicated but do have a carry-set and so weren't caught above.
   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
       Mnemonic != "sbcs" && Mnemonic != "rscs" &&
       !(hasMVE() &&
         (Mnemonic == "vmine" ||
          Mnemonic == "vshle" || Mnemonic == "vshlt" || Mnemonic == "vshllt" ||
+         Mnemonic == "vrshle" || Mnemonic == "vrshlt" ||
          Mnemonic == "vmvne" || Mnemonic == "vorne" ||
          Mnemonic == "vnege" || Mnemonic == "vnegt" ||
          Mnemonic == "vmule" || Mnemonic == "vmult" ||
          Mnemonic == "vrintne" ||
          Mnemonic == "vcmult" || Mnemonic == "vcmule" ||
          Mnemonic.startswith("vq")))) {
     unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
     if (CC != ~0U) {
if (Mnemonic.endswith("s") &&
         Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
         Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
         Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
         Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
         Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
         Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
         Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
         Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
-        Mnemonic == "bxns" || Mnemonic == "blxns" ||
+        Mnemonic == "bxns" || Mnemonic == "blxns" || Mnemonic == "vfmas" ||
+        Mnemonic == "vmlas" ||
         (Mnemonic == "movs" && isThumb()))) {
     Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
     CarrySetting = true;
   }
 
   // The "cps" instruction can have a interrupt mode operand which is glued into
   // the mnemonic. Check if this is the case, split it and parse the imod op
   if (Mnemonic.startswith("cps")) {
bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
   return false;
 }
 
 bool ARMAsmParser::shouldOmitVectorPredicateOperand(StringRef Mnemonic,
                                                     OperandVector &Operands) {
   if (!hasMVE() || Operands.size() < 3)
     return true;
 
+  if (Mnemonic.startswith("vctp"))
+    return false;
+
   if (Mnemonic.startswith("vmov") &&
       !(Mnemonic.startswith("vmovl") || Mnemonic.startswith("vmovn") ||
         Mnemonic.startswith("vmovx"))) {
     for (auto &Operand : Operands) {
       if (static_cast<ARMOperand &>(*Operand).isVectorIndex() ||
           ((*Operand).isReg() &&
            (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(
              (*Operand).getReg()) ||

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

 static DecodeStatus DecodeRestrictedFPPredicateOperand(MCInst &Inst,
                                                        unsigned Val,
                                                        uint64_t Address,
                                                        const void *Decoder);
 template<bool Writeback>
 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
                                           uint64_t Address,
                                           const void *Decoder);
+template<unsigned MinLog, unsigned MaxLog>
+static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
+                                          uint64_t Address,
+                                          const void *Decoder);
 template <int shift>
 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val,
                                              uint64_t Address,
                                              const void *Decoder);
 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
                                       uint64_t Address, const void *Decoder);
 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
                                     uint64_t Address, const void *Decoder);
 template<bool scalar, OperandDecoder predicate_decoder>
 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn,
                                   uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn,
+                                  uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn,
                                                   uint64_t Address,
                                                   const void *Decoder);
 #include "ARMGenDisassemblerTables.inc"
 
 static MCDisassembler *createARMDisassembler(const Target &T,
                                              const MCSubtargetInfo &STI,
                                              MCContext &Ctx) {
if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder)))
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createImm(ARMCC::AL));
   Inst.addOperand(MCOperand::createReg(0));
 
   return S;
 }
 
+template<unsigned MinLog, unsigned MaxLog>
+static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
+                                          uint64_t Address,
+                                          const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+
+  if (Val < MinLog || Val > MaxLog)
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::createImm(1 << Val));
+  return S;
+}
+
 template <int shift>
 static DecodeStatus DecodeExpandedImmOperand(MCInst &Inst, unsigned Val,
                                              uint64_t Address,
                                              const void *Decoder) {
     Val <<= shift;
 
     Inst.addOperand(MCOperand::createImm(Val));
     return MCDisassembler::Success;
if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder)))
     return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createImm(ARMVCC::None));
   Inst.addOperand(MCOperand::createReg(0));
   Inst.addOperand(MCOperand::createImm(0));
 
   return S;
 }
+
+static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
+                                  const void *Decoder) {
+  DecodeStatus S = MCDisassembler::Success;
+  Inst.addOperand(MCOperand::createReg(ARM::VPR));
+  unsigned Rn = fieldFromInstruction(Insn, 16, 4);
+  if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
+    return MCDisassembler::Fail;
+  return S;
+}

llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

public:
   unsigned NEONThumb2V8PostEncoder(const MCInst &MI,
                                    unsigned EncodedValue,
                                    const MCSubtargetInfo &STI) const;
 
   unsigned VFPThumb2PostEncoder(const MCInst &MI,
                                 unsigned EncodedValue,
                                 const MCSubtargetInfo &STI) const;
 
+  uint32_t getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
+                              SmallVectorImpl<MCFixup> &Fixups,
+                              const MCSubtargetInfo &STI) const;
+
   void EmitByte(unsigned char C, raw_ostream &OS) const {
     OS << (char)C;
   }
 
   void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
     // Output the constant in little endian byte order.
     for (unsigned i = 0; i != Size; ++i) {
       unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
case ARMCC::LT:
     return 5;
   case ARMCC::GT:
     return 6;
   case ARMCC::LE:
     return 7;
   }
 }
 
+uint32_t ARMMCCodeEmitter::
+getPowerTwoOpValue(const MCInst &MI, unsigned OpIdx,
+                   SmallVectorImpl<MCFixup> &Fixups,
+                   const MCSubtargetInfo &STI) const {
+  const MCOperand &MO = MI.getOperand(OpIdx);
+  assert(MO.isImm() && "Unexpected operand type!");
+  return countTrailingZeros((uint64_t)MO.getImm());
+}
+
 #include "ARMGenMCCodeEmitter.inc"
 
 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
                                               const MCRegisterInfo &MRI,
                                               MCContext &Ctx) {
   return new ARMMCCodeEmitter(MCII, Ctx, true);
 }
 
 MCCodeEmitter *llvm::createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
                                               const MCRegisterInfo &MRI,
                                               MCContext &Ctx) {
   return new ARMMCCodeEmitter(MCII, Ctx, false);
 }

llvm/test/MC/ARM/mve-qdest-rsrc.s

+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding  < %s \
+# RUN:   | FileCheck --check-prefix=CHECK-NOFP %s
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding  < %s 2>%t \
+# RUN:   | FileCheck --check-prefix=CHECK %s
+# RUN:     FileCheck --check-prefix=ERROR < %t %s
+
+# CHECK: vsub.i8 q0, q3, r3  @ encoding: [0x07,0xee,0x43,0x1f]
+# CHECK-NOFP: vsub.i8 q0, q3, r3  @ encoding: [0x07,0xee,0x43,0x1f]
+vsub.i8 q0, q3, r3
+
+# CHECK: vsub.i16 q0, q7, lr  @ encoding: [0x1f,0xee,0x4e,0x1f]
+# CHECK-NOFP: vsub.i16 q0, q7, lr  @ encoding: [0x1f,0xee,0x4e,0x1f]
+vsub.i16 q0, q7, lr
+
+# CHECK: vsub.i32 q1, q5, r10  @ encoding: [0x2b,0xee,0x4a,0x3f]
+# CHECK-NOFP: vsub.i32 q1, q5, r10  @ encoding: [0x2b,0xee,0x4a,0x3f]
+vsub.i32 q1, q5, r10
+
+# CHECK: vadd.i8 q1, q4, r7  @ encoding: [0x09,0xee,0x47,0x2f]
+# CHECK-NOFP: vadd.i8 q1, q4, r7  @ encoding: [0x09,0xee,0x47,0x2f]
+vadd.i8 q1, q4, r7
+
+# CHECK: vadd.i16 q0, q6, r11  @ encoding: [0x1d,0xee,0x4b,0x0f]
+# CHECK-NOFP: vadd.i16 q0, q6, r11  @ encoding: [0x1d,0xee,0x4b,0x0f]
+vadd.i16 q0, q6, r11
+
+# CHECK: vadd.i32 q0, q1, r6  @ encoding: [0x23,0xee,0x46,0x0f]
+# CHECK-NOFP: vadd.i32 q0, q1, r6  @ encoding: [0x23,0xee,0x46,0x0f]
+vadd.i32 q0, q1, r6
+
+# CHECK: vqsub.s8 q2, q2, r8  @ encoding: [0x04,0xee,0x68,0x5f]
+# CHECK-NOFP: vqsub.s8 q2, q2, r8  @ encoding: [0x04,0xee,0x68,0x5f]
+vqsub.s8 q2, q2, r8
+
+# CHECK: vqsub.s16 q1, q4, r0  @ encoding: [0x18,0xee,0x60,0x3f]
+# CHECK-NOFP: vqsub.s16 q1, q4, r0  @ encoding: [0x18,0xee,0x60,0x3f]
+vqsub.s16 q1, q4, r0
+
+# CHECK: vqsub.s32 q0, q2, r0  @ encoding: [0x24,0xee,0x60,0x1f]
+# CHECK-NOFP: vqsub.s32 q0, q2, r0  @ encoding: [0x24,0xee,0x60,0x1f]
+vqsub.s32 q0, q2, r0
+
+# CHECK: vqsub.u8 q0, q1, r2  @ encoding: [0x02,0xfe,0x62,0x1f]
+# CHECK-NOFP: vqsub.u8 q0, q1, r2  @ encoding: [0x02,0xfe,0x62,0x1f]
+vqsub.u8 q0, q1, r2
+
+# CHECK: vqsub.u16 q0, q2, r6  @ encoding: [0x14,0xfe,0x66,0x1f]
+# CHECK-NOFP: vqsub.u16 q0, q2, r6  @ encoding: [0x14,0xfe,0x66,0x1f]
+vqsub.u16 q0, q2, r6
+
+# CHECK: vqsub.u32 q0, q2, r2  @ encoding: [0x24,0xfe,0x62,0x1f]
+# CHECK-NOFP: vqsub.u32 q0, q2, r2  @ encoding: [0x24,0xfe,0x62,0x1f]
+vqsub.u32 q0, q2, r2
+
+# CHECK: vqadd.s8 q0, q6, r1  @ encoding: [0x0c,0xee,0x61,0x0f]
+# CHECK-NOFP: vqadd.s8 q0, q6, r1  @ encoding: [0x0c,0xee,0x61,0x0f]
+vqadd.s8 q0, q6, r1
+
+# CHECK: vqadd.s16 q3, q4, r2  @ encoding: [0x18,0xee,0x62,0x6f]
+# CHECK-NOFP: vqadd.s16 q3, q4, r2  @ encoding: [0x18,0xee,0x62,0x6f]
+vqadd.s16 q3, q4, r2
+
+# CHECK: vqadd.s32 q0, q5, r11  @ encoding: [0x2a,0xee,0x6b,0x0f]
+# CHECK-NOFP: vqadd.s32 q0, q5, r11  @ encoding: [0x2a,0xee,0x6b,0x0f]
+vqadd.s32 q0, q5, r11
+
+# CHECK: vqadd.u8 q0, q1, r8  @ encoding: [0x02,0xfe,0x68,0x0f]
+# CHECK-NOFP: vqadd.u8 q0, q1, r8  @ encoding: [0x02,0xfe,0x68,0x0f]
+vqadd.u8 q0, q1, r8
+
+# CHECK: vqadd.u16 q0, q5, r9  @ encoding: [0x1a,0xfe,0x69,0x0f]
+# CHECK-NOFP: vqadd.u16 q0, q5, r9  @ encoding: [0x1a,0xfe,0x69,0x0f]
+vqadd.u16 q0, q5, r9
+
+# CHECK: vqadd.u32 q0, q0, r7  @ encoding: [0x20,0xfe,0x67,0x0f]
+# CHECK-NOFP: vqadd.u32 q0, q0, r7  @ encoding: [0x20,0xfe,0x67,0x0f]
+vqadd.u32 q0, q0, r7
+
+# CHECK: vqdmullb.s16 q0, q1, r6  @ encoding: [0x32,0xee,0x66,0x0f]
+# CHECK-NOFP: vqdmullb.s16 q0, q1, r6  @ encoding: [0x32,0xee,0x66,0x0f]
+vqdmullb.s16 q0, q1, r6
+
+# CHECK: vqdmullb.s32 q0, q3, q7  @ encoding: [0x36,0xfe,0x0f,0x0f]
+# CHECK-NOFP: vqdmullb.s32 q0, q3, q7  @ encoding: [0x36,0xfe,0x0f,0x0f]
+vqdmullb.s32 q0, q3, q7
+
+# CHECK: vqdmullt.s16 q0, q1, r0  @ encoding: [0x32,0xee,0x60,0x1f]
+# CHECK-NOFP: vqdmullt.s16 q0, q1, r0  @ encoding: [0x32,0xee,0x60,0x1f]
+vqdmullt.s16 q0, q1, r0
+
+# CHECK: vqdmullt.s32 q0, q4, r5  @ encoding: [0x38,0xfe,0x65,0x1f]
+# CHECK-NOFP: vqdmullt.s32 q0, q4, r5  @ encoding: [0x38,0xfe,0x65,0x1f]
+vqdmullt.s32 q0, q4, r5
+
+# CHECK: vsub.f16 q0, q3, r7  @ encoding: [0x36,0xfe,0x47,0x1f]
+# CHECK-NOFP-NOT: vsub.f16 q0, q3, r7  @ encoding: [0x36,0xfe,0x47,0x1f]
+vsub.f16 q0, q3, r7
+
+# CHECK: vsub.f32 q1, q1, r10  @ encoding: [0x32,0xee,0x4a,0x3f]
+# CHECK-NOFP-NOT: vsub.f32 q1, q1, r10  @ encoding: [0x32,0xee,0x4a,0x3f]
+vsub.f32 q1, q1, r10
+
+# CHECK: vadd.f16 q0, q1, lr  @ encoding: [0x32,0xfe,0x4e,0x0f]
+# CHECK-NOFP-NOT: vadd.f16 q0, q1, lr  @ encoding: [0x32,0xfe,0x4e,0x0f]
+vadd.f16 q0, q1, lr
+
+# CHECK: vadd.f32 q1, q4, r4  @ encoding: [0x38,0xee,0x44,0x2f]
+# CHECK-NOFP-NOT: vadd.f32 q1, q4, r4  @ encoding: [0x38,0xee,0x44,0x2f]
+vadd.f32 q1, q4, r4
+
+# CHECK: vhsub.s8 q0, q3, lr  @ encoding: [0x06,0xee,0x4e,0x1f]
+# CHECK-NOFP: vhsub.s8 q0, q3, lr  @ encoding: [0x06,0xee,0x4e,0x1f]
+vhsub.s8 q0, q3, lr
+
+# CHECK: vhsub.s16 q0, q0, r6  @ encoding: [0x10,0xee,0x46,0x1f]
+# CHECK-NOFP: vhsub.s16 q0, q0, r6  @ encoding: [0x10,0xee,0x46,0x1f]
+vhsub.s16 q0, q0, r6
+
+# CHECK: vhsub.s32 q1, q2, r7  @ encoding: [0x24,0xee,0x47,0x3f]
+# CHECK-NOFP: vhsub.s32 q1, q2, r7  @ encoding: [0x24,0xee,0x47,0x3f]
+vhsub.s32 q1, q2, r7
+
+# CHECK: vhsub.u8 q1, q6, r5  @ encoding: [0x0c,0xfe,0x45,0x3f]
+# CHECK-NOFP: vhsub.u8 q1, q6, r5  @ encoding: [0x0c,0xfe,0x45,0x3f]
+vhsub.u8 q1, q6, r5
+
+# CHECK: vhsub.u16 q0, q4, r10  @ encoding: [0x18,0xfe,0x4a,0x1f]
+# CHECK-NOFP: vhsub.u16 q0, q4, r10  @ encoding: [0x18,0xfe,0x4a,0x1f]
+vhsub.u16 q0, q4, r10
+
+# CHECK: vhsub.u32 q0, q4, r12  @ encoding: [0x28,0xfe,0x4c,0x1f]
+# CHECK-NOFP: vhsub.u32 q0, q4, r12  @ encoding: [0x28,0xfe,0x4c,0x1f]
+vhsub.u32 q0, q4, r12
+
+# CHECK: vhadd.s8 q0, q2, r1  @ encoding: [0x04,0xee,0x41,0x0f]
+# CHECK-NOFP: vhadd.s8 q0, q2, r1  @ encoding: [0x04,0xee,0x41,0x0f]
+vhadd.s8 q0, q2, r1
+
+# CHECK: vhadd.s16 q0, q2, r1  @ encoding: [0x14,0xee,0x41,0x0f]
+# CHECK-NOFP: vhadd.s16 q0, q2, r1  @ encoding: [0x14,0xee,0x41,0x0f]
+vhadd.s16 q0, q2, r1
+
+# CHECK: vhadd.s32 q0, q0, r10  @ encoding: [0x20,0xee,0x4a,0x0f]
+# CHECK-NOFP: vhadd.s32 q0, q0, r10  @ encoding: [0x20,0xee,0x4a,0x0f]
+vhadd.s32 q0, q0, r10
+
+# CHECK: vhadd.u8 q0, q5, lr  @ encoding: [0x0a,0xfe,0x4e,0x0f]
+# CHECK-NOFP: vhadd.u8 q0, q5, lr  @ encoding: [0x0a,0xfe,0x4e,0x0f]
+vhadd.u8 q0, q5, lr
+
+# CHECK: vhadd.u16 q1, q2, r2  @ encoding: [0x14,0xfe,0x42,0x2f]
+# CHECK-NOFP: vhadd.u16 q1, q2, r2  @ encoding: [0x14,0xfe,0x42,0x2f]
+vhadd.u16 q1, q2, r2
+
+# CHECK: vhadd.u32 q0, q2, r11  @ encoding: [0x24,0xfe,0x4b,0x0f]
+# CHECK-NOFP: vhadd.u32 q0, q2, r11  @ encoding: [0x24,0xfe,0x4b,0x0f]
+vhadd.u32 q0, q2, r11
+
+# CHECK: vqrshl.s8 q0, r0  @ encoding: [0x33,0xee,0xe0,0x1e]
+# CHECK-NOFP: vqrshl.s8 q0, r0  @ encoding: [0x33,0xee,0xe0,0x1e]
+vqrshl.s8 q0, r0
+
+# CHECK: vqrshl.s16 q0, r3  @ encoding: [0x37,0xee,0xe3,0x1e]
+# CHECK-NOFP: vqrshl.s16 q0, r3  @ encoding: [0x37,0xee,0xe3,0x1e]
+vqrshl.s16 q0, r3
+
+# CHECK: vqrshl.s32 q0, lr  @ encoding: [0x3b,0xee,0xee,0x1e]
+# CHECK-NOFP: vqrshl.s32 q0, lr  @ encoding: [0x3b,0xee,0xee,0x1e]
+vqrshl.s32 q0, lr
+
+# CHECK: vqrshl.u8 q0, r0  @ encoding: [0x33,0xfe,0xe0,0x1e]
+# CHECK-NOFP: vqrshl.u8 q0, r0  @ encoding: [0x33,0xfe,0xe0,0x1e]
+vqrshl.u8 q0, r0
+
+# CHECK: vqrshl.u16 q0, r2  @ encoding: [0x37,0xfe,0xe2,0x1e]
+# CHECK-NOFP: vqrshl.u16 q0, r2  @ encoding: [0x37,0xfe,0xe2,0x1e]
+vqrshl.u16 q0, r2
+
+# CHECK: vqrshl.u32 q0, r3  @ encoding: [0x3b,0xfe,0xe3,0x1e]
+# CHECK-NOFP: vqrshl.u32 q0, r3  @ encoding: [0x3b,0xfe,0xe3,0x1e]
+vqrshl.u32 q0, r3
+
+# CHECK: vqshl.s8 q0, r0  @ encoding: [0x31,0xee,0xe0,0x1e]
+# CHECK-NOFP: vqshl.s8 q0, r0  @ encoding: [0x31,0xee,0xe0,0x1e]
+vqshl.s8 q0, r0
+
+# CHECK: vqshl.s16 q1, r1  @ encoding: [0x35,0xee,0xe1,0x3e]
+# CHECK-NOFP: vqshl.s16 q1, r1  @ encoding: [0x35,0xee,0xe1,0x3e]
+vqshl.s16 q1, r1
+
+# CHECK: vqshl.s32 q0, r3  @ encoding: [0x39,0xee,0xe3,0x1e]
+# CHECK-NOFP: vqshl.s32 q0, r3  @ encoding: [0x39,0xee,0xe3,0x1e]
+vqshl.s32 q0, r3
+
+# CHECK: vqshl.u8 q0, r1  @ encoding: [0x31,0xfe,0xe1,0x1e]
+# CHECK-NOFP: vqshl.u8 q0, r1  @ encoding: [0x31,0xfe,0xe1,0x1e]
+vqshl.u8 q0, r1
+
+# CHECK: vqshl.u16 q0, r11  @ encoding: [0x35,0xfe,0xeb,0x1e]
+# CHECK-NOFP: vqshl.u16 q0, r11  @ encoding: [0x35,0xfe,0xeb,0x1e]
+vqshl.u16 q0, r11
+
+# CHECK: vqshl.u32 q0, lr  @ encoding: [0x39,0xfe,0xee,0x1e]
+# CHECK-NOFP: vqshl.u32 q0, lr  @ encoding: [0x39,0xfe,0xee,0x1e]
+vqshl.u32 q0, lr
+
+# CHECK: vrshl.s8 q0, r6  @ encoding: [0x33,0xee,0x66,0x1e]
+# CHECK-NOFP: vrshl.s8 q0, r6  @ encoding: [0x33,0xee,0x66,0x1e]
+vrshl.s8 q0, r6
+
+# CHECK: vrshl.s16 q0, lr  @ encoding: [0x37,0xee,0x6e,0x1e]
+# CHECK-NOFP: vrshl.s16 q0, lr  @ encoding: [0x37,0xee,0x6e,0x1e]
+vrshl.s16 q0, lr
+
+# CHECK: vrshl.s32 q0, r4  @ encoding: [0x3b,0xee,0x64,0x1e]
+# CHECK-NOFP: vrshl.s32 q0, r4  @ encoding: [0x3b,0xee,0x64,0x1e]
+vrshl.s32 q0, r4
+
+# CHECK: vrshl.u8 q0, r0  @ encoding: [0x33,0xfe,0x60,0x1e]
+# CHECK-NOFP: vrshl.u8 q0, r0  @ encoding: [0x33,0xfe,0x60,0x1e]
+vrshl.u8 q0, r0
+
+# CHECK: vrshl.u16 q0, r10  @ encoding: [0x37,0xfe,0x6a,0x1e]
+# CHECK-NOFP: vrshl.u16 q0, r10  @ encoding: [0x37,0xfe,0x6a,0x1e]
+vrshl.u16 q0, r10
+
+# CHECK: vrshl.u32 q0, r1  @ encoding: [0x3b,0xfe,0x61,0x1e]
+# CHECK-NOFP: vrshl.u32 q0, r1  @ encoding: [0x3b,0xfe,0x61,0x1e]
+vrshl.u32 q0, r1
+
+# CHECK: vshl.s8 q0, lr  @ encoding: [0x31,0xee,0x6e,0x1e]
+# CHECK-NOFP: vshl.s8 q0, lr  @ encoding: [0x31,0xee,0x6e,0x1e]
+vshl.s8 q0, lr
+
+# CHECK: vshl.s16 q0, lr  @ encoding: [0x35,0xee,0x6e,0x1e]
+# CHECK-NOFP: vshl.s16 q0, lr  @ encoding: [0x35,0xee,0x6e,0x1e]
+vshl.s16 q0, lr
+
+# CHECK: vshl.s32 q0, r1  @ encoding: [0x39,0xee,0x61,0x1e]
+# CHECK-NOFP: vshl.s32 q0, r1  @ encoding: [0x39,0xee,0x61,0x1e]
+vshl.s32 q0, r1
+
+# CHECK: vshl.u8 q0, r10  @ encoding: [0x31,0xfe,0x6a,0x1e]
+# CHECK-NOFP: vshl.u8 q0, r10  @ encoding: [0x31,0xfe,0x6a,0x1e]
+vshl.u8 q0, r10
+
+# CHECK: vshl.u16 q1, r10  @ encoding: [0x35,0xfe,0x6a,0x3e]
+# CHECK-NOFP: vshl.u16 q1, r10  @ encoding: [0x35,0xfe,0x6a,0x3e]
+vshl.u16 q1, r10
+
+# CHECK: vshl.u32 q0, r12  @ encoding: [0x39,0xfe,0x6c,0x1e]
+# CHECK-NOFP: vshl.u32 q0, r12  @ encoding: [0x39,0xfe,0x6c,0x1e]
+vshl.u32 q0, r12
+
+# CHECK: vbrsr.8 q0, q4, r8  @ encoding: [0x09,0xfe,0x68,0x1e]
+# CHECK-NOFP: vbrsr.8 q0, q4, r8  @ encoding: [0x09,0xfe,0x68,0x1e]
+vbrsr.8 q0, q4, r8
+
+# CHECK: vbrsr.16 q0, q1, r1  @ encoding: [0x13,0xfe,0x61,0x1e]
+# CHECK-NOFP: vbrsr.16 q0, q1, r1  @ encoding: [0x13,0xfe,0x61,0x1e]
+vbrsr.16 q0, q1, r1
+
+# CHECK: vbrsr.32 q0, q6, r0  @ encoding: [0x2d,0xfe,0x60,0x1e]
+# CHECK-NOFP: vbrsr.32 q0, q6, r0  @ encoding: [0x2d,0xfe,0x60,0x1e]
+vbrsr.32 q0, q6, r0
+
+# CHECK: vmul.i8 q0, q0, r12  @ encoding: [0x01,0xee,0x6c,0x1e]
+# CHECK-NOFP: vmul.i8 q0, q0, r12  @ encoding: [0x01,0xee,0x6c,0x1e]
+vmul.i8 q0, q0, r12
+
+# CHECK: vmul.i16 q0, q4, r7  @ encoding: [0x19,0xee,0x67,0x1e]
+# CHECK-NOFP: vmul.i16 q0, q4, r7  @ encoding: [0x19,0xee,0x67,0x1e]
+vmul.i16 q0, q4, r7
+
+# CHECK: vmul.i32 q0, q1, r11  @ encoding: [0x23,0xee,0x6b,0x1e]
+# CHECK-NOFP: vmul.i32 q0, q1, r11  @ encoding: [0x23,0xee,0x6b,0x1e]
+vmul.i32 q0, q1, r11
+
+# CHECK: vmul.f16 q0, q0, r10  @ encoding: [0x31,0xfe,0x6a,0x0e]
+# CHECK-NOFP-NOT: vmul.f16 q0, q0, r10  @ encoding: [0x31,0xfe,0x6a,0x0e]
+vmul.f16 q0, q0, r10
+
+# CHECK: vmul.f32 q0, q1, r7  @ encoding: [0x33,0xee,0x67,0x0e]
+# CHECK-NOFP-NOT: vmul.f32 q0, q1, r7  @ encoding: [0x33,0xee,0x67,0x0e]
+vmul.f32 q0, q1, r7
+
+# CHECK: vqdmulh.s8 q0, q1, r6  @ encoding: [0x03,0xee,0x66,0x0e]
+# CHECK-NOFP: vqdmulh.s8 q0, q1, r6  @ encoding: [0x03,0xee,0x66,0x0e]
+vqdmulh.s8 q0, q1, r6
+
+# CHECK: vqdmulh.s16 q0, q2, r2  @ encoding: [0x15,0xee,0x62,0x0e]
+# CHECK-NOFP: vqdmulh.s16 q0, q2, r2  @ encoding: [0x15,0xee,0x62,0x0e]
+vqdmulh.s16 q0, q2, r2
+
+# CHECK: vqdmulh.s32 q1, q3, r8  @ encoding: [0x27,0xee,0x68,0x2e]
+# CHECK-NOFP: vqdmulh.s32 q1, q3, r8  @ encoding: [0x27,0xee,0x68,0x2e]
+vqdmulh.s32 q1, q3, r8
+
+# CHECK: vqrdmulh.s8 q0, q2, r6  @ encoding: [0x05,0xfe,0x66,0x0e]
+# CHECK-NOFP: vqrdmulh.s8 q0, q2, r6  @ encoding: [0x05,0xfe,0x66,0x0e]
+vqrdmulh.s8 q0, q2, r6
+
+# CHECK: vqrdmulh.s16 q0, q0, r2  @ encoding: [0x11,0xfe,0x62,0x0e]
+# CHECK-NOFP: vqrdmulh.s16 q0, q0, r2  @ encoding: [0x11,0xfe,0x62,0x0e]
+vqrdmulh.s16 q0, q0, r2
+
+# CHECK: vqrdmulh.s32 q0, q0, r2  @ encoding: [0x21,0xfe,0x62,0x0e]
+# CHECK-NOFP: vqrdmulh.s32 q0, q0, r2  @ encoding: [0x21,0xfe,0x62,0x0e]
+vqrdmulh.s32 q0, q0, r2
+
+# CHECK: vfmas.f16 q0, q0, r12  @ encoding: [0x31,0xfe,0x4c,0x1e]
+# CHECK-NOFP-NOT: vfmas.f16 q0, q0, r12  @ encoding: [0x31,0xfe,0x4c,0x1e]
+vfmas.f16 q0, q0, r12
+
+# CHECK: vfmas.f32 q0, q3, lr  @ encoding: [0x37,0xee,0x4e,0x1e]
+# CHECK-NOFP-NOT: vfmas.f32 q0, q3, lr  @ encoding: [0x37,0xee,0x4e,0x1e]
+vfmas.f32 q0, q3, lr
+
+# CHECK: vmlas.s8 q0, q0, r6  @ encoding: [0x01,0xee,0x46,0x1e]
+# CHECK-NOFP: vmlas.s8 q0, q0, r6  @ encoding: [0x01,0xee,0x46,0x1e]
+vmlas.s8 q0, q0, r6
+
+# CHECK: vmlas.s16 q0, q2, r9  @ encoding: [0x15,0xee,0x49,0x1e]
+# CHECK-NOFP: vmlas.s16 q0, q2, r9  @ encoding: [0x15,0xee,0x49,0x1e]
+vmlas.s16 q0, q2, r9
+
+# CHECK: vmlas.s32 q0, q7, r6  @ encoding: [0x2f,0xee,0x46,0x1e]
+# CHECK-NOFP: vmlas.s32 q0, q7, r6  @ encoding: [0x2f,0xee,0x46,0x1e]
+vmlas.s32 q0, q7, r6
+
+# CHECK: vmlas.u8 q0, q5, lr  @ encoding: [0x0b,0xfe,0x4e,0x1e]
+# CHECK-NOFP: vmlas.u8 q0, q5, lr  @ encoding: [0x0b,0xfe,0x4e,0x1e]
+vmlas.u8 q0, q5, lr
+
+# CHECK: vmlas.u16 q0, q3, r12  @ encoding: [0x17,0xfe,0x4c,0x1e]
+# CHECK-NOFP: vmlas.u16 q0, q3, r12  @ encoding: [0x17,0xfe,0x4c,0x1e]
+vmlas.u16 q0, q3, r12
+
+# CHECK: vmlas.u32 q1, q1, r11  @ encoding: [0x23,0xfe,0x4b,0x3e]
+# CHECK-NOFP: vmlas.u32 q1, q1, r11  @ encoding: [0x23,0xfe,0x4b,0x3e]
+vmlas.u32 q1, q1, r11
+
+# CHECK: vfma.f16 q1, q1, r6  @ encoding: [0x33,0xfe,0x46,0x2e]
+# CHECK-NOFP-NOT: vfma.f16 q1, q1, r6  @ encoding: [0x33,0xfe,0x46,0x2e]
+vfma.f16 q1, q1, r6
+
+# CHECK: vfmas.f32 q7, q4, r6  @ encoding: [0x39,0xee,0x46,0xfe]
+# CHECK-NOFP-NOT: vfmas.f32 q7, q4, r6  @ encoding: [0x39,0xee,0x46,0xfe]
+vfmas.f32 q7, q4, r6
+
+# CHECK: vmla.s8 q0, q3, r8  @ encoding: [0x07,0xee,0x48,0x0e]
+# CHECK-NOFP: vmla.s8 q0, q3, r8  @ encoding: [0x07,0xee,0x48,0x0e]
+vmla.s8 q0, q3, r8
+
+# CHECK: vmla.s16 q1, q3, r10  @ encoding: [0x17,0xee,0x4a,0x2e]
+# CHECK-NOFP: vmla.s16 q1, q3, r10  @ encoding: [0x17,0xee,0x4a,0x2e]
+vmla.s16 q1, q3, r10
+
+# CHECK: vmla.s32 q1, q3, r1  @ encoding: [0x27,0xee,0x41,0x2e]
+# CHECK-NOFP: vmla.s32 q1, q3, r1  @ encoding: [0x27,0xee,0x41,0x2e]
+vmla.s32 q1, q3, r1
+
+# CHECK: vmla.u8 q0, q7, r10  @ encoding: [0x0f,0xfe,0x4a,0x0e]
+# CHECK-NOFP: vmla.u8 q0, q7, r10  @ encoding: [0x0f,0xfe,0x4a,0x0e]
+vmla.u8 q0, q7, r10
+
+# CHECK: vmla.u16 q0, q0, r7  @ encoding: [0x11,0xfe,0x47,0x0e]
+# CHECK-NOFP: vmla.u16 q0, q0, r7  @ encoding: [0x11,0xfe,0x47,0x0e]
+vmla.u16 q0, q0, r7
+
+# CHECK: vmla.u32 q1, q6, r10  @ encoding: [0x2d,0xfe,0x4a,0x2e]
+# CHECK-NOFP: vmla.u32 q1, q6, r10  @ encoding: [0x2d,0xfe,0x4a,0x2e]
+vmla.u32 q1, q6, r10
+
+# CHECK: vqdmlash.s8 q0, q0, r5  @ encoding: [0x00,0xee,0x65,0x1e]
+# CHECK-NOFP: vqdmlash.s8 q0, q0, r5  @ encoding: [0x00,0xee,0x65,0x1e]
+vqdmlash.s8 q0, q0, r5
+
+# CHECK: vqdmlash.s16 q0, q5, lr  @ encoding: [0x1a,0xee,0x6e,0x1e]
+# CHECK-NOFP: vqdmlash.s16 q0, q5, lr  @ encoding: [0x1a,0xee,0x6e,0x1e]
+vqdmlash.s16 q0, q5, lr
+
+# CHECK: vqdmlash.s32 q0, q2, r3  @ encoding: [0x24,0xee,0x63,0x1e]
+# CHECK-NOFP: vqdmlash.s32 q0, q2, r3  @ encoding: [0x24,0xee,0x63,0x1e]
+vqdmlash.s32 q0, q2, r3
+
+# CHECK: vqdmlash.u8 q0, q4, r2  @ encoding: [0x08,0xfe,0x62,0x1e]
+# CHECK-NOFP: vqdmlash.u8 q0, q4, r2  @ encoding: [0x08,0xfe,0x62,0x1e]
+vqdmlash.u8 q0, q4, r2
+
+# CHECK: vqdmlash.u16 q1, q4, r2  @ encoding: [0x18,0xfe,0x62,0x3e]
+# CHECK-NOFP: vqdmlash.u16 q1, q4, r2  @ encoding: [0x18,0xfe,0x62,0x3e]
+vqdmlash.u16 q1, q4, r2
+
+# CHECK: vqdmlash.u32 q1, q5, r0  @ encoding: [0x2a,0xfe,0x60,0x3e]
+# CHECK-NOFP: vqdmlash.u32 q1, q5, r0  @ encoding: [0x2a,0xfe,0x60,0x3e]
+vqdmlash.u32 q1, q5, r0
+
+# CHECK: vqdmlah.s8 q0, q3, r3  @ encoding: [0x06,0xee,0x63,0x0e]
+# CHECK-NOFP: vqdmlah.s8 q0, q3, r3  @ encoding: [0x06,0xee,0x63,0x0e]
+vqdmlah.s8 q0, q3, r3
+
+# CHECK: vqdmlah.s16 q5, q3, r9  @ encoding: [0x16,0xee,0x69,0xae]
+# CHECK-NOFP: vqdmlah.s16 q5, q3, r9  @ encoding: [0x16,0xee,0x69,0xae]
+vqdmlah.s16 q5, q3, r9
+
+# CHECK: vqdmlah.s32 q0, q1, r11  @ encoding: [0x22,0xee,0x6b,0x0e]
+# CHECK-NOFP: vqdmlah.s32 q0, q1, r11  @ encoding: [0x22,0xee,0x6b,0x0e]
+vqdmlah.s32 q0, q1, r11
+
+# CHECK: vqdmlah.u8 q0, q2, lr  @ encoding: [0x04,0xfe,0x6e,0x0e]
+# CHECK-NOFP: vqdmlah.u8 q0, q2, lr  @ encoding: [0x04,0xfe,0x6e,0x0e]
+vqdmlah.u8 q0, q2, lr
+
+# CHECK: vqdmlah.u16 q0, q3, r10  @ encoding: [0x16,0xfe,0x6a,0x0e]
+# CHECK-NOFP: vqdmlah.u16 q0, q3, r10  @ encoding: [0x16,0xfe,0x6a,0x0e]
+vqdmlah.u16 q0, q3, r10
+
+# CHECK: vqdmlah.u32 q1, q5, r2  @ encoding: [0x2a,0xfe,0x62,0x2e]
+# CHECK-NOFP: vqdmlah.u32 q1, q5, r2  @ encoding: [0x2a,0xfe,0x62,0x2e]
+vqdmlah.u32 q1, q5, r2
+
+# CHECK: vqrdmlash.s8 q0, q5, r10  @ encoding: [0x0a,0xee,0x4a,0x1e]
+# CHECK-NOFP: vqrdmlash.s8 q0, q5, r10  @ encoding: [0x0a,0xee,0x4a,0x1e]
+vqrdmlash.s8 q0, q5, r10
+
+# CHECK: vqrdmlash.s16 q0, q3, r2  @ encoding: [0x16,0xee,0x42,0x1e]
+# CHECK-NOFP: vqrdmlash.s16 q0, q3, r2  @ encoding: [0x16,0xee,0x42,0x1e]
+vqrdmlash.s16 q0, q3, r2
+
+# CHECK: vqrdmlash.s32 q0, q0, r4  @ encoding: [0x20,0xee,0x44,0x1e]
+# CHECK-NOFP: vqrdmlash.s32 q0, q0, r4  @ encoding: [0x20,0xee,0x44,0x1e]
+vqrdmlash.s32 q0, q0, r4
+
+# CHECK: vqrdmlash.u8 q0, q4, r9  @ encoding: [0x08,0xfe,0x49,0x1e]
+# CHECK-NOFP: vqrdmlash.u8 q0, q4, r9  @ encoding: [0x08,0xfe,0x49,0x1e]
+vqrdmlash.u8 q0, q4, r9
+
+# CHECK: vqrdmlash.u16 q0, q6, r12  @ encoding: [0x1c,0xfe,0x4c,0x1e]
+# CHECK-NOFP: vqrdmlash.u16 q0, q6, r12  @ encoding: [0x1c,0xfe,0x4c,0x1e]
+vqrdmlash.u16 q0, q6, r12
+
+# CHECK: vqrdmlash.u32 q0, q3, r7  @ encoding: [0x26,0xfe,0x47,0x1e]
+# CHECK-NOFP: vqrdmlash.u32 q0, q3, r7  @ encoding: [0x26,0xfe,0x47,0x1e]
+vqrdmlash.u32 q0, q3, r7
+
+# CHECK: vqrdmlah.s8 q0, q5, r11  @ encoding: [0x0a,0xee,0x4b,0x0e]
+# CHECK-NOFP: vqrdmlah.s8 q0, q5, r11  @ encoding: [0x0a,0xee,0x4b,0x0e]
+vqrdmlah.s8 q0, q5, r11
+
+# CHECK: vqrdmlah.s16 q0, q2, r10  @ encoding: [0x14,0xee,0x4a,0x0e]
+# CHECK-NOFP: vqrdmlah.s16 q0, q2, r10  @ encoding: [0x14,0xee,0x4a,0x0e]
+vqrdmlah.s16 q0, q2, r10
+
+# CHECK: vqrdmlah.s32 q0, q4, r11  @ encoding: [0x28,0xee,0x4b,0x0e]
+# CHECK-NOFP: vqrdmlah.s32 q0, q4, r11  @ encoding: [0x28,0xee,0x4b,0x0e]
+vqrdmlah.s32 q0, q4, r11
+
+# CHECK: vqrdmlah.u8 q0, q4, r2  @ encoding: [0x08,0xfe,0x42,0x0e]
+# CHECK-NOFP: vqrdmlah.u8 q0, q4, r2  @ encoding: [0x08,0xfe,0x42,0x0e]
+vqrdmlah.u8 q0, q4, r2
+
+# CHECK: vqrdmlah.u16 q0, q6, r1  @ encoding: [0x1c,0xfe,0x41,0x0e]
+# CHECK-NOFP: vqrdmlah.u16 q0, q6, r1  @ encoding: [0x1c,0xfe,0x41,0x0e]
+vqrdmlah.u16 q0, q6, r1
+
+# CHECK: vqrdmlah.u32 q0, q4, r2  @ encoding: [0x28,0xfe,0x42,0x0e]
+# CHECK-NOFP: vqrdmlah.u32 q0, q4, r2  @ encoding: [0x28,0xfe,0x42,0x0e]
+vqrdmlah.u32 q0, q4, r2
+
+# CHECK: viwdup.u8 q0, lr, r1, #1  @ encoding: [0x0f,0xee,0x60,0x0f]
+# CHECK-NOFP: viwdup.u8 q0, lr, r1, #1  @ encoding: [0x0f,0xee,0x60,0x0f]
+viwdup.u8 q0, lr, r1, #1
+
+# CHECK: viwdup.u16 q1, r10, r1, #8  @ encoding: [0x1b,0xee,0xe1,0x2f]
+# CHECK-NOFP: viwdup.u16 q1, r10, r1, #8  @ encoding: [0x1b,0xee,0xe1,0x2f]
+viwdup.u16 q1, r10, r1, #8
+
+# CHECK: viwdup.u32 q6, r10, r5, #4  @ encoding: [0x2b,0xee,0xe4,0xcf]
+# CHECK-NOFP: viwdup.u32 q6, r10, r5, #4  @ encoding: [0x2b,0xee,0xe4,0xcf]
+viwdup.u32 q6, r10, r5, #4
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector increment immediate must be 1, 2, 4 or 8
+viwdup.u32 q6, r10, r5, #3
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an even-numbered register
+viwdup.u32 q6, r3, r5, #4
+
+# CHECK: vdwdup.u8 q0, r12, r11, #8  @ encoding: [0x0d,0xee,0xeb,0x1f]
+# CHECK-NOFP: vdwdup.u8 q0, r12, r11, #8  @ encoding: [0x0d,0xee,0xeb,0x1f]
+vdwdup.u8 q0, r12, r11, #8
+
+# CHECK: vdwdup.u16 q0, r12, r1, #2  @ encoding: [0x1d,0xee,0x61,0x1f]
+# CHECK-NOFP: vdwdup.u16 q0, r12, r1, #2  @ encoding: [0x1d,0xee,0x61,0x1f]
+vdwdup.u16 q0, r12, r1, #2
+
+# CHECK: vdwdup.u32 q0, r0, r7, #8  @ encoding: [0x21,0xee,0xe7,0x1f]
+# CHECK-NOFP: vdwdup.u32 q0, r0, r7, #8  @ encoding: [0x21,0xee,0xe7,0x1f]
+vdwdup.u32 q0, r0, r7, #8
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector increment immediate must be 1, 2, 4 or 8
+vdwdup.u32 q0, r0, r7, #9
+
+# CHECK: vidup.u8 q0, lr, #2  @ encoding: [0x0f,0xee,0x6f,0x0f]
+# CHECK-NOFP: vidup.u8 q0, lr, #2  @ encoding: [0x0f,0xee,0x6f,0x0f]
+vidup.u8 q0, lr, #2
+
+# CHECK: vidup.u16 q0, lr, #4  @ encoding: [0x1f,0xee,0xee,0x0f]
+# CHECK-NOFP: vidup.u16 q0, lr, #4  @ encoding: [0x1f,0xee,0xee,0x0f]
+vidup.u16 q0, lr, #4
+
+# CHECK: vidup.u32 q0, r12, #1  @ encoding: [0x2d,0xee,0x6e,0x0f]
+# CHECK-NOFP: vidup.u32 q0, r12, #1  @ encoding: [0x2d,0xee,0x6e,0x0f]
+vidup.u32 q0, r12, #1
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector increment immediate must be 1, 2, 4 or 8
+vidup.u32 q0, r12, #3
+
+# CHECK: vddup.u8 q0, r4, #4  @ encoding: [0x05,0xee,0xee,0x1f]
+# CHECK-NOFP: vddup.u8 q0, r4, #4  @ encoding: [0x05,0xee,0xee,0x1f]
+vddup.u8 q0, r4, #4
+
+# CHECK: vddup.u16 q0, r10, #4  @ encoding: [0x1b,0xee,0xee,0x1f]
+# CHECK-NOFP: vddup.u16 q0, r10, #4  @ encoding: [0x1b,0xee,0xee,0x1f]
+vddup.u16 q0, r10, #4
+
+# CHECK: vddup.u32 q2, r0, #8  @ encoding: [0x21,0xee,0xef,0x5f]
+# CHECK-NOFP: vddup.u32 q2, r0, #8  @ encoding: [0x21,0xee,0xef,0x5f]
+vddup.u32 q2, r0, #8
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector increment immediate must be 1, 2, 4 or 8
+vddup.u32 q2, r0, #5
+
+# CHECK: vctp.8 lr  @ encoding: [0x0e,0xf0,0x01,0xe8]
+# CHECK-NOFP: vctp.8 lr  @ encoding: [0x0e,0xf0,0x01,0xe8]
+vctp.8 lr
+
+# CHECK: vctp.16 r0  @ encoding: [0x10,0xf0,0x01,0xe8]
+# CHECK-NOFP: vctp.16 r0  @ encoding: [0x10,0xf0,0x01,0xe8]
+vctp.16 r0
+
+# CHECK: vctp.32 r10  @ encoding: [0x2a,0xf0,0x01,0xe8]
+# CHECK-NOFP: vctp.32 r10  @ encoding: [0x2a,0xf0,0x01,0xe8]
+vctp.32 r10
+
+# CHECK: vctp.64 r1  @ encoding: [0x31,0xf0,0x01,0xe8]
+# CHECK-NOFP: vctp.64 r1  @ encoding: [0x31,0xf0,0x01,0xe8]
+vctp.64 r1
+
+vpste
+vmult.i8 q0, q1, q2
+vmule.i16 q0, q1, q2
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vmult.i8  q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x09]
+# CHECK-NOFP: vmult.i8  q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x09]
+# CHECK: vmule.i16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x09]
+# CHECK-NOFP: vmule.i16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x09]
+
+vpste
+vmult.i16 q0, q1, q2
+vmule.i16 q1, q2, q3
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vmult.i16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x09]
+# CHECK-NOFP: vmult.i16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x09]
+# CHECK: vmule.i16 q1, q2, q3 @ encoding: [0x14,0xef,0x56,0x29]
+# CHECK-NOFP: vmule.i16 q1, q2, q3 @ encoding: [0x14,0xef,0x56,0x29]
+
+vqrshl.u32 q0, r0
+# CHECK: vqrshl.u32 q0, r0 @ encoding: [0x3b,0xfe,0xe0,0x1e]
+# CHECK-NOFP: vqrshl.u32 q0, r0 @ encoding: [0x3b,0xfe,0xe0,0x1e]
+
+vpste
+vqrshlt.u16 q0, r0
+vqrshle.s16 q0, q1, q2
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vqrshlt.u16 q0, r0 @ encoding: [0x37,0xfe,0xe0,0x1e]
+# CHECK-NOFP: vqrshlt.u16 q0, r0 @ encoding: [0x37,0xfe,0xe0,0x1e]
+# CHECK: vqrshle.s16 q0, q1, q2 @ encoding: [0x14,0xef,0x52,0x05]
+# CHECK-NOFP: vqrshle.s16 q0, q1, q2 @ encoding: [0x14,0xef,0x52,0x05]
+
+vpste
+vrshlt.u16 q0, q1, q2
+vrshle.s32 q0, r0
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vrshlt.u16 q0, q1, q2 @ encoding: [0x14,0xff,0x42,0x05]
+# CHECK-NOFP: vrshlt.u16 q0, q1, q2 @ encoding: [0x14,0xff,0x42,0x05]
+# CHECK: vrshle.s32 q0, r0 @ encoding: [0x3b,0xee,0x60,0x1e]
+# CHECK-NOFP: vrshle.s32 q0, r0 @ encoding: [0x3b,0xee,0x60,0x1e]
+
+vpste
+vshlt.s8 q0, r0
+vshle.u32 q0, r0
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vshlt.s8 q0, r0 @ encoding: [0x31,0xee,0x60,0x1e]
+# CHECK-NOFP: vshlt.s8 q0, r0 @ encoding: [0x31,0xee,0x60,0x1e]
+# CHECK: vshle.u32 q0, r0 @ encoding: [0x39,0xfe,0x60,0x1e]
+# CHECK-NOFP: vshle.u32 q0, r0 @ encoding: [0x39,0xfe,0x60,0x1e]

llvm/test/MC/ARM/mve-reductions.s

 vabav.u16 r0, q1, q3
 
 # CHECK: vabav.u32  r0, q1, q3 @ encoding: [0xa2,0xfe,0x07,0x0f]
 vabav.u32 r0, q1, q3
 
 # CHECK: vaddv.s16 lr, q0  @ encoding: [0xf5,0xee,0x00,0xef]
 vaddv.s16 lr, q0
 
-# ERROR: [[@LINE+1]]:11: {{error|note}}: invalid operand for instruction
+# ERROR: [[@LINE+1]]:11: {{error|note}}: operand must be an even-numbered register
 vaddv.s16 r1, q0
 
 # CHECK: vpte.i8 eq, q0, q0
 # CHECK: vaddvt.s16 r0, q6  @ encoding: [0xf5,0xee,0x0c,0x0f]
 # CHECK: vaddve.s16 r0, q6  @ encoding: [0xf5,0xee,0x0c,0x0f]
 vpte.i8 eq, q0, q0
 vaddvt.s16 r0, q6
 vaddve.s16 r0, q6
 
 # CHECK: vaddva.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
 vaddva.s16 lr, q0
 
 # CHECK: vpte.i8 eq, q0, q0
 # CHECK: vaddvat.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
 # CHECK: vaddvae.s16 lr, q0  @ encoding: [0xf5,0xee,0x20,0xef]
 vpte.i8 eq, q0, q0
 vaddvat.s16 lr, q0
 vaddvae.s16 lr, q0
 
 # CHECK: vaddlv.s32 r0, r9, q2  @ encoding: [0xc9,0xee,0x04,0x0f]
 vaddlv.s32 r0, r9, q2
 
-# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an odd-numbered register in range [r1,r11]
 vaddlv.s32 r0, r2, q2
 
-# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an even-numbered register
 vaddlv.s32 r1, r3, q2
 
 # CHECK: vaddlv.u32 r0, r1, q1  @ encoding: [0x89,0xfe,0x02,0x0f]
 vaddlv.u32 r0, r1, q1
 
 # CHECK: vminv.s8 lr, q0  @ encoding: [0xe2,0xee,0x80,0xef]
 vminv.s8 lr, q0
 

 vrmlaldavh.s32 lr, r1, q6, q2
 
 # CHECK: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
 vrmlaldavh.u32 lr, r1, q5, q2
 
 # CHECK: vrmlalvh.u32 lr, r1, q5, q2  @ encoding: [0x8a,0xfe,0x04,0xef]
 vrmlaldavh.u32 lr, r1, q5, q2
 
-# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an even-numbered register
 vrmlaldavh.u32 r1, r3, q5, q2
 
-# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be an odd-numbered register in range [r1,r11]
 vrmlaldavh.u32 r2, r4, q5, q2
 
 # CHECK: vrmlaldavhax.s32 lr, r1, q3, q0  @ encoding: [0x86,0xee,0x20,0xff]
 vrmlaldavhax.s32 lr, r1, q3, q0
 
 # CHECK: vrmlsldavh.s32 lr, r11, q6, q5  @ encoding: [0xdc,0xfe,0x0b,0xee]
 vrmlsldavh.s32 lr, r11, q6, q5
 

llvm/test/MC/ARM/mve-scalar-shift.s

 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
 asrl    r3, r2, #33
 
 # ERROR: [[@LINE+3]]:{{[0-9]+}}: {{error|note}}: operand must be an immediate in the range [1,32]
 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
 asrl    r0, r1, #33
 
-# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be an odd-numbered register in range [r1,r11]
 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
 asrl    r0, r0, #32
 
 # CHECK: asrl    r0, r1, r4  @ encoding: [0x50,0xea,0x2d,0x41]
 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
 asrl    r0, r1, r4
 
-# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be an odd-numbered register in range [r1,r11]
 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
 asrl    r0, r0, r4
 
 # The assembler will reject the above shifts when MVE is not supported,
 # so the previous valid instruction will be IT EQ, so we need to add
 # a NOPEQ:
 nopeq
 

llvm/test/MC/Disassembler/ARM/mve-qdest-rsrc.txt

+# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
+# RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
+
+# CHECK: vsub.i8 q0, q3, r3  @ encoding: [0x07,0xee,0x43,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x07,0xee,0x43,0x1f]
+
+# CHECK: vsub.i16 q0, q7, lr  @ encoding: [0x1f,0xee,0x4e,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1f,0xee,0x4e,0x1f]
+
+# CHECK: vsub.i32 q1, q5, r10  @ encoding: [0x2b,0xee,0x4a,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2b,0xee,0x4a,0x3f]
+
+# CHECK: vadd.i8 q1, q4, r7  @ encoding: [0x09,0xee,0x47,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x09,0xee,0x47,0x2f]
+
+# CHECK: vadd.i16 q0, q6, r11  @ encoding: [0x1d,0xee,0x4b,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1d,0xee,0x4b,0x0f]
+
+# CHECK: vadd.i32 q0, q1, r6  @ encoding: [0x23,0xee,0x46,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x23,0xee,0x46,0x0f]
+
+# CHECK: vqsub.s8 q2, q2, r8  @ encoding: [0x04,0xee,0x68,0x5f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xee,0x68,0x5f]
+
+# CHECK: vqsub.s16 q1, q4, r0  @ encoding: [0x18,0xee,0x60,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xee,0x60,0x3f]
+
+# CHECK: vqsub.s32 q0, q2, r0  @ encoding: [0x24,0xee,0x60,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xee,0x60,0x1f]
+
+# CHECK: vqsub.u8 q0, q1, r2  @ encoding: [0x02,0xfe,0x62,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xfe,0x62,0x1f]
+
+# CHECK: vqsub.u16 q0, q2, r6  @ encoding: [0x14,0xfe,0x66,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xfe,0x66,0x1f]
+
+# CHECK: vqsub.u32 q0, q2, r2  @ encoding: [0x24,0xfe,0x62,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xfe,0x62,0x1f]
+
+# CHECK: vqadd.s8 q0, q6, r1  @ encoding: [0x0c,0xee,0x61,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xee,0x61,0x0f]
+
+# CHECK: vqadd.s16 q3, q4, r2  @ encoding: [0x18,0xee,0x62,0x6f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xee,0x62,0x6f]
+
+# CHECK: vqadd.s32 q0, q5, r11  @ encoding: [0x2a,0xee,0x6b,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xee,0x6b,0x0f]
+
+# CHECK: vqadd.u8 q0, q1, r8  @ encoding: [0x02,0xfe,0x68,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xfe,0x68,0x0f]
+
+# CHECK: vqadd.u16 q0, q5, r9  @ encoding: [0x1a,0xfe,0x69,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xfe,0x69,0x0f]
+
+# CHECK: vqadd.u32 q0, q0, r7  @ encoding: [0x20,0xfe,0x67,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xfe,0x67,0x0f]
+
+# CHECK: vqdmullb.s16 q0, q1, r6  @ encoding: [0x32,0xee,0x66,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xee,0x66,0x0f]
+
+# CHECK: vqdmullb.s32 q0, q3, q7  @ encoding: [0x36,0xfe,0x0f,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x36,0xfe,0x0f,0x0f]
+
+# CHECK: vqdmullt.s16 q0, q1, r0  @ encoding: [0x32,0xee,0x60,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xee,0x60,0x1f]
+
+# CHECK: vqdmullt.s32 q0, q4, r5  @ encoding: [0x38,0xfe,0x65,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x38,0xfe,0x65,0x1f]
+
+# CHECK: vsub.f16 q0, q3, r7  @ encoding: [0x36,0xfe,0x47,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x36,0xfe,0x47,0x1f]
+
+# CHECK: vsub.f32 q1, q1, r10  @ encoding: [0x32,0xee,0x4a,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xee,0x4a,0x3f]
+
+# CHECK: vadd.f16 q0, q1, lr  @ encoding: [0x32,0xfe,0x4e,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x32,0xfe,0x4e,0x0f]
+
+# CHECK: vadd.f32 q1, q4, r4  @ encoding: [0x38,0xee,0x44,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x38,0xee,0x44,0x2f]
+
+# CHECK: vhsub.s8 q0, q3, lr  @ encoding: [0x06,0xee,0x4e,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x06,0xee,0x4e,0x1f]
+
+# CHECK: vhsub.s16 q0, q0, r6  @ encoding: [0x10,0xee,0x46,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x10,0xee,0x46,0x1f]
+
+# CHECK: vhsub.s32 q1, q2, r7  @ encoding: [0x24,0xee,0x47,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xee,0x47,0x3f]
+
+# CHECK: vhsub.u8 q1, q6, r5  @ encoding: [0x0c,0xfe,0x45,0x3f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0c,0xfe,0x45,0x3f]
+
+# CHECK: vhsub.u16 q0, q4, r10  @ encoding: [0x18,0xfe,0x4a,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xfe,0x4a,0x1f]
+
+# CHECK: vhsub.u32 q0, q4, r12  @ encoding: [0x28,0xfe,0x4c,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xfe,0x4c,0x1f]
+
+# CHECK: vhadd.s8 q0, q2, r1  @ encoding: [0x04,0xee,0x41,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xee,0x41,0x0f]
+
+# CHECK: vhadd.s16 q0, q2, r1  @ encoding: [0x14,0xee,0x41,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xee,0x41,0x0f]
+
+# CHECK: vhadd.s32 q0, q0, r10  @ encoding: [0x20,0xee,0x4a,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xee,0x4a,0x0f]
+
+# CHECK: vhadd.u8 q0, q5, lr  @ encoding: [0x0a,0xfe,0x4e,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0a,0xfe,0x4e,0x0f]
+
+# CHECK: vhadd.u16 q1, q2, r2  @ encoding: [0x14,0xfe,0x42,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xfe,0x42,0x2f]
+
+# CHECK: vhadd.u32 q0, q2, r11  @ encoding: [0x24,0xfe,0x4b,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xfe,0x4b,0x0f]
+
+# CHECK: vqrshl.s8 q0, r0  @ encoding: [0x33,0xee,0xe0,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0xe0,0x1e]
+
+# CHECK: vqrshl.s16 q0, r3  @ encoding: [0x37,0xee,0xe3,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0xe3,0x1e]
+
+# CHECK: vqrshl.s32 q0, lr  @ encoding: [0x3b,0xee,0xee,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xee,0xee,0x1e]
+
+# CHECK: vqrshl.u8 q0, r0  @ encoding: [0x33,0xfe,0xe0,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfe,0xe0,0x1e]
+
+# CHECK: vqrshl.u16 q0, r2  @ encoding: [0x37,0xfe,0xe2,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xfe,0xe2,0x1e]
+
+# CHECK: vqrshl.u32 q0, r3  @ encoding: [0x3b,0xfe,0xe3,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xfe,0xe3,0x1e]
+
+# CHECK: vqshl.s8 q0, r0  @ encoding: [0x31,0xee,0xe0,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xee,0xe0,0x1e]
+
+# CHECK: vqshl.s16 q1, r1  @ encoding: [0x35,0xee,0xe1,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xee,0xe1,0x3e]
+
+# CHECK: vqshl.s32 q0, r3  @ encoding: [0x39,0xee,0xe3,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x39,0xee,0xe3,0x1e]
+
+# CHECK: vqshl.u8 q0, r1  @ encoding: [0x31,0xfe,0xe1,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0xe1,0x1e]
+
+# CHECK: vqshl.u16 q0, r11  @ encoding: [0x35,0xfe,0xeb,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xfe,0xeb,0x1e]
+
+# CHECK: vqshl.u32 q0, lr  @ encoding: [0x39,0xfe,0xee,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x39,0xfe,0xee,0x1e]
+
+# CHECK: vrshl.s8 q0, r6  @ encoding: [0x33,0xee,0x66,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x66,0x1e]
+
+# CHECK: vrshl.s16 q0, lr  @ encoding: [0x37,0xee,0x6e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x6e,0x1e]
+
+# CHECK: vrshl.s32 q0, r4  @ encoding: [0x3b,0xee,0x64,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xee,0x64,0x1e]
+
+# CHECK: vrshl.u8 q0, r0  @ encoding: [0x33,0xfe,0x60,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfe,0x60,0x1e]
+
+# CHECK: vrshl.u16 q0, r10  @ encoding: [0x37,0xfe,0x6a,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xfe,0x6a,0x1e]
+
+# CHECK: vrshl.u32 q0, r1  @ encoding: [0x3b,0xfe,0x61,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xfe,0x61,0x1e]
+
+# CHECK: vshl.s8 q0, lr  @ encoding: [0x31,0xee,0x6e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xee,0x6e,0x1e]
+
+# CHECK: vshl.s16 q0, lr  @ encoding: [0x35,0xee,0x6e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xee,0x6e,0x1e]
+
+# CHECK: vshl.s32 q0, r1  @ encoding: [0x39,0xee,0x61,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x39,0xee,0x61,0x1e]
+
+# CHECK: vshl.u8 q0, r10  @ encoding: [0x31,0xfe,0x6a,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x6a,0x1e]
+
+# CHECK: vshl.u16 q1, r10  @ encoding: [0x35,0xfe,0x6a,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x35,0xfe,0x6a,0x3e]
+
+# CHECK: vshl.u32 q0, r12  @ encoding: [0x39,0xfe,0x6c,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x39,0xfe,0x6c,0x1e]
+
+# CHECK: vbrsr.8 q0, q4, r8  @ encoding: [0x09,0xfe,0x68,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x09,0xfe,0x68,0x1e]
+
+# CHECK: vbrsr.16 q0, q1, r1  @ encoding: [0x13,0xfe,0x61,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x13,0xfe,0x61,0x1e]
+
+# CHECK: vbrsr.32 q0, q6, r0  @ encoding: [0x2d,0xfe,0x60,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2d,0xfe,0x60,0x1e]
+
+# CHECK: vmul.i8 q0, q0, r12  @ encoding: [0x01,0xee,0x6c,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x01,0xee,0x6c,0x1e]
+
+# CHECK: vmul.i16 q0, q4, r7  @ encoding: [0x19,0xee,0x67,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x19,0xee,0x67,0x1e]
+
+# CHECK: vmul.i32 q0, q1, r11  @ encoding: [0x23,0xee,0x6b,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x23,0xee,0x6b,0x1e]
+
+# CHECK: vmul.f16 q0, q0, r10  @ encoding: [0x31,0xfe,0x6a,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x6a,0x0e]
+
+# CHECK: vmul.f32 q0, q1, r7  @ encoding: [0x33,0xee,0x67,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xee,0x67,0x0e]
+
+# CHECK: vqdmulh.s8 q0, q1, r6  @ encoding: [0x03,0xee,0x66,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x03,0xee,0x66,0x0e]
+
+# CHECK: vqdmulh.s16 q0, q2, r2  @ encoding: [0x15,0xee,0x62,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x15,0xee,0x62,0x0e]
+
+# CHECK: vqdmulh.s32 q1, q3, r8  @ encoding: [0x27,0xee,0x68,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x27,0xee,0x68,0x2e]
+
+# CHECK: vqrdmulh.s8 q0, q2, r6  @ encoding: [0x05,0xfe,0x66,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x05,0xfe,0x66,0x0e]
+
+# CHECK: vqrdmulh.s16 q0, q0, r2  @ encoding: [0x11,0xfe,0x62,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x11,0xfe,0x62,0x0e]
+
+# CHECK: vqrdmulh.s32 q0, q0, r2  @ encoding: [0x21,0xfe,0x62,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x21,0xfe,0x62,0x0e]
+
+# CHECK: vfmas.f16 q0, q0, r12  @ encoding: [0x31,0xfe,0x4c,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x4c,0x1e]
+
+# CHECK: vfmas.f32 q0, q3, lr  @ encoding: [0x37,0xee,0x4e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x37,0xee,0x4e,0x1e]
+
+# CHECK: vmlas.s8 q0, q0, r6  @ encoding: [0x01,0xee,0x46,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x01,0xee,0x46,0x1e]
+
+# CHECK: vmlas.s16 q0, q2, r9  @ encoding: [0x15,0xee,0x49,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x15,0xee,0x49,0x1e]
+
+# CHECK: vmlas.s32 q0, q7, r6  @ encoding: [0x2f,0xee,0x46,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2f,0xee,0x46,0x1e]
+
+# CHECK: vmlas.u8 q0, q5, lr  @ encoding: [0x0b,0xfe,0x4e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0b,0xfe,0x4e,0x1e]
+
+# CHECK: vmlas.u16 q0, q3, r12  @ encoding: [0x17,0xfe,0x4c,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x17,0xfe,0x4c,0x1e]
+
+# CHECK: vmlas.u32 q1, q1, r11  @ encoding: [0x23,0xfe,0x4b,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x23,0xfe,0x4b,0x3e]
+
+# CHECK: vfma.f16 q1, q1, r6  @ encoding: [0x33,0xfe,0x46,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x33,0xfe,0x46,0x2e]
+
+# CHECK: vfmas.f32 q7, q4, r6  @ encoding: [0x39,0xee,0x46,0xfe]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x39,0xee,0x46,0xfe]
+
+# CHECK: vmla.s8 q0, q3, r8  @ encoding: [0x07,0xee,0x48,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x07,0xee,0x48,0x0e]
+
+# CHECK: vmla.s16 q1, q3, r10  @ encoding: [0x17,0xee,0x4a,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x17,0xee,0x4a,0x2e]
+
+# CHECK: vmla.s32 q1, q3, r1  @ encoding: [0x27,0xee,0x41,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x27,0xee,0x41,0x2e]
+
+# CHECK: vmla.u8 q0, q7, r10  @ encoding: [0x0f,0xfe,0x4a,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0f,0xfe,0x4a,0x0e]
+
+# CHECK: vmla.u16 q0, q0, r7  @ encoding: [0x11,0xfe,0x47,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x11,0xfe,0x47,0x0e]
+
+# CHECK: vmla.u32 q1, q6, r10  @ encoding: [0x2d,0xfe,0x4a,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2d,0xfe,0x4a,0x2e]
+
+# CHECK: vqdmlash.s8 q0, q0, r5  @ encoding: [0x00,0xee,0x65,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xee,0x65,0x1e]
+
+# CHECK: vqdmlash.s16 q0, q5, lr  @ encoding: [0x1a,0xee,0x6e,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1a,0xee,0x6e,0x1e]
+
+# CHECK: vqdmlash.s32 q0, q2, r3  @ encoding: [0x24,0xee,0x63,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x24,0xee,0x63,0x1e]
+
+# CHECK: vqdmlash.u8 q0, q4, r2  @ encoding: [0x08,0xfe,0x62,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xfe,0x62,0x1e]
+
+# CHECK: vqdmlash.u16 q1, q4, r2  @ encoding: [0x18,0xfe,0x62,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x18,0xfe,0x62,0x3e]
+
+# CHECK: vqdmlash.u32 q1, q5, r0  @ encoding: [0x2a,0xfe,0x60,0x3e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xfe,0x60,0x3e]
+
+# CHECK: vqdmlah.s8 q0, q3, r3  @ encoding: [0x06,0xee,0x63,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x06,0xee,0x63,0x0e]
+
+# CHECK: vqdmlah.s16 q5, q3, r9  @ encoding: [0x16,0xee,0x69,0xae]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xee,0x69,0xae]
+
+# CHECK: vqdmlah.s32 q0, q1, r11  @ encoding: [0x22,0xee,0x6b,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xee,0x6b,0x0e]
+
+# CHECK: vqdmlah.u8 q0, q2, lr  @ encoding: [0x04,0xfe,0x6e,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x04,0xfe,0x6e,0x0e]
+
+# CHECK: vqdmlah.u16 q0, q3, r10  @ encoding: [0x16,0xfe,0x6a,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xfe,0x6a,0x0e]
+
+# CHECK: vqdmlah.u32 q1, q5, r2  @ encoding: [0x2a,0xfe,0x62,0x2e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2a,0xfe,0x62,0x2e]
+
+# CHECK: vqrdmlash.s8 q0, q5, r10  @ encoding: [0x0a,0xee,0x4a,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0a,0xee,0x4a,0x1e]
+
+# CHECK: vqrdmlash.s16 q0, q3, r2  @ encoding: [0x16,0xee,0x42,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x16,0xee,0x42,0x1e]
+
+# CHECK: vqrdmlash.s32 q0, q0, r4  @ encoding: [0x20,0xee,0x44,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x20,0xee,0x44,0x1e]
+
+# CHECK: vqrdmlash.u8 q0, q4, r9  @ encoding: [0x08,0xfe,0x49,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xfe,0x49,0x1e]
+
+# CHECK: vqrdmlash.u16 q0, q6, r12  @ encoding: [0x1c,0xfe,0x4c,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1c,0xfe,0x4c,0x1e]
+
+# CHECK: vqrdmlash.u32 q0, q3, r7  @ encoding: [0x26,0xfe,0x47,0x1e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x26,0xfe,0x47,0x1e]
+
+# CHECK: vqrdmlah.s8 q0, q5, r11  @ encoding: [0x0a,0xee,0x4b,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0a,0xee,0x4b,0x0e]
+
+# CHECK: vqrdmlah.s16 q0, q2, r10  @ encoding: [0x14,0xee,0x4a,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x14,0xee,0x4a,0x0e]
+
+# CHECK: vqrdmlah.s32 q0, q4, r11  @ encoding: [0x28,0xee,0x4b,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xee,0x4b,0x0e]
+
+# CHECK: vqrdmlah.u8 q0, q4, r2  @ encoding: [0x08,0xfe,0x42,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x08,0xfe,0x42,0x0e]
+
+# CHECK: vqrdmlah.u16 q0, q6, r1  @ encoding: [0x1c,0xfe,0x41,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1c,0xfe,0x41,0x0e]
+
+# CHECK: vqrdmlah.u32 q0, q4, r2  @ encoding: [0x28,0xfe,0x42,0x0e]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x28,0xfe,0x42,0x0e]
+
+# CHECK: viwdup.u8 q0, lr, r1, #1  @ encoding: [0x0f,0xee,0x60,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0f,0xee,0x60,0x0f]
+
+# CHECK: viwdup.u16 q1, r10, r1, #8  @ encoding: [0x1b,0xee,0xe1,0x2f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1b,0xee,0xe1,0x2f]
+
+# CHECK: viwdup.u32 q6, r10, r5, #4  @ encoding: [0x2b,0xee,0xe4,0xcf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2b,0xee,0xe4,0xcf]
+
+# CHECK: vdwdup.u8 q0, r12, r11, #8  @ encoding: [0x0d,0xee,0xeb,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0d,0xee,0xeb,0x1f]
+
+# CHECK: vdwdup.u16 q0, r12, r1, #2  @ encoding: [0x1d,0xee,0x61,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1d,0xee,0x61,0x1f]
+
+# CHECK: vdwdup.u32 q0, r0, r7, #8  @ encoding: [0x21,0xee,0xe7,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x21,0xee,0xe7,0x1f]
+
+# CHECK: vidup.u8 q0, lr, #2  @ encoding: [0x0f,0xee,0x6f,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x0f,0xee,0x6f,0x0f]
+
+# CHECK: vidup.u16 q0, lr, #4  @ encoding: [0x1f,0xee,0xee,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1f,0xee,0xee,0x0f]
+
+# CHECK: vidup.u32 q0, r12, #1  @ encoding: [0x2d,0xee,0x6e,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x2d,0xee,0x6e,0x0f]
+
+# CHECK: vddup.u8 q0, r4, #4  @ encoding: [0x05,0xee,0xee,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x05,0xee,0xee,0x1f]
+
+# CHECK: vddup.u16 q0, r10, #4  @ encoding: [0x1b,0xee,0xee,0x1f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x1b,0xee,0xee,0x1f]
+
+# CHECK: vddup.u32 q2, r0, #8  @ encoding: [0x21,0xee,0xef,0x5f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x21,0xee,0xef,0x5f]
+
+# CHECK: vctp.8 lr  @ encoding: [0x0e,0xf0,0x01,0xe8]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0e,0xf0,0x01,0xe8]
+
+# CHECK: vctp.16 r0  @ encoding: [0x10,0xf0,0x01,0xe8]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x10,0xf0,0x01,0xe8]
+
+# CHECK: vctp.32 r10  @ encoding: [0x2a,0xf0,0x01,0xe8]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x2a,0xf0,0x01,0xe8]
+
+# CHECK: vctp.64 r1  @ encoding: [0x31,0xf0,0x01,0xe8]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x31,0xf0,0x01,0xe8]