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simon_tatham (Simon Tatham)
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User Since
Jul 12 2017, 1:23 AM (114 w, 1 d)

Recent Activity

Wed, Sep 11

simon_tatham created D67438: [InstCombine] Range metadata for ARM MVE VMIN/VMAX..
Wed, Sep 11, 5:01 AM · Restricted Project
simon_tatham updated the diff for D67160: [clang,ARM] Default to -fno-lax-vector-conversions in ARM v8.1-M..

Added a test.

Wed, Sep 11, 5:01 AM · Restricted Project
simon_tatham updated the diff for D67162: [InstCombine] Known-bits optimization for ARM MVE VADC..

Moved the vmin range metadata into a separate patch.

Wed, Sep 11, 5:01 AM · Restricted Project
simon_tatham added inline comments to D67162: [InstCombine] Known-bits optimization for ARM MVE VADC..
Wed, Sep 11, 5:01 AM · Restricted Project
simon_tatham updated the diff for D67161: [clang,ARM] Initial ACLE intrinsics for MVE..

Updated along with the patches it depends on. In particular, D67159 now needs a list of valid uses of the `__clang_arm_mve_alias`, so this patch now has to have an extra piece of Tablegen backend that generates that list.

Wed, Sep 11, 5:01 AM · Restricted Project
simon_tatham retitled D67159: [clang] New __attribute__((__clang_arm_mve_alias)). from [clang] New __attribute__((__clang_builtin)). to [clang] New __attribute__((__clang_arm_mve_alias))..
Wed, Sep 11, 5:01 AM · Restricted Project
simon_tatham updated the diff for D67159: [clang] New __attribute__((__clang_arm_mve_alias))..

New version which renames the attribute to be MVE-specific, and locks it down as requested.

Wed, Sep 11, 4:55 AM · Restricted Project
simon_tatham updated the diff for D67158: [ARM] Add IR intrinsics for a sample of MVE instructions..

Addressed many review comments.

Wed, Sep 11, 4:54 AM · Restricted Project
simon_tatham added inline comments to D67158: [ARM] Add IR intrinsics for a sample of MVE instructions..
Wed, Sep 11, 4:54 AM · Restricted Project

Mon, Sep 9

simon_tatham committed rG0e48bd24e212: [ARM] Remove some spurious MVE reduction instructions. (authored by simon_tatham).
[ARM] Remove some spurious MVE reduction instructions.
Mon, Sep 9, 8:18 AM
simon_tatham updated the summary of D67214: [ARM] Remove some spurious MVE reduction instructions..
Mon, Sep 9, 7:27 AM · Restricted Project
simon_tatham updated the diff for D67214: [ARM] Remove some spurious MVE reduction instructions..

Reworked the patch to reverse the multiclass nesting order, avoiding the need to fake a Tablegen if using foreach.

Mon, Sep 9, 7:27 AM · Restricted Project

Thu, Sep 5

simon_tatham added inline comments to D67162: [InstCombine] Known-bits optimization for ARM MVE VADC..
Thu, Sep 5, 9:04 AM · Restricted Project
simon_tatham added a comment to D67159: [clang] New __attribute__((__clang_arm_mve_alias))..

Come to think of it, it would also not be too hard to constrain it to only be usable for a particular subset of builtins, and perhaps even only with a particular set of alias names for them. (I could easily derive all that information from the same Tablegen that arm_mve.h itself is made from.)

Thu, Sep 5, 3:53 AM · Restricted Project
simon_tatham added a comment to D67159: [clang] New __attribute__((__clang_arm_mve_alias))..

On the general discomfort with this attribute existing: I'd be happy to lock it down, or mark it as "not recommended" in some way, if that's any help. I don't personally intend any use of it outside a single system header file (namely arm_mve.h, which D67161 will introduce the initial version of).

Thu, Sep 5, 3:41 AM · Restricted Project
simon_tatham created D67214: [ARM] Remove some spurious MVE reduction instructions..
Thu, Sep 5, 1:28 AM · Restricted Project

Wed, Sep 4

simon_tatham added a comment to D67159: [clang] New __attribute__((__clang_arm_mve_alias))..

Sorry about that – I didn't want to put the discussion of rationale in too many different places. The commit message for the followup patch D67161 discusses it a bit.

Wed, Sep 4, 6:15 AM · Restricted Project
simon_tatham created D67162: [InstCombine] Known-bits optimization for ARM MVE VADC..
Wed, Sep 4, 5:50 AM · Restricted Project
simon_tatham created D67161: [clang,ARM] Initial ACLE intrinsics for MVE..
Wed, Sep 4, 5:48 AM · Restricted Project
simon_tatham created D67160: [clang,ARM] Default to -fno-lax-vector-conversions in ARM v8.1-M..
Wed, Sep 4, 5:48 AM · Restricted Project
simon_tatham created D67159: [clang] New __attribute__((__clang_arm_mve_alias))..
Wed, Sep 4, 5:48 AM · Restricted Project
simon_tatham created D67158: [ARM] Add IR intrinsics for a sample of MVE instructions..
Wed, Sep 4, 5:47 AM · Restricted Project

Aug 8 2019

simon_tatham added a comment to D65884: [ARM] MVE Tail Predication.

Sam's suggestion to me for the ACLE intrinsics was that there should be an IR intrinsic that converts the i16 provided by the user into an <n x i1> for whatever n makes sense. In my unpushed (and unpolished) draft implementation there's also one that converts back again, which the ACLE intrinsics will need for the return value of vcmp. So it could be used here as well if that's useful.

Aug 8 2019, 7:23 AM · Restricted Project
simon_tatham added a comment to D65929: [ARM] Make v2i1 a valid type for the MVE predicate register..

Hmm. I may have underestimated the difficulty, then! My thought was that all I really needed was to arrange that if you already had a v2i1, you could use it as the predicate operand for one of the 64-bit-lane instructions and not have instruction selection fail, and perhaps if you already had a pair of them you could do bitwise ops between them just like you can with all the others.

Aug 8 2019, 3:20 AM · Restricted Project
simon_tatham added inline comments to D65583: [ARM] MVE big endian loads/stores.
Aug 8 2019, 2:25 AM · Restricted Project
simon_tatham created D65929: [ARM] Make v2i1 a valid type for the MVE predicate register..
Aug 8 2019, 2:24 AM · Restricted Project
simon_tatham added inline comments to D65583: [ARM] MVE big endian loads/stores.
Aug 8 2019, 1:28 AM · Restricted Project

Aug 7 2019

simon_tatham added inline comments to D65580: [ARM] Tighten up VLDRH.32 with low alignments.
Aug 7 2019, 2:08 AM · Restricted Project

Jul 23 2019

simon_tatham accepted D65133: [ARM] MVE VPNOT.
Jul 23 2019, 1:18 AM · Restricted Project

Jul 19 2019

simon_tatham accepted D64810: [ARM] Add <saturate> operand to SQRSHRL and UQRSHLL.
Jul 19 2019, 2:41 AM · Restricted Project
simon_tatham added inline comments to D64810: [ARM] Add <saturate> operand to SQRSHRL and UQRSHLL.
Jul 19 2019, 1:27 AM · Restricted Project

Jul 17 2019

simon_tatham added a comment to D63863: [ARM] Make coprocessor number restrictions consistent..

So it sounds as if the most immediate problem is that there now _isn't_ an architecture you can specify on clang's command line that permits the union of all the instructions you plan to use?

Jul 17 2019, 2:10 AM · Restricted Project
simon_tatham added a comment to D63863: [ARM] Make coprocessor number restrictions consistent..

Hmmm. This surely can't be the first time a case like this has come up. What's the usual solution in other similar situations, when you want to include code for mutually incompatible architectures in the same object because you're going to test at run time which one to execute?

Jul 17 2019, 12:56 AM · Restricted Project

Jul 11 2019

simon_tatham committed rG7916198a4105: [ARM] Remove nonexistent unsigned forms of MVE VQDMLAH. (authored by simon_tatham).
[ARM] Remove nonexistent unsigned forms of MVE VQDMLAH.
Jul 11 2019, 2:53 AM

Jul 10 2019

simon_tatham created D64502: [ARM] Remove nonexistent unsigned forms of MVE VQDMLAH..
Jul 10 2019, 8:19 AM · Restricted Project

Jul 8 2019

simon_tatham accepted D64250: [ARM] Relax constraints on operands of VQxDMLxDH instructions.
Jul 8 2019, 1:03 AM · Restricted Project

Jul 4 2019

simon_tatham committed rGc74322a11bcc: [TableGen] Allow DAG isel patterns to override default operands. (authored by simon_tatham).
[TableGen] Allow DAG isel patterns to override default operands.
Jul 4 2019, 1:44 AM

Jul 2 2019

simon_tatham committed rGbffd099d1582: [ARM] MVE: allow soft-float ABI to pass vector types. (authored by simon_tatham).
[ARM] MVE: allow soft-float ABI to pass vector types.
Jul 2 2019, 4:27 AM
simon_tatham added inline comments to D63937: [ARM] MVE: allow soft-float ABI to pass vector types..
Jul 2 2019, 4:27 AM · Restricted Project
simon_tatham committed rG7b63a9533c7e: [ARM] Stop using scalar FP instructions in integer-only MVE mode. (authored by simon_tatham).
[ARM] Stop using scalar FP instructions in integer-only MVE mode.
Jul 2 2019, 4:27 AM
simon_tatham accepted D64044: [clang][Driver][ARM] NFC: Remove unused function parameter.
Jul 2 2019, 1:55 AM · Restricted Project, Restricted Project

Jul 1 2019

simon_tatham updated the diff for D63937: [ARM] MVE: allow soft-float ABI to pass vector types..

Revised patch is intended to apply after D63938 rather than before.

Jul 1 2019, 9:54 AM · Restricted Project
simon_tatham updated the diff for D63938: [ARM] Stop using scalar FP instructions in integer-only MVE mode..

Revised patch fixes those two target triples in the tests, and makes the setAllExpand calls for f32 and f64 conditional on different things. Also, to make that less cumbersome, I've moved a few re-enabling setOperationAction calls into setAllExpand itself which otherwise had to be run after every single call.

Jul 1 2019, 9:49 AM · Restricted Project
simon_tatham added inline comments to D63938: [ARM] Stop using scalar FP instructions in integer-only MVE mode..
Jul 1 2019, 9:31 AM · Restricted Project
simon_tatham added a comment to D63936: [clang][Driver][ARM] Favor -mfpu over default CPU features.

I can't shed as much light as you might hope, I'm afraid, but in D62998 my intention was not to make -mcpu=anything win over -mfpu=anything. It was to make an explicit request to enable a feature win over an implicit request to disable it. It so happened in my example that the explicit request was in the -mcpu option.

Jul 1 2019, 9:26 AM · Restricted Project, Restricted Project
simon_tatham accepted D64009: [ARM] MVE: support QQPRRegClass and QQQQPRRegClass.

Otherwise LGTM.

Jul 1 2019, 8:56 AM · Restricted Project
simon_tatham accepted D64007: [ARM] Fix MVE_VQxDMLxDH instruction class.
Jul 1 2019, 8:54 AM · Restricted Project
simon_tatham updated the summary of D63814: [TableGen] Allow DAG isel patterns to override default operands..
Jul 1 2019, 7:45 AM · Restricted Project
simon_tatham updated the diff for D63814: [TableGen] Allow DAG isel patterns to override default operands..

Apparently it would: trying it that way, it does look simpler, and as far as I can tell it doesn't change the output of any currently checked-in Tablegen input.

Jul 1 2019, 7:45 AM · Restricted Project
simon_tatham added inline comments to D63937: [ARM] MVE: allow soft-float ABI to pass vector types..
Jul 1 2019, 5:33 AM · Restricted Project

Jun 28 2019

simon_tatham created D63937: [ARM] MVE: allow soft-float ABI to pass vector types..
Jun 28 2019, 9:38 AM · Restricted Project
simon_tatham created D63938: [ARM] Stop using scalar FP instructions in integer-only MVE mode..
Jun 28 2019, 9:38 AM · Restricted Project
simon_tatham added a comment to D62680: [ARM] Add MVE vector load/store instructions..

Sorry about that. rL364635 should fix it.

Jun 28 2019, 2:32 AM · Restricted Project
simon_tatham committed rG29ff1b4f4653: [ARM] Fix integer UB in MVE load/store immediate handling. (authored by simon_tatham).
[ARM] Fix integer UB in MVE load/store immediate handling.
Jun 28 2019, 2:31 AM

Jun 27 2019

simon_tatham updated the summary of D63814: [TableGen] Allow DAG isel patterns to override default operands..
Jun 27 2019, 6:27 AM · Restricted Project
simon_tatham updated the diff for D63814: [TableGen] Allow DAG isel patterns to override default operands..

Changed my mind about the opt-in system: instead of using a subclass of OperandWithDefaultOps, I've switched to using a flag field inside the existing class.

Jun 27 2019, 6:15 AM · Restricted Project
simon_tatham committed rG1a3dc8f67849: [ARM] Fix bogus assertions in copyPhysReg v8.1-M cases. (authored by simon_tatham).
[ARM] Fix bogus assertions in copyPhysReg v8.1-M cases.
Jun 27 2019, 5:45 AM
simon_tatham committed rGffb2b347ffbd: [ARM] Fix handling of zero offsets in LOB instructions. (authored by simon_tatham).
[ARM] Fix handling of zero offsets in LOB instructions.
Jun 27 2019, 5:45 AM
simon_tatham committed rGe5ce56fb950b: [ARM] Make coprocessor number restrictions consistent. (authored by simon_tatham).
[ARM] Make coprocessor number restrictions consistent.
Jun 27 2019, 5:44 AM
simon_tatham committed rG02449f9c3cf5: [ARM] Tighten restrictions on use of SP in v8.1-M CSEL. (authored by simon_tatham).
[ARM] Tighten restrictions on use of SP in v8.1-M CSEL.
Jun 27 2019, 5:44 AM
simon_tatham added inline comments to D63862: [ARM] Tighten restrictions on use of SP in v8.1-M CSEL..
Jun 27 2019, 4:58 AM · Restricted Project
simon_tatham created D63865: [ARM] Fix bogus assertions in copyPhysReg v8.1-M cases..
Jun 27 2019, 2:50 AM · Restricted Project
simon_tatham created D63863: [ARM] Make coprocessor number restrictions consistent..
Jun 27 2019, 2:50 AM · Restricted Project
simon_tatham created D63864: [ARM] Fix handling of zero offsets in LOB instructions..
Jun 27 2019, 2:50 AM · Restricted Project
simon_tatham created D63862: [ARM] Tighten restrictions on use of SP in v8.1-M CSEL..
Jun 27 2019, 2:49 AM · Restricted Project

Jun 26 2019

simon_tatham created D63814: [TableGen] Allow DAG isel patterns to override default operands..
Jun 26 2019, 5:23 AM · Restricted Project
simon_tatham added inline comments to D60709: [ARM] Support inline assembler constraints for MVE..
Jun 26 2019, 1:31 AM · Restricted Project, Restricted Project

Jun 25 2019

simon_tatham committed rGe8de8ba6a637: [ARM] Support inline assembler constraints for MVE. (authored by simon_tatham).
[ARM] Support inline assembler constraints for MVE.
Jun 25 2019, 9:51 AM
simon_tatham committed rGa4b415a6839b: [ARM] Code-generation infrastructure for MVE. (authored by simon_tatham).
[ARM] Code-generation infrastructure for MVE.
Jun 25 2019, 9:50 AM
simon_tatham updated the summary of D60708: [ARM] Code-generation infrastructure for MVE..
Jun 25 2019, 8:11 AM · Restricted Project
simon_tatham updated the diff for D60709: [ARM] Support inline assembler constraints for MVE..

Rebased this patch to current trunk, and also fixed a test failure by adding arm_aapcs_vfpcc to the test functions that use MVE vector types (since we can't support passing vector types in GPRs until we get all the operations like build_vector and insert_element fully supported).

Jun 25 2019, 8:11 AM · Restricted Project, Restricted Project
simon_tatham updated the diff for D60708: [ARM] Code-generation infrastructure for MVE..

Revised this patch to work properly with all the other MVE-related changes we've been making.

Jun 25 2019, 8:11 AM · Restricted Project
simon_tatham committed rGec18f0f64c54: [ARM] Re-enable misspelled RUN: lines in fullfp16.s. (authored by simon_tatham).
[ARM] Re-enable misspelled RUN: lines in fullfp16.s.
Jun 25 2019, 6:20 AM
simon_tatham committed rG287f0403e310: [ARM] Fix buildbot failure due to -Werror. (authored by simon_tatham).
[ARM] Fix buildbot failure due to -Werror.
Jun 25 2019, 5:26 AM
simon_tatham committed rGd9654723ad85: [ARM] Extra MVE-related testing. (authored by simon_tatham).
[ARM] Extra MVE-related testing.
Jun 25 2019, 4:31 AM
simon_tatham committed rG4cf18c284955: [ARM] Explicit lowering of half <-> double conversions. (authored by simon_tatham).
[ARM] Explicit lowering of half <-> double conversions.
Jun 25 2019, 4:31 AM
simon_tatham committed rG86b7a1e660b5: [ARM] Add remaining miscellaneous MVE instructions. (authored by simon_tatham).
[ARM] Add remaining miscellaneous MVE instructions.
Jun 25 2019, 4:26 AM
simon_tatham committed rGe6824160dd6f: [ARM] Add MVE vector load/store instructions. (authored by simon_tatham).
[ARM] Add MVE vector load/store instructions.
Jun 25 2019, 4:25 AM
simon_tatham updated the diff for D62681: [ARM] Add remaining miscellaneous MVE instructions..

Addressed all review comments.

Jun 25 2019, 2:28 AM · Restricted Project
simon_tatham added inline comments to D62681: [ARM] Add remaining miscellaneous MVE instructions..
Jun 25 2019, 2:27 AM · Restricted Project
simon_tatham updated the diff for D62680: [ARM] Add MVE vector load/store instructions..

Addressed all review comments, I think.

Jun 25 2019, 1:51 AM · Restricted Project
simon_tatham added inline comments to D62680: [ARM] Add MVE vector load/store instructions..
Jun 25 2019, 1:51 AM · Restricted Project

Jun 24 2019

simon_tatham closed D63650: [ARM] Add MVE interleaving load/store family..

I committed this this morning as rL364172, but accidentally left off the Phabricator footer (sorry). Now closing.

Jun 24 2019, 9:10 AM · Restricted Project
simon_tatham updated the diff for D62680: [ARM] Add MVE vector load/store instructions..

Minor revisions to this patch: changed a couple of legacy t2rGPR into rGPR (after the former was withdrawn during code review of D63650). Also added a small knock-on fix in checkTargetMatchPredicate, preventing an assertion failure in a check that was specific to rGPR.

Jun 24 2019, 9:08 AM · Restricted Project
simon_tatham added an edge to rGfe8017621ea5: [ARM] Add MVE interleaving load/store family.: D63650: [ARM] Add MVE interleaving load/store family..
Jun 24 2019, 9:08 AM
simon_tatham added 1 commit(s) for D63650: [ARM] Add MVE interleaving load/store family.: rGfe8017621ea5: [ARM] Add MVE interleaving load/store family..
Jun 24 2019, 9:08 AM · Restricted Project
simon_tatham updated the diff for D62680: [ARM] Add MVE vector load/store instructions..

Reworked the remaining loads and stores to address review comments, implement consistent naming of instruction ids, and tidy up the Tablegen so that it's hopefully halfway readable.

Jun 24 2019, 5:56 AM · Restricted Project
simon_tatham updated the diff for D62681: [ARM] Add remaining miscellaneous MVE instructions..

Updated instruction spellings in line with intended consistent MVE practice, and also reworked the WLSTP/DLSTP and LETP/LCTP definitions to remove pointless !if from the base classes. (In particular, the instructions that don't have a label field in the encoding now don't have one in their Tablegen defs either.)

Jun 24 2019, 4:04 AM · Restricted Project
simon_tatham committed rGfe8017621ea5: [ARM] Add MVE interleaving load/store family. (authored by simon_tatham).
[ARM] Add MVE interleaving load/store family.
Jun 24 2019, 3:04 AM

Jun 21 2019

simon_tatham updated the diff for D63650: [ARM] Add MVE interleaving load/store family..

Addressed all review comments.

Jun 21 2019, 9:00 AM · Restricted Project
simon_tatham added inline comments to D63650: [ARM] Add MVE interleaving load/store family..
Jun 21 2019, 9:00 AM · Restricted Project
simon_tatham added a comment to D62680: [ARM] Add MVE vector load/store instructions..

I've decided this patch is too large to manage all in one go. Also, the interleaving family of loads (VLD20 and friends) share essentially no infrastructure with the VLDR family, so that seems like a natural place to split the patch in two.

Jun 21 2019, 7:30 AM · Restricted Project
simon_tatham created D63650: [ARM] Add MVE interleaving load/store family..
Jun 21 2019, 7:29 AM · Restricted Project
simon_tatham committed rG0c7af66450ba: [ARM] Add MVE 64-bit GPR <-> vector move instructions. (authored by simon_tatham).
[ARM] Add MVE 64-bit GPR <-> vector move instructions.
Jun 21 2019, 6:18 AM
simon_tatham committed rGbafb105e9697: [ARM] Add MVE vector instructions that take a scalar input. (authored by simon_tatham).
[ARM] Add MVE vector instructions that take a scalar input.
Jun 21 2019, 6:18 AM
simon_tatham closed D62679: [ARM] Add MVE 64-bit GPR <-> vector move instructions..
Jun 21 2019, 6:18 AM · Restricted Project
simon_tatham closed D62678: [ARM] Add MVE vector instructions that take a scalar input..
Jun 21 2019, 6:18 AM · Restricted Project
simon_tatham updated the diff for D62678: [ARM] Add MVE vector instructions that take a scalar input..

Revised the VIDUP immediate operand handling so as to draw a distinction between the general concept 'power of 2 which is encoded as a left-shift count in the instruction', and the specific case used in VIDUP which takes a fixed range of inputs and has a custom DiagnosticString as you suggested that explains what it's used for.

Jun 21 2019, 5:35 AM · Restricted Project
simon_tatham committed rGa6b6a15701c8: [ARM] Add a batch of similarly encoded MVE instructions. (authored by simon_tatham).
[ARM] Add a batch of similarly encoded MVE instructions.
Jun 21 2019, 5:14 AM
simon_tatham updated the diff for D62677: [ARM] Add a batch of similarly encoded MVE instructions..

Addressed review comment about Mnemonic.startswith("vmul"), and also updated this patch to use the existing NEON complex rotation operands (with matching change in the test to expect the new nicer error messages).

Jun 21 2019, 4:43 AM · Restricted Project