[RISCV][SelectionDAG] Lower shuffles as bitrotates with vror.vi when possible

[luke]

Summary

Given a shuffle mask like <3, 0, 1, 2, 7, 4, 5, 6> for v8i8, we can
reinterpret it as a shuffle of v2i32 where the two i32s are bit rotated, and
lower it as a vror.vi (if legal with zvbb enabled).
We also need to make sure that the larger element type is a valid SEW, hence
the tests for zve32x.

X86 already did this, so I've extracted the logic for it and put it inside
ShuffleVectorSDNode so it could be reused by RISC-V. I originally tried to add
this as a generic combine in DAGCombiner.cpp, but it ended up causing worse
codegen on X86 and PPC.

[luke]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4141–4147

As an example, If the rotateAmt is 24 then on RV32 the constant comes out as:

t3:v1i64 = bitcast t4
t4:v2i32 = build_vector <i32 24, i32 0>

I tried handling this case in lowerBuildVectorOfConstants to lower it as a v1i64 vmv_v_x_vl, with the constant reinterpreted across the elements, but it doesn't seem to catch any other cases since this pattern doesn't seem to be generated anywhere else.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

4147

So directly lower it to a vmv.v.x gets picked up and matched to a vror.vi.

I think there's some words missing from that sentence.

[luke]

Fix typo in comments
Also move logic from ShuffleVectorSDNode to ShuffleVectorInst in
Instruction.h. The old signature returned an EVT since nothing else in
SelectionDAGNodes.h seemed to return an MVT, but we still had to pass
through an MVT which seemed hairy. So I've shuffled it about to just
operate on the mask array and placed it amongst the other mask helpers,
even though it isn't necessarily used by the middle-end. But I think that
should be OK, since the helpers in ShuffleVectorInst are used by both the
middle-end and the backend.

[luke]

Fix X86 build

[reames]

This might be an over generalization, but I can't help but notice that we don't need the same rotate amount in each chunk. Given the small number of possible rotate amounts, I wonder if we'd be worth generating a rotate by a build_vector. This might be overly general.

When looking at your tests, I noticed a bunch which should probably be vrev8.v instead. Might be worth implementing that, then rebasing this over. I'd be fine with the other order too, so don't take that as must.

Broader point is that maybe we should be doing this even without zbb.

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll

192

This case is interesting a couple different ways.

First, the vror here is also a vrev8.v. This points out that we probably should be matching brev8.v. Minor, but we should probably also be preferring it here when both are possible.

Second, the bswap lowering for 2 element pairs is going to be cheaper than the vrgather even without zvbb. We probably should be matching high/low swapping on all element sizes up to XLEN.

240

Continuing from the prior comment..

Since this isn't an arbitrary byte shuffle within each element, but instead two contiguous regions, I think using the rotate expansion even for no-zbb is going to be profitable.

[luke]

In D157417#4593411, @reames wrote:

Broader point is that maybe we should be doing this even without zbb.

For reference, this is the new sequence we would be generating without zvbb:

 define <8 x i16> @shuffle_v8i16_as_i32(<8 x i16> %v) {
 ; CHECK-LABEL: shuffle_v8i16_as_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lui a0, %hi(.LCPI18_0)
-; CHECK-NEXT:    addi a0, a0, %lo(.LCPI18_0)
-; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT:    vle16.v v10, (a0)
-; CHECK-NEXT:    vrgather.vv v9, v8, v10
-; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.i v9, 0
+; CHECK-NEXT:    li a0, 16
+; CHECK-NEXT:    vwsubu.vx v10, v9, a0
+; CHECK-NEXT:    li a1, 31
+; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT:    vand.vx v9, v10, a1
+; CHECK-NEXT:    vsrl.vv v9, v8, v9
+; CHECK-NEXT:    vmv.v.x v10, a0
+; CHECK-NEXT:    vand.vx v10, v10, a1
+; CHECK-NEXT:    vsll.vv v8, v8, v10
+; CHECK-NEXT:    vor.vv v8, v8, v9
 ; CHECK-NEXT:    ret
 ;
 ; ZVBB_V-LABEL: shuffle_v8i16_as_i32:
 ; ZVBB_V:       # %bb.0:
 ; ZVBB_V-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
 ; ZVBB_V-NEXT:    vror.vi v8, v8, 16
 ; ZVBB_V-NEXT:    ret
 ;
 ; ZVBB_ZVE32X-LABEL: shuffle_v8i16_as_i32:
 ; ZVBB_ZVE32X:       # %bb.0:
 ; ZVBB_ZVE32X-NEXT:    vsetivli zero, 4, e32, m4, ta, ma
 ; ZVBB_ZVE32X-NEXT:    vror.vi v8, v8, 16
 ; ZVBB_ZVE32X-NEXT:    ret
   %shuffle = shufflevector <8 x i16> %v, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
   ret <8 x i16> %shuffle
 }

[craig.topper]

In D157417#4595013, @luke wrote:

In D157417#4593411, @reames wrote:

Broader point is that maybe we should be doing this even without zbb.

For reference, this is the new sequence we would be generating without zvbb:

 define <8 x i16> @shuffle_v8i16_as_i32(<8 x i16> %v) {
 ; CHECK-LABEL: shuffle_v8i16_as_i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lui a0, %hi(.LCPI18_0)
-; CHECK-NEXT:    addi a0, a0, %lo(.LCPI18_0)
-; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT:    vle16.v v10, (a0)
-; CHECK-NEXT:    vrgather.vv v9, v8, v10
-; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.i v9, 0
+; CHECK-NEXT:    li a0, 16
+; CHECK-NEXT:    vwsubu.vx v10, v9, a0
+; CHECK-NEXT:    li a1, 31
+; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT:    vand.vx v9, v10, a1
+; CHECK-NEXT:    vsrl.vv v9, v8, v9
+; CHECK-NEXT:    vmv.v.x v10, a0
+; CHECK-NEXT:    vand.vx v10, v10, a1
+; CHECK-NEXT:    vsll.vv v8, v8, v10
+; CHECK-NEXT:    vor.vv v8, v8, v9
 ; CHECK-NEXT:    ret
 ;
 ; ZVBB_V-LABEL: shuffle_v8i16_as_i32:
 ; ZVBB_V:       # %bb.0:
 ; ZVBB_V-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
 ; ZVBB_V-NEXT:    vror.vi v8, v8, 16
 ; ZVBB_V-NEXT:    ret
 ;
 ; ZVBB_ZVE32X-LABEL: shuffle_v8i16_as_i32:
 ; ZVBB_ZVE32X:       # %bb.0:
 ; ZVBB_ZVE32X-NEXT:    vsetivli zero, 4, e32, m4, ta, ma
 ; ZVBB_ZVE32X-NEXT:    vror.vi v8, v8, 16
 ; ZVBB_ZVE32X-NEXT:    ret
   %shuffle = shufflevector <8 x i16> %v, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
   ret <8 x i16> %shuffle
 }

Why isn't this constant folded

+; CHECK-NEXT:    vmv.v.i v9, 0
+; CHECK-NEXT:    li a0, 16
+; CHECK-NEXT:    vwsubu.vx v10, v9, a0

This and feels unnecessary. This shift only uses the lower 5 bits

+; CHECK-NEXT:    li a1, 31
+; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT:    vand.vx v9, v10, a1
+; CHECK-NEXT:    vsrl.vv v9, v8, v9

[luke]

Fix extra multiplication on x86, and fix test diffs that didn't get included

[luke]

In D157417#4596043, @craig.topper wrote:

Why isn't this constant folded

+; CHECK-NEXT:    vmv.v.i v9, 0
+; CHECK-NEXT:    li a0, 16
+; CHECK-NEXT:    vwsubu.vx v10, v9, a0

This and feels unnecessary. This shift only uses the lower 5 bits

+; CHECK-NEXT:    li a1, 31
+; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-NEXT:    vand.vx v9, v10, a1
+; CHECK-NEXT:    vsrl.vv v9, v8, v9

I put both sequences through llvm-mca, and on the sifive-x280 model it seems like the rotate sequence has better throughput.

rotate-mca-output.txt4 KBDownload

But if there's still some codegen issues to be addressed, should we defer handling non-zvbb archs to a later patch?

[reames]

In D157417#4602937, @luke wrote:

But if there's still some codegen issues to be addressed, should we defer handling non-zvbb archs to a later patch?

I'm fine with staging in this way. I mostly brought it up because it might result in a different code structure.

LGTM

Follow ups worth exploring:

• Can we use slide lowering when no-zbb?
• Can we handle vector.reverse via tree of rotates? Either only with zbb, or always? (Edit: This only covers very short fixed vectors and probably isn't that interesting.)
• Is matching a rotate with a non-splat rotate amount interesting? This feels like maybe the start of a more general "handle nearby parts" shuffle lowering strategy, and is maybe worth some offline discussion.

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll

192 ↗

(On Diff #551493)

As a follow up, it's worth noting this can be done as two rotates. One at 32 SEW by 16, and one at SEW by 8. The later is a brev8.

[Jim]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll

5

In testcases for RISC-V, I always saw that use '-' not '_' underline in check-prefixes.

[luke]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll

5

Good catch, will fix!

[luke]

Adding a few more X86 people, hope you're ok with me stealing your code :)

[luke]

Rename filecheck prefixes

[reames]

Just to be explicit - my LGTM still stands here.

[luke]

In D157417#4626029, @reames wrote:

Just to be explicit - my LGTM still stands here.

Thanks. Is it worthwhile waiting to see if any of the x86 people are ok with the refactoring?

[pengfei]

LGTM.

llvm/include/llvm/CodeGen/SelectionDAGNodes.h

for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i)
       if (Mask[i] >= 0)
         return Mask[i];
 
     // We can choose any index value here and be correct because all elements
     // are undefined. Return 0 for better potential for callers to simplify.
     return 0;
   }
 
+  /// Checks if the shuffle is a rotation of the first operand, e.g:
+  ///
+  /// shuffle %a:v8i8, %b:v8i8, <1, 0, 3, 2, 5, 4, 7, 6>
+  ///
+  /// could be expressed as
+  ///
+  /// rotl (bitcast %a):v4i16, 8
+  ///
+  /// If it can be expressed as a rotation, returns the type that should be used
+  /// for the rotation and the number of bits to rotate by.
+  std::optional<std::pair<EVT, unsigned>> isBitRotate() {
+    EVT VT = getValueType(0);
+    ArrayRef<int> Mask = getMask();
+    return isBitRotate(VT.getScalarSizeInBits(), Mask, 2, Mask.size());
+  }
+
+  static std::optional<std::pair<EVT, unsigned>> isBitRotate(int EltSizeInBits,
+                                                             ArrayRef<int> Mask,
+                                                             int MinSubElts,
+                                                             int MaxSubElts);
+
   static bool isSplatMask(const int *Mask, EVT VT);
 
   /// Change values in a shuffle permute mask assuming
   /// the two vector operands have swapped position.
   static void commuteMask(MutableArrayRef<int> Mask) {
     unsigned NumElems = Mask.size();
     for (unsigned i = 0; i != NumElems; ++i) {
       int idx = Mask[i];

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

for (unsigned i = 2; i < NumOps; ++i) {
     APInt Val = getConstantOperandAPInt(i).trunc(EltSize);
     if (Val != (Start + (Stride * i)))
       return std::nullopt;
   }
 
   return std::make_pair(Start, Stride);
 }
 
+/// Try to lower a vector shuffle as a bit rotation.
+///
+/// Look for a repeated rotation pattern in each sub group.
+/// Returns a ISD::ROTL element rotation amount or -1 if failed.
+static int matchShuffleAsBitRotate(ArrayRef<int> Mask, int NumSubElts) {
+  int NumElts = Mask.size();
+  assert((NumElts % NumSubElts) == 0 && "Illegal shuffle mask");
+
+  int RotateAmt = -1;
+  for (int i = 0; i != NumElts; i += NumSubElts) {
+    for (int j = 0; j != NumSubElts; ++j) {
+      int M = Mask[i + j];
+      if (M < 0)
+        continue;
+      if (M < i || M >= i + NumSubElts)
+        return -1;
+      int Offset = (NumSubElts - (M - (i + j))) % NumSubElts;
+      if (0 <= RotateAmt && Offset != RotateAmt)
+        return -1;
+      RotateAmt = Offset;
+    }
+  }
+  return RotateAmt;
+}
+
+std::optional<std::pair<EVT, unsigned>>
+ShuffleVectorSDNode::isBitRotate(int EltSizeInBits, ArrayRef<int> Mask,
+                                 int MinSubElts, int MaxSubElts) {
+  int NumElts = Mask.size();
+  for (int NumSubElts = MinSubElts; NumSubElts <= MaxSubElts; NumSubElts *= 2) {
+    int RotateAmt = matchShuffleAsBitRotate(Mask, NumSubElts);
+    if (RotateAmt < 0)
+      continue;
+
+    MVT RotateSVT = MVT::getIntegerVT(EltSizeInBits * NumSubElts);
+    MVT RotateVT = MVT::getVectorVT(RotateSVT, NumElts / NumSubElts);
+    return std::make_pair(RotateVT, RotateAmt * EltSizeInBits);
+  }
+
+  return std::nullopt;
+}
+
 bool ShuffleVectorSDNode::isSplatMask(const int *Mask, EVT VT) {
   // Find the first non-undef value in the shuffle mask.
   unsigned i, e;
   for (i = 0, e = VT.getVectorNumElements(); i != e && Mask[i] < 0; ++i)
     /* search */;
 
   // If all elements are undefined, this shuffle can be considered a splat
   // (although it should eventually get simplified away completely).

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

MVT ResultVT =
                        VecVT.getVectorElementCount().multiplyCoefficientBy(2));
   if (ResultVT.isFixedLengthVector())
     Interleaved =
         convertFromScalableVector(ResultVT, Interleaved, DAG, Subtarget);
 
   return Interleaved;
 }
 
+// Given a shuffle mask like <3, 0, 1, 2, 7, 4, 5, 6> for v8i8, we can
+// reinterpret it as a shuffle of v2i32 where the two i32s are bit rotated, and
+// lower it as a vror.vi (if legal with zvbb enabled).
+static SDValue lowerVECTOR_SHUFFLEAsRotate(ShuffleVectorSDNode *SVN,
+                                           SelectionDAG &DAG,
+                                           const RISCVSubtarget &Subtarget) {
+  SDLoc DL(SVN);
+
+  EVT VT = SVN->getValueType(0);
+  auto MaybeRotate = SVN->isBitRotate();
+  if (!MaybeRotate)
+    return SDValue();
+  auto [RotateEVT, RotateAmt] = *MaybeRotate;
+  MVT RotateVT = RotateEVT.getSimpleVT();
+
+  // We might have a RotateVT that isn't legal, e.g. v4i64 on zve32x.
+  if (!Subtarget.getTargetLowering()->isOperationLegalOrCustom(ISD::ROTL,
+                                                               RotateVT))
+    return SDValue();
+
+  // If we just create the shift amount with
+  //
+  // DAG.getConstant(RotateAmt, DL, RotateVT)
+  //
+  // then for e64 we get a weird bitcasted build_vector on RV32 that we're
+  // unable to detect as a splat during pattern matching. So directly lower it
+  // to a vmv.v.x gets picked up and matched to a vror.vi.
+  MVT ContainerVT = getContainerForFixedLengthVector(DAG, RotateVT, Subtarget);
+  SDValue VL =
+      getDefaultVLOps(RotateVT, ContainerVT, DL, DAG, Subtarget).second;
+  SDValue RotateAmtSplat = DAG.getNode(
+      RISCVISD::VMV_V_X_VL, DL, ContainerVT, DAG.getUNDEF(ContainerVT),
+      DAG.getConstant(RotateAmt, DL, Subtarget.getXLenVT()), VL);
+  RotateAmtSplat =
+      convertFromScalableVector(RotateVT, RotateAmtSplat, DAG, Subtarget);
+
+  SDValue Rotate =
+      DAG.getNode(ISD::ROTL, DL, RotateVT,
+                  DAG.getBitcast(RotateVT, SVN->getOperand(0)), RotateAmtSplat);
+  return DAG.getBitcast(VT, Rotate);
+}
+
 static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
                                    const RISCVSubtarget &Subtarget) {
   SDValue V1 = Op.getOperand(0);
   SDValue V2 = Op.getOperand(1);
   SDLoc DL(Op);
   MVT XLenVT = Subtarget.getXLenVT();
   MVT VT = Op.getSimpleValueType();
   unsigned NumElts = VT.getVectorNumElements();
   ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
 
+  // Lower groups of rotations to element-wise rotations. Do this before we
+  // promote i1s to i8s.
+  if (SDValue V = lowerVECTOR_SHUFFLEAsRotate(SVN, DAG, Subtarget))
+    return V;
+
   // Promote i1 shuffle to i8 shuffle.
   if (VT.getVectorElementType() == MVT::i1) {
     MVT WidenVT = MVT::getVectorVT(MVT::i8, VT.getVectorElementCount());
     V1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenVT, V1);
     V2 = V2.isUndef() ? DAG.getUNDEF(WidenVT)
                       : DAG.getNode(ISD::ZERO_EXTEND, DL, WidenVT, V2);
     SDValue Shuffled = DAG.getVectorShuffle(WidenVT, DL, V1, V2, SVN->getMask());
     return DAG.getSetCC(DL, VT, Shuffled, DAG.getConstant(0, DL, WidenVT),

llvm/lib/Target/X86/X86ISelLowering.cpp

for (int i = 0; i != NumElts; i += NumEltsPerLane)
       }
   }
 
   V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), V1Mask);
   V2 = DAG.getVectorShuffle(VT, DL, V2, DAG.getUNDEF(VT), V2Mask);
   return DAG.getVectorShuffle(VT, DL, V1, V2, FinalMask);
 }
 
-/// Try to lower a vector shuffle as a bit rotation.
-///
-/// Look for a repeated rotation pattern in each sub group.
-/// Returns a ISD::ROTL element rotation amount or -1 if failed.
-static int matchShuffleAsBitRotate(ArrayRef<int> Mask, int NumSubElts) {
-  int NumElts = Mask.size();
-  assert((NumElts % NumSubElts) == 0 && "Illegal shuffle mask");
-
-  int RotateAmt = -1;
-  for (int i = 0; i != NumElts; i += NumSubElts) {
-    for (int j = 0; j != NumSubElts; ++j) {
-      int M = Mask[i + j];
-      if (M < 0)
-        continue;
-      if (!isInRange(M, i, i + NumSubElts))
-        return -1;
-      int Offset = (NumSubElts - (M - (i + j))) % NumSubElts;
-      if (0 <= RotateAmt && Offset != RotateAmt)
-        return -1;
-      RotateAmt = Offset;
-    }
-  }
-  return RotateAmt;
-}
-
 static int matchShuffleAsBitRotate(MVT &RotateVT, int EltSizeInBits,
                                    const X86Subtarget &Subtarget,
                                    ArrayRef<int> Mask) {
   assert(!isNoopShuffleMask(Mask) && "We shouldn't lower no-op shuffles!");
   assert(EltSizeInBits < 64 && "Can't rotate 64-bit integers");
 
   // AVX512 only has vXi32/vXi64 rotates, so limit the rotation sub group size.
   int MinSubElts = Subtarget.hasAVX512() ? std::max(32 / EltSizeInBits, 2) : 2;
   int MaxSubElts = 64 / EltSizeInBits;
-  for (int NumSubElts = MinSubElts; NumSubElts <= MaxSubElts; NumSubElts *= 2) {
-    int RotateAmt = matchShuffleAsBitRotate(Mask, NumSubElts);
-    if (RotateAmt < 0)
-      continue;
-
-    int NumElts = Mask.size();
-    MVT RotateSVT = MVT::getIntegerVT(EltSizeInBits * NumSubElts);
-    RotateVT = MVT::getVectorVT(RotateSVT, NumElts / NumSubElts);
-    return RotateAmt * EltSizeInBits;
-  }
-
+  auto BitRotate = ShuffleVectorSDNode::isBitRotate(EltSizeInBits, Mask,
+                                                    MinSubElts, MaxSubElts);
+  if (!BitRotate)
     return -1;
+  auto [RotateEVT, RotateAmt] = *BitRotate;
+  RotateVT = RotateEVT.getSimpleVT();
+  return RotateAmt;
 }
 
 /// Lower shuffle using X86ISD::VROTLI rotations.
 static SDValue lowerShuffleAsBitRotate(const SDLoc &DL, MVT VT, SDValue V1,
                                        ArrayRef<int> Mask,
                                        const X86Subtarget &Subtarget,
                                        SelectionDAG &DAG) {
   // Only XOP + AVX512 targets have bit rotation instructions.

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVBB_V
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVBB_V
+; RUN: llc -mtriple=riscv32 -mattr=+zve32x,+zvfh,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVBB_ZVE32X
+; RUN: llc -mtriple=riscv64 -mattr=+zve32x,+zvfh,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVBB_ZVE32X
+
+define <8 x i1> @shuffle_v8i1_as_i8_1(<8 x i1> %v) {
+; CHECK-LABEL: shuffle_v8i1_as_i8_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT:    vslidedown.vi v9, v8, 1
+; CHECK-NEXT:    vslideup.vi v9, v8, 7
+; CHECK-NEXT:    vmsne.vi v0, v9, 0
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i1_as_i8_1:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
+; ZVBB_V-NEXT:    vror.vi v0, v0, 1
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i1_as_i8_1:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; ZVBB_ZVE32X-NEXT:    vror.vi v0, v0, 1
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i1> %v, <8 x i1> poison, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0>
+  ret <8 x i1> %shuffle
+}
+
+define <8 x i1> @shuffle_v8i1_as_i8_2(<8 x i1> %v) {
+; CHECK-LABEL: shuffle_v8i1_as_i8_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT:    vslidedown.vi v9, v8, 2
+; CHECK-NEXT:    vslideup.vi v9, v8, 6
+; CHECK-NEXT:    vmsne.vi v0, v9, 0
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i1_as_i8_2:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
+; ZVBB_V-NEXT:    vror.vi v0, v0, 2
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i1_as_i8_2:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; ZVBB_ZVE32X-NEXT:    vror.vi v0, v0, 2
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i1> %v, <8 x i1> poison, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1>
+  ret <8 x i1> %shuffle
+}
+
+define <8 x i1> @shuffle_v8i1_as_i8_3(<8 x i1> %v) {
+; CHECK-LABEL: shuffle_v8i1_as_i8_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT:    vslidedown.vi v9, v8, 3
+; CHECK-NEXT:    vslideup.vi v9, v8, 5
+; CHECK-NEXT:    vmsne.vi v0, v9, 0
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i1_as_i8_3:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
+; ZVBB_V-NEXT:    vror.vi v0, v0, 3
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i1_as_i8_3:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; ZVBB_ZVE32X-NEXT:    vror.vi v0, v0, 3
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i1> %v, <8 x i1> poison, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2>
+  ret <8 x i1> %shuffle
+}
+
+define <8 x i1> @shuffle_v8i1_as_i8_4(<8 x i1> %v) {
+; CHECK-LABEL: shuffle_v8i1_as_i8_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT:    vslidedown.vi v9, v8, 4
+; CHECK-NEXT:    vslideup.vi v9, v8, 4
+; CHECK-NEXT:    vmsne.vi v0, v9, 0
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i1_as_i8_4:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
+; ZVBB_V-NEXT:    vror.vi v0, v0, 4
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i1_as_i8_4:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; ZVBB_ZVE32X-NEXT:    vror.vi v0, v0, 4
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i1> %v, <8 x i1> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+  ret <8 x i1> %shuffle
+}
+
+define <8 x i1> @shuffle_v8i1_as_i8_5(<8 x i1> %v) {
+; CHECK-LABEL: shuffle_v8i1_as_i8_5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT:    vslidedown.vi v9, v8, 5
+; CHECK-NEXT:    vslideup.vi v9, v8, 3
+; CHECK-NEXT:    vmsne.vi v0, v9, 0
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i1_as_i8_5:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
+; ZVBB_V-NEXT:    vror.vi v0, v0, 5
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i1_as_i8_5:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; ZVBB_ZVE32X-NEXT:    vror.vi v0, v0, 5
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i1> %v, <8 x i1> poison, <8 x i32> <i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4>
+  ret <8 x i1> %shuffle
+}
+
+define <8 x i1> @shuffle_v8i1_as_i8_6(<8 x i1> %v) {
+; CHECK-LABEL: shuffle_v8i1_as_i8_6:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT:    vslidedown.vi v9, v8, 6
+; CHECK-NEXT:    vslideup.vi v9, v8, 2
+; CHECK-NEXT:    vmsne.vi v0, v9, 0
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i1_as_i8_6:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
+; ZVBB_V-NEXT:    vror.vi v0, v0, 6
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i1_as_i8_6:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; ZVBB_ZVE32X-NEXT:    vror.vi v0, v0, 6
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i1> %v, <8 x i1> poison, <8 x i32> <i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5>
+  ret <8 x i1> %shuffle
+}
+
+define <8 x i1> @shuffle_v8i1_as_i8_7(<8 x i1> %v) {
+; CHECK-LABEL: shuffle_v8i1_as_i8_7:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT:    vslidedown.vi v9, v8, 7
+; CHECK-NEXT:    vslideup.vi v9, v8, 1
+; CHECK-NEXT:    vmsne.vi v0, v9, 0
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i1_as_i8_7:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 1, e8, mf8, ta, ma
+; ZVBB_V-NEXT:    vror.vi v0, v0, 7
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i1_as_i8_7:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 1, e8, mf4, ta, ma
+; ZVBB_ZVE32X-NEXT:    vror.vi v0, v0, 7
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i1> %v, <8 x i1> poison, <8 x i32> <i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
+  ret <8 x i1> %shuffle
+}
+
+define <8 x i8> @shuffle_v8i8_as_i16(<8 x i8> %v) {
+; CHECK-LABEL: shuffle_v8i8_as_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI7_0)
+; CHECK-NEXT:    addi a0, a0, %lo(.LCPI7_0)
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vle8.v v10, (a0)
+; CHECK-NEXT:    vrgather.vv v9, v8, v10
+; CHECK-NEXT:    vmv1r.v v8, v9
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i8_as_i16:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 8
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i8_as_i16:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 4, e16, m2, ta, ma
+; ZVBB_ZVE32X-NEXT:    vror.vi v8, v8, 8
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
+  ret <8 x i8> %shuffle
+}
+
+define <8 x i8> @shuffle_v8i8_as_i32_8(<8 x i8> %v) {
+; CHECK-LABEL: shuffle_v8i8_as_i32_8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI8_0)
+; CHECK-NEXT:    addi a0, a0, %lo(.LCPI8_0)
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vle8.v v10, (a0)
+; CHECK-NEXT:    vrgather.vv v9, v8, v10
+; CHECK-NEXT:    vmv1r.v v8, v9
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i8_as_i32_8:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 8
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i8_as_i32_8:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
+; ZVBB_ZVE32X-NEXT:    vror.vi v8, v8, 8
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 1, i32 2, i32 3, i32 0, i32 5, i32 6, i32 7, i32 4>
+  ret <8 x i8> %shuffle
+}
+
+define <8 x i8> @shuffle_v8i8_as_i32_16(<8 x i8> %v) {
+; CHECK-LABEL: shuffle_v8i8_as_i32_16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI9_0)
+; CHECK-NEXT:    addi a0, a0, %lo(.LCPI9_0)
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vle8.v v10, (a0)
+; CHECK-NEXT:    vrgather.vv v9, v8, v10
+; CHECK-NEXT:    vmv1r.v v8, v9
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i8_as_i32_16:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 16
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i8_as_i32_16:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
+; ZVBB_ZVE32X-NEXT:    vror.vi v8, v8, 16
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 6, i32 7, i32 4, i32 5>
+  ret <8 x i8> %shuffle
+}
+
+define <8 x i8> @shuffle_v8i8_as_i32_24(<8 x i8> %v) {
+; CHECK-LABEL: shuffle_v8i8_as_i32_24:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI10_0)
+; CHECK-NEXT:    addi a0, a0, %lo(.LCPI10_0)
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vle8.v v10, (a0)
+; CHECK-NEXT:    vrgather.vv v9, v8, v10
+; CHECK-NEXT:    vmv1r.v v8, v9
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i8_as_i32_24:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 24
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i8_as_i32_24:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
+; ZVBB_ZVE32X-NEXT:    vror.vi v8, v8, 24
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 3, i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6>
+  ret <8 x i8> %shuffle
+}
+
+define <8 x i8> @shuffle_v8i8_as_i64_8(<8 x i8> %v) {
+; CHECK-LABEL: shuffle_v8i8_as_i64_8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vslidedown.vi v9, v8, 1
+; CHECK-NEXT:    vslideup.vi v9, v8, 7
+; CHECK-NEXT:    vmv1r.v v8, v9
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i8_as_i64_8:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 8
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i8_as_i64_8:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 8, e8, m2, ta, ma
+; ZVBB_ZVE32X-NEXT:    vslidedown.vi v10, v8, 1
+; ZVBB_ZVE32X-NEXT:    vslideup.vi v10, v8, 7
+; ZVBB_ZVE32X-NEXT:    vmv.v.v v8, v10
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0>
+  ret <8 x i8> %shuffle
+}
+
+define <8 x i8> @shuffle_v8i8_as_i64_16(<8 x i8> %v) {
+; CHECK-LABEL: shuffle_v8i8_as_i64_16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vslidedown.vi v9, v8, 2
+; CHECK-NEXT:    vslideup.vi v9, v8, 6
+; CHECK-NEXT:    vmv1r.v v8, v9
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i8_as_i64_16:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 16
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i8_as_i64_16:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 8, e8, m2, ta, ma
+; ZVBB_ZVE32X-NEXT:    vslidedown.vi v10, v8, 2
+; ZVBB_ZVE32X-NEXT:    vslideup.vi v10, v8, 6
+; ZVBB_ZVE32X-NEXT:    vmv.v.v v8, v10
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1>
+  ret <8 x i8> %shuffle
+}
+
+define <8 x i8> @shuffle_v8i8_as_i64_24(<8 x i8> %v) {
+; CHECK-LABEL: shuffle_v8i8_as_i64_24:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vslidedown.vi v9, v8, 3
+; CHECK-NEXT:    vslideup.vi v9, v8, 5
+; CHECK-NEXT:    vmv1r.v v8, v9
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i8_as_i64_24:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 24
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i8_as_i64_24:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 8, e8, m2, ta, ma
+; ZVBB_ZVE32X-NEXT:    vslidedown.vi v10, v8, 3
+; ZVBB_ZVE32X-NEXT:    vslideup.vi v10, v8, 5
+; ZVBB_ZVE32X-NEXT:    vmv.v.v v8, v10
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2>
+  ret <8 x i8> %shuffle
+}
+
+define <8 x i8> @shuffle_v8i8_as_i64_32(<8 x i8> %v) {
+; CHECK-LABEL: shuffle_v8i8_as_i64_32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vslidedown.vi v9, v8, 4
+; CHECK-NEXT:    vslideup.vi v9, v8, 4
+; CHECK-NEXT:    vmv1r.v v8, v9
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i8_as_i64_32:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 32
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i8_as_i64_32:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 8, e8, m2, ta, ma
+; ZVBB_ZVE32X-NEXT:    vslidedown.vi v10, v8, 4
+; ZVBB_ZVE32X-NEXT:    vslideup.vi v10, v8, 4
+; ZVBB_ZVE32X-NEXT:    vmv.v.v v8, v10
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
+  ret <8 x i8> %shuffle
+}
+
+define <8 x i8> @shuffle_v8i8_as_i64_40(<8 x i8> %v) {
+; CHECK-LABEL: shuffle_v8i8_as_i64_40:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vslidedown.vi v9, v8, 5
+; CHECK-NEXT:    vslideup.vi v9, v8, 3
+; CHECK-NEXT:    vmv1r.v v8, v9
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i8_as_i64_40:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 40
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i8_as_i64_40:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 8, e8, m2, ta, ma
+; ZVBB_ZVE32X-NEXT:    vslidedown.vi v10, v8, 5
+; ZVBB_ZVE32X-NEXT:    vslideup.vi v10, v8, 3
+; ZVBB_ZVE32X-NEXT:    vmv.v.v v8, v10
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4>
+  ret <8 x i8> %shuffle
+}
+
+define <8 x i8> @shuffle_v8i8_as_i64_48(<8 x i8> %v) {
+; CHECK-LABEL: shuffle_v8i8_as_i64_48:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vslidedown.vi v9, v8, 6
+; CHECK-NEXT:    vslideup.vi v9, v8, 2
+; CHECK-NEXT:    vmv1r.v v8, v9
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i8_as_i64_48:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 48
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i8_as_i64_48:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 8, e8, m2, ta, ma
+; ZVBB_ZVE32X-NEXT:    vslidedown.vi v10, v8, 6
+; ZVBB_ZVE32X-NEXT:    vslideup.vi v10, v8, 2
+; ZVBB_ZVE32X-NEXT:    vmv.v.v v8, v10
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5>
+  ret <8 x i8> %shuffle
+}
+
+define <8 x i8> @shuffle_v8i8_as_i64_56(<8 x i8> %v) {
+; CHECK-LABEL: shuffle_v8i8_as_i64_56:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vslidedown.vi v9, v8, 7
+; CHECK-NEXT:    vslideup.vi v9, v8, 1
+; CHECK-NEXT:    vmv1r.v v8, v9
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i8_as_i64_56:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 56
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i8_as_i64_56:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 8, e8, m2, ta, ma
+; ZVBB_ZVE32X-NEXT:    vslidedown.vi v10, v8, 7
+; ZVBB_ZVE32X-NEXT:    vslideup.vi v10, v8, 1
+; ZVBB_ZVE32X-NEXT:    vmv.v.v v8, v10
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
+  ret <8 x i8> %shuffle
+}
+
+define <8 x i16> @shuffle_v8i16_as_i32(<8 x i16> %v) {
+; CHECK-LABEL: shuffle_v8i16_as_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI18_0)
+; CHECK-NEXT:    addi a0, a0, %lo(.LCPI18_0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v10, (a0)
+; CHECK-NEXT:    vrgather.vv v9, v8, v10
+; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i16_as_i32:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 16
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i16_as_i32:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 4, e32, m4, ta, ma
+; ZVBB_ZVE32X-NEXT:    vror.vi v8, v8, 16
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i16> %v, <8 x i16> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
+  ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_v8i16_as_i64_16(<8 x i16> %v) {
+; CHECK-LABEL: shuffle_v8i16_as_i64_16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI19_0)
+; CHECK-NEXT:    addi a0, a0, %lo(.LCPI19_0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v10, (a0)
+; CHECK-NEXT:    vrgather.vv v9, v8, v10
+; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i16_as_i64_16:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 16
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i16_as_i64_16:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    lui a0, %hi(.LCPI19_0)
+; ZVBB_ZVE32X-NEXT:    addi a0, a0, %lo(.LCPI19_0)
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 8, e16, m4, ta, ma
+; ZVBB_ZVE32X-NEXT:    vle16.v v16, (a0)
+; ZVBB_ZVE32X-NEXT:    vrgather.vv v12, v8, v16
+; ZVBB_ZVE32X-NEXT:    vmv.v.v v8, v12
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i16> %v, <8 x i16> poison, <8 x i32> <i32 1, i32 2, i32 3, i32 0, i32 5, i32 6, i32 7, i32 4>
+  ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_v8i16_as_i64_32(<8 x i16> %v) {
+; CHECK-LABEL: shuffle_v8i16_as_i64_32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI20_0)
+; CHECK-NEXT:    addi a0, a0, %lo(.LCPI20_0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v10, (a0)
+; CHECK-NEXT:    vrgather.vv v9, v8, v10
+; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i16_as_i64_32:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 32
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i16_as_i64_32:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    lui a0, %hi(.LCPI20_0)
+; ZVBB_ZVE32X-NEXT:    addi a0, a0, %lo(.LCPI20_0)
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 8, e16, m4, ta, ma
+; ZVBB_ZVE32X-NEXT:    vle16.v v16, (a0)
+; ZVBB_ZVE32X-NEXT:    vrgather.vv v12, v8, v16
+; ZVBB_ZVE32X-NEXT:    vmv.v.v v8, v12
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i16> %v, <8 x i16> poison, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 6, i32 7, i32 4, i32 5>
+  ret <8 x i16> %shuffle
+}
+
+define <8 x i16> @shuffle_v8i16_as_i64_48(<8 x i16> %v) {
+; CHECK-LABEL: shuffle_v8i16_as_i64_48:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI21_0)
+; CHECK-NEXT:    addi a0, a0, %lo(.LCPI21_0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v10, (a0)
+; CHECK-NEXT:    vrgather.vv v9, v8, v10
+; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i16_as_i64_48:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 48
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i16_as_i64_48:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    lui a0, %hi(.LCPI21_0)
+; ZVBB_ZVE32X-NEXT:    addi a0, a0, %lo(.LCPI21_0)
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 8, e16, m4, ta, ma
+; ZVBB_ZVE32X-NEXT:    vle16.v v16, (a0)
+; ZVBB_ZVE32X-NEXT:    vrgather.vv v12, v8, v16
+; ZVBB_ZVE32X-NEXT:    vmv.v.v v8, v12
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i16> %v, <8 x i16> poison, <8 x i32> <i32 3, i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6>
+  ret <8 x i16> %shuffle
+}
+
+define <8 x i32> @shuffle_v8i32_as_i64(<8 x i32> %v) {
+; CHECK-LABEL: shuffle_v8i32_as_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI22_0)
+; CHECK-NEXT:    addi a0, a0, %lo(.LCPI22_0)
+; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT:    vle32.v v12, (a0)
+; CHECK-NEXT:    vrgather.vv v10, v8, v12
+; CHECK-NEXT:    vmv.v.v v8, v10
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8i32_as_i64:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 32
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8i32_as_i64:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    lui a0, %hi(.LCPI22_0)
+; ZVBB_ZVE32X-NEXT:    addi a0, a0, %lo(.LCPI22_0)
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 8, e32, m8, ta, ma
+; ZVBB_ZVE32X-NEXT:    vle32.v v24, (a0)
+; ZVBB_ZVE32X-NEXT:    vrgather.vv v16, v8, v24
+; ZVBB_ZVE32X-NEXT:    vmv.v.v v8, v16
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x i32> %v, <8 x i32> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
+  ret <8 x i32> %shuffle
+}
+
+define <8 x half> @shuffle_v8f16_as_i32(<8 x half> %v) {
+; CHECK-LABEL: shuffle_v8f16_as_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI23_0)
+; CHECK-NEXT:    addi a0, a0, %lo(.LCPI23_0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v10, (a0)
+; CHECK-NEXT:    vrgather.vv v9, v8, v10
+; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8f16_as_i32:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 16
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8f16_as_i32:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 4, e32, m4, ta, ma
+; ZVBB_ZVE32X-NEXT:    vror.vi v8, v8, 16
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x half> %v, <8 x half> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
+  ret <8 x half> %shuffle
+}
+
+define <8 x half> @shuffle_v8f16_as_i64_16(<8 x half> %v) {
+; CHECK-LABEL: shuffle_v8f16_as_i64_16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI24_0)
+; CHECK-NEXT:    addi a0, a0, %lo(.LCPI24_0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v10, (a0)
+; CHECK-NEXT:    vrgather.vv v9, v8, v10
+; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8f16_as_i64_16:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 16
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8f16_as_i64_16:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    lui a0, %hi(.LCPI24_0)
+; ZVBB_ZVE32X-NEXT:    addi a0, a0, %lo(.LCPI24_0)
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 8, e16, m4, ta, ma
+; ZVBB_ZVE32X-NEXT:    vle16.v v16, (a0)
+; ZVBB_ZVE32X-NEXT:    vrgather.vv v12, v8, v16
+; ZVBB_ZVE32X-NEXT:    vmv.v.v v8, v12
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x half> %v, <8 x half> poison, <8 x i32> <i32 1, i32 2, i32 3, i32 0, i32 5, i32 6, i32 7, i32 4>
+  ret <8 x half> %shuffle
+}
+
+define <8 x half> @shuffle_v8f16_as_i64_32(<8 x half> %v) {
+; CHECK-LABEL: shuffle_v8f16_as_i64_32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI25_0)
+; CHECK-NEXT:    addi a0, a0, %lo(.LCPI25_0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v10, (a0)
+; CHECK-NEXT:    vrgather.vv v9, v8, v10
+; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8f16_as_i64_32:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 32
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8f16_as_i64_32:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    lui a0, %hi(.LCPI25_0)
+; ZVBB_ZVE32X-NEXT:    addi a0, a0, %lo(.LCPI25_0)
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 8, e16, m4, ta, ma
+; ZVBB_ZVE32X-NEXT:    vle16.v v16, (a0)
+; ZVBB_ZVE32X-NEXT:    vrgather.vv v12, v8, v16
+; ZVBB_ZVE32X-NEXT:    vmv.v.v v8, v12
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x half> %v, <8 x half> poison, <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 6, i32 7, i32 4, i32 5>
+  ret <8 x half> %shuffle
+}
+
+define <8 x half> @shuffle_v8f16_as_i64_48(<8 x half> %v) {
+; CHECK-LABEL: shuffle_v8f16_as_i64_48:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI26_0)
+; CHECK-NEXT:    addi a0, a0, %lo(.LCPI26_0)
+; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT:    vle16.v v10, (a0)
+; CHECK-NEXT:    vrgather.vv v9, v8, v10
+; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8f16_as_i64_48:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 48
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8f16_as_i64_48:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    lui a0, %hi(.LCPI26_0)
+; ZVBB_ZVE32X-NEXT:    addi a0, a0, %lo(.LCPI26_0)
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 8, e16, m4, ta, ma
+; ZVBB_ZVE32X-NEXT:    vle16.v v16, (a0)
+; ZVBB_ZVE32X-NEXT:    vrgather.vv v12, v8, v16
+; ZVBB_ZVE32X-NEXT:    vmv.v.v v8, v12
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x half> %v, <8 x half> poison, <8 x i32> <i32 3, i32 0, i32 1, i32 2, i32 7, i32 4, i32 5, i32 6>
+  ret <8 x half> %shuffle
+}
+
+define <8 x float> @shuffle_v8f32_as_i64(<8 x float> %v) {
+; CHECK-LABEL: shuffle_v8f32_as_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, %hi(.LCPI27_0)
+; CHECK-NEXT:    addi a0, a0, %lo(.LCPI27_0)
+; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-NEXT:    vle32.v v12, (a0)
+; CHECK-NEXT:    vrgather.vv v10, v8, v12
+; CHECK-NEXT:    vmv.v.v v8, v10
+; CHECK-NEXT:    ret
+;
+; ZVBB_V-LABEL: shuffle_v8f32_as_i64:
+; ZVBB_V:       # %bb.0:
+; ZVBB_V-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
+; ZVBB_V-NEXT:    vror.vi v8, v8, 32
+; ZVBB_V-NEXT:    ret
+;
+; ZVBB_ZVE32X-LABEL: shuffle_v8f32_as_i64:
+; ZVBB_ZVE32X:       # %bb.0:
+; ZVBB_ZVE32X-NEXT:    lui a0, %hi(.LCPI27_0)
+; ZVBB_ZVE32X-NEXT:    addi a0, a0, %lo(.LCPI27_0)
+; ZVBB_ZVE32X-NEXT:    vsetivli zero, 8, e32, m8, ta, ma
+; ZVBB_ZVE32X-NEXT:    vle32.v v24, (a0)
+; ZVBB_ZVE32X-NEXT:    vrgather.vv v16, v8, v24
+; ZVBB_ZVE32X-NEXT:    vmv.v.v v8, v16
+; ZVBB_ZVE32X-NEXT:    ret
+  %shuffle = shufflevector <8 x float> %v, <8 x float> poison, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
+  ret <8 x float> %shuffle
+}