[X86] Add SM4 instructions.

[FreddyYe]

Summary

For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

[pengfei]

llvm/test/MC/Disassembler/X86/sm4-64.txt

4–5

Merge 64-bit tests.

[pengfei]

llvm/test/CodeGen/X86/sm4-intrinsics.ll

3

Remove O0.

4

ditto.

[skan]

llvm/lib/Target/X86/X86InstrSSE.td

8308

From the description, it seems that WriteVecIMul is not the right schedule?

llvm/test/MC/Disassembler/X86/sm4-64.txt

5

Remove -x86-asm-syntax=intel

[FreddyYe]

llvm/lib/Target/X86/X86InstrSSE.td

8308

Added FIXME.

[FreddyYe]

Address comments.

[RKSimon]

clang/lib/Headers/sm4intrin.h

18

doxygen descriptions?

clang/test/CodeGen/X86/sm4-builtins.c

6

what is stddef.h needed for?

llvm/test/MC/Disassembler/X86/sm4-64.txt

5

As with sm3 - keep the 64-bit tests but make sure we have at least some test coverage with x86_64 specific registers (ymm8..ymm15 / r8..r15 etc.)

[FreddyYe]

Remove #include <stddef.h>

[FreddyYe]

clang/test/CodeGen/X86/sm4-builtins.c

6

Good catch! probably be copy paste error.

[FreddyYe]

Address comments.

[RKSimon]

clang/lib/Headers/sm4intrin.h

27

VPDPBSSD ?

[FreddyYe]

Address comments.

[RKSimon]

@pengfei Are you happy with the intrinsics doxygen descriptions?

[pengfei]

In D155148#4510472, @RKSimon wrote:

@pengfei Are you happy with the intrinsics doxygen descriptions?

LGTM except for one comment.

clang/lib/Headers/sm4intrin.h

24

Missing return type here. The same for below.

[FreddyYe]

Address comment.

[skan]

LGTM

[FreddyYe]

rebase and fix lit fail

clang/docs/ReleaseNotes.rst

 - Support ISA of ``SHA512``.
   * Support intrinsic of ``_mm256_sha512msg1_epi64``.
   * Support intrinsic of ``_mm256_sha512msg2_epi64``.
   * Support intrinsic of ``_mm256_sha512rnds2_epi64``.
 - Support ISA of ``SM3``.
   * Support intrinsic of ``_mm_sm3msg1_epi32``.
   * Support intrinsic of ``_mm_sm3msg2_epi32``.
   * Support intrinsic of ``_mm_sm3rnds2_epi32``.
+- Support ISA of ``SM4``.
+  * Support intrinsic of ``_mm(256)_sm4key4_epi32``.
+  * Support intrinsic of ``_mm(256)_sm4rnds4_epi32``.
 
 Arm and AArch64 Support
 ^^^^^^^^^^^^^^^^^^^^^^^
 
 - The hard-float ABI is now available in Armv8.1-M configurations that
   have integer MVE instructions (and therefore have FP registers) but
   no scalar or vector floating point computation. Previously, trying
   to select the hard-float ABI on such a target (via

clang/include/clang/Basic/BuiltinsX86.def

 TARGET_HEADER_BUILTIN(_InterlockedOr64,          "WiWiD*Wi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_InterlockedXor64,         "WiWiD*Wi", "nh", INTRIN_H, ALL_MS_LANGUAGES, "")
 
 // SM3
 TARGET_BUILTIN(__builtin_ia32_vsm3msg1, "V4UiV4UiV4UiV4Ui", "nV:128:", "sm3")
 TARGET_BUILTIN(__builtin_ia32_vsm3msg2, "V4UiV4UiV4UiV4Ui", "nV:128:", "sm3")
 TARGET_BUILTIN(__builtin_ia32_vsm3rnds2, "V4UiV4UiV4UiV4UiIUi", "nV:128:", "sm3")
 
+// SM4
+TARGET_BUILTIN(__builtin_ia32_vsm4key4128, "V4UiV4UiV4Ui", "nV:128:", "sm4")
+TARGET_BUILTIN(__builtin_ia32_vsm4key4256, "V8UiV8UiV8Ui", "nV:256:", "sm4")
+TARGET_BUILTIN(__builtin_ia32_vsm4rnds4128, "V4UiV4UiV4Ui", "nV:128:", "sm4")
+TARGET_BUILTIN(__builtin_ia32_vsm4rnds4256, "V8UiV8UiV8Ui", "nV:256:", "sm4")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN
 #undef TARGET_HEADER_BUILTIN

clang/include/clang/Driver/Options.td

 def msgx : Flag<["-"], "msgx">, Group<m_x86_Features_Group>;
 def mno_sgx : Flag<["-"], "mno-sgx">, Group<m_x86_Features_Group>;
 def msha : Flag<["-"], "msha">, Group<m_x86_Features_Group>;
 def mno_sha : Flag<["-"], "mno-sha">, Group<m_x86_Features_Group>;
 def msha512 : Flag<["-"], "msha512">, Group<m_x86_Features_Group>;
 def mno_sha512 : Flag<["-"], "mno-sha512">, Group<m_x86_Features_Group>;
 def msm3 : Flag<["-"], "msm3">, Group<m_x86_Features_Group>;
 def mno_sm3 : Flag<["-"], "mno-sm3">, Group<m_x86_Features_Group>;
+def msm4 : Flag<["-"], "msm4">, Group<m_x86_Features_Group>;
+def mno_sm4 : Flag<["-"], "mno-sm4">, Group<m_x86_Features_Group>;
 def mtbm : Flag<["-"], "mtbm">, Group<m_x86_Features_Group>;
 def mno_tbm : Flag<["-"], "mno-tbm">, Group<m_x86_Features_Group>;
 def mtsxldtrk : Flag<["-"], "mtsxldtrk">, Group<m_x86_Features_Group>;
 def mno_tsxldtrk : Flag<["-"], "mno-tsxldtrk">, Group<m_x86_Features_Group>;
 def muintr : Flag<["-"], "muintr">, Group<m_x86_Features_Group>;
 def mno_uintr : Flag<["-"], "mno-uintr">, Group<m_x86_Features_Group>;
 def mvaes : Flag<["-"], "mvaes">, Group<m_x86_Features_Group>;
 def mno_vaes : Flag<["-"], "mno-vaes">, Group<m_x86_Features_Group>;

clang/lib/Basic/Targets/X86.h

class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
   bool HasAVXIFMA = false;
   bool HasAVX512IFMA = false;
   bool HasAVX512VP2INTERSECT = false;
   bool HasSHA = false;
   bool HasSHA512 = false;
   bool HasSHSTK = false;
   bool HasSM3 = false;
   bool HasSGX = false;
+  bool HasSM4 = false;
   bool HasCX8 = false;
   bool HasCX16 = false;
   bool HasFXSR = false;
   bool HasXSAVE = false;
   bool HasXSAVEOPT = false;
   bool HasXSAVEC = false;
   bool HasXSAVES = false;
   bool HasMWAITX = false;

clang/lib/Basic/Targets/X86.cpp

for (const auto &Feature : Features) {
     } else if (Feature == "+sha") {
       HasSHA = true;
     } else if (Feature == "+sha512") {
       HasSHA512 = true;
     } else if (Feature == "+shstk") {
       HasSHSTK = true;
     } else if (Feature == "+sm3") {
       HasSM3 = true;
+    } else if (Feature == "+sm4") {
+      HasSM4 = true;
     } else if (Feature == "+movbe") {
       HasMOVBE = true;
     } else if (Feature == "+sgx") {
       HasSGX = true;
     } else if (Feature == "+cx8") {
       HasCX8 = true;
     } else if (Feature == "+cx16") {
       HasCX16 = true;
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
   if (HasWBNOINVD)
     Builder.defineMacro("__WBNOINVD__");
   if (HasSHSTK)
     Builder.defineMacro("__SHSTK__");
   if (HasSGX)
     Builder.defineMacro("__SGX__");
   if (HasSM3)
     Builder.defineMacro("__SM3__");
+  if (HasSM4)
+    Builder.defineMacro("__SM4__");
   if (HasPREFETCHI)
     Builder.defineMacro("__PREFETCHI__");
   if (HasPREFETCHWT1)
     Builder.defineMacro("__PREFETCHWT1__");
   if (HasCLZERO)
     Builder.defineMacro("__CLZERO__");
   if (HasKL)
     Builder.defineMacro("__KL__");
return llvm::StringSwitch<bool>(Name)
       .Case("rtm", true)
       .Case("sahf", true)
       .Case("serialize", true)
       .Case("sgx", true)
       .Case("sha", true)
       .Case("sha512", true)
       .Case("shstk", true)
       .Case("sm3", true)
+      .Case("sm4", true)
       .Case("sse", true)
       .Case("sse2", true)
       .Case("sse3", true)
       .Case("ssse3", true)
       .Case("sse4", true)
       .Case("sse4.1", true)
       .Case("sse4.2", true)
       .Case("sse4a", true)
return llvm::StringSwitch<bool>(Feature)
       .Case("rtm", HasRTM)
       .Case("sahf", HasLAHFSAHF)
       .Case("serialize", HasSERIALIZE)
       .Case("sgx", HasSGX)
       .Case("sha", HasSHA)
       .Case("sha512", HasSHA512)
       .Case("shstk", HasSHSTK)
       .Case("sm3", HasSM3)
+      .Case("sm4", HasSM4)
       .Case("sse", SSELevel >= SSE1)
       .Case("sse2", SSELevel >= SSE2)
       .Case("sse3", SSELevel >= SSE3)
       .Case("ssse3", SSELevel >= SSSE3)
       .Case("sse4.1", SSELevel >= SSE41)
       .Case("sse4.2", SSELevel >= SSE42)
       .Case("sse4a", XOPLevel >= SSE4A)
       .Case("tbm", HasTBM)

clang/lib/Headers/CMakeLists.txt

# Intrinsics
   rdpruintrin.h
   rdseedintrin.h
   rtmintrin.h
   serializeintrin.h
   sgxintrin.h
   sha512intrin.h
   shaintrin.h
   sm3intrin.h
+  sm4intrin.h
   smmintrin.h
   tbmintrin.h
   tmmintrin.h
   tsxldtrkintrin.h
   uintrintrin.h
   vaesintrin.h
   vpclmulqdqintrin.h
   waitpkgintrin.h

clang/lib/Headers/immintrin.h

 #endif
 
 #if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
     defined(__SM3__)
 #include <sm3intrin.h>
 #endif
 
 #if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
+    defined(__SM4__)
+#include <sm4intrin.h>
+#endif
+
+#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
     defined(__RDPID__)
 /// Returns the value of the IA32_TSC_AUX MSR (0xc0000103).
 ///
 /// \headerfile <immintrin.h>
 ///
 /// This intrinsic corresponds to the <c> RDPID </c> instruction.
 static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__, __target__("rdpid")))
 _rdpid_u32(void) {

clang/lib/Headers/sm4intrin.h

+/*===--------------- sm4intrin.h - SM4 intrinsics -----------------===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+
+#ifndef __IMMINTRIN_H
+#error "Never use <sm4intrin.h> directly; include <immintrin.h> instead."
+#endif // __IMMINTRIN_H
+
+#ifndef __SM4INTRIN_H
+#define __SM4INTRIN_H
+
+/// This intrinsic performs four rounds of SM4 key expansion. The intrinsic
+///    operates on independent 128-bit lanes. The calculated results are
+///    stored in \a dst.
+/// \headerfile <immintrin.h>
+///
+/// \code
+/// __m128i _mm_sm4key4_epi32(__m128i __A, __m128i __B)
+/// \endcode
+///
+/// This intrinsic corresponds to the \c VSM4KEY4 instruction.
+///
+/// \param __A
+///    A 128-bit vector of [4 x int].
+/// \param __B
+///    A 128-bit vector of [4 x int].
+/// \returns
+///    A 128-bit vector of [4 x int].
+///
+/// \code{.operation}
+/// DEFINE ROL32(dword, n) {
+///   count := n % 32
+///   dest := (dword << count) | (dword >> (32-count))
+///   RETURN dest
+/// }
+/// DEFINE SBOX_BYTE(dword, i) {
+///   RETURN sbox[dword.byte[i]]
+/// }
+/// DEFINE lower_t(dword) {
+///   tmp.byte[0] := SBOX_BYTE(dword, 0)
+///   tmp.byte[1] := SBOX_BYTE(dword, 1)
+///   tmp.byte[2] := SBOX_BYTE(dword, 2)
+///   tmp.byte[3] := SBOX_BYTE(dword, 3)
+///   RETURN tmp
+/// }
+/// DEFINE L_KEY(dword) {
+///   RETURN dword ^ ROL32(dword, 13) ^ ROL32(dword, 23)
+/// }
+/// DEFINE T_KEY(dword) {
+///   RETURN L_KEY(lower_t(dword))
+/// }
+/// DEFINE F_KEY(X0, X1, X2, X3, round_key) {
+///   RETURN X0 ^ T_KEY(X1 ^ X2 ^ X3 ^ round_key)
+/// }
+/// FOR i:= 0 to 0
+///   P[0] := __B.xmm[i].dword[0]
+///   P[1] := __B.xmm[i].dword[1]
+///   P[2] := __B.xmm[i].dword[2]
+///   P[3] := __B.xmm[i].dword[3]
+///   C[0] := F_KEY(P[0], P[1], P[2], P[3], __A.xmm[i].dword[0])
+///   C[1] := F_KEY(P[1], P[2], P[3], C[0], __A.xmm[i].dword[1])
+///   C[2] := F_KEY(P[2], P[3], C[0], C[1], __A.xmm[i].dword[2])
+///   C[3] := F_KEY(P[3], C[0], C[1], C[2], __A.xmm[i].dword[3])
+///   DEST.xmm[i].dword[0] := C[0]
+///   DEST.xmm[i].dword[1] := C[1]
+///   DEST.xmm[i].dword[2] := C[2]
+///   DEST.xmm[i].dword[3] := C[3]
+/// ENDFOR
+/// DEST[MAX:128] := 0
+/// \endcode
+#define _mm_sm4key4_epi32(A, B)                                                \
+  (__m128i) __builtin_ia32_vsm4key4128((__v4su)A, (__v4su)B)
+
+/// This intrinsic performs four rounds of SM4 key expansion. The intrinsic
+///    operates on independent 128-bit lanes. The calculated results are
+///    stored in \a dst.
+/// \headerfile <immintrin.h>
+///
+/// \code
+/// __m256i _mm256_sm4key4_epi32(__m256i __A, __m256i __B)
+/// \endcode
+///
+/// This intrinsic corresponds to the \c VSM4KEY4 instruction.
+///
+/// \param __A
+///    A 256-bit vector of [8 x int].
+/// \param __B
+///    A 256-bit vector of [8 x int].
+/// \returns
+///    A 256-bit vector of [8 x int].
+///
+/// \code{.operation}
+/// DEFINE ROL32(dword, n) {
+///   count := n % 32
+///   dest := (dword << count) | (dword >> (32-count))
+///   RETURN dest
+/// }
+/// DEFINE SBOX_BYTE(dword, i) {
+///   RETURN sbox[dword.byte[i]]
+/// }
+/// DEFINE lower_t(dword) {
+///   tmp.byte[0] := SBOX_BYTE(dword, 0)
+///   tmp.byte[1] := SBOX_BYTE(dword, 1)
+///   tmp.byte[2] := SBOX_BYTE(dword, 2)
+///   tmp.byte[3] := SBOX_BYTE(dword, 3)
+///   RETURN tmp
+/// }
+/// DEFINE L_KEY(dword) {
+///   RETURN dword ^ ROL32(dword, 13) ^ ROL32(dword, 23)
+/// }
+/// DEFINE T_KEY(dword) {
+///   RETURN L_KEY(lower_t(dword))
+/// }
+/// DEFINE F_KEY(X0, X1, X2, X3, round_key) {
+///   RETURN X0 ^ T_KEY(X1 ^ X2 ^ X3 ^ round_key)
+/// }
+/// FOR i:= 0 to 1
+///   P[0] := __B.xmm[i].dword[0]
+///   P[1] := __B.xmm[i].dword[1]
+///   P[2] := __B.xmm[i].dword[2]
+///   P[3] := __B.xmm[i].dword[3]
+///   C[0] := F_KEY(P[0], P[1], P[2], P[3], __A.xmm[i].dword[0])
+///   C[1] := F_KEY(P[1], P[2], P[3], C[0], __A.xmm[i].dword[1])
+///   C[2] := F_KEY(P[2], P[3], C[0], C[1], __A.xmm[i].dword[2])
+///   C[3] := F_KEY(P[3], C[0], C[1], C[2], __A.xmm[i].dword[3])
+///   DEST.xmm[i].dword[0] := C[0]
+///   DEST.xmm[i].dword[1] := C[1]
+///   DEST.xmm[i].dword[2] := C[2]
+///   DEST.xmm[i].dword[3] := C[3]
+/// ENDFOR
+/// DEST[MAX:256] := 0
+/// \endcode
+#define _mm256_sm4key4_epi32(A, B)                                             \
+  (__m256i) __builtin_ia32_vsm4key4256((__v8su)A, (__v8su)B)
+
+/// This intrinisc performs four rounds of SM4 encryption. The intrinisc
+///    operates on independent 128-bit lanes. The calculated results are
+///    stored in \a dst.
+/// \headerfile <immintrin.h>
+///
+/// \code
+/// __m128i _mm_sm4rnds4_epi32(__m128i __A, __m128i __B)
+/// \endcode
+///
+/// This intrinsic corresponds to the \c VSM4RNDS4 instruction.
+///
+/// \param __A
+///    A 128-bit vector of [4 x int].
+/// \param __B
+///    A 128-bit vector of [4 x int].
+/// \returns
+///    A 128-bit vector of [4 x int].
+///
+/// \code{.operation}
+/// DEFINE ROL32(dword, n) {
+///   count := n % 32
+///   dest := (dword << count) | (dword >> (32-count))
+///   RETURN dest
+/// }
+/// DEFINE lower_t(dword) {
+///   tmp.byte[0] := SBOX_BYTE(dword, 0)
+///   tmp.byte[1] := SBOX_BYTE(dword, 1)
+///   tmp.byte[2] := SBOX_BYTE(dword, 2)
+///   tmp.byte[3] := SBOX_BYTE(dword, 3)
+///   RETURN tmp
+/// }
+/// DEFINE L_RND(dword) {
+///   tmp := dword
+///   tmp := tmp ^ ROL32(dword, 2)
+///   tmp := tmp ^ ROL32(dword, 10)
+///   tmp := tmp ^ ROL32(dword, 18)
+///   tmp := tmp ^ ROL32(dword, 24)
+///   RETURN tmp
+/// }
+/// DEFINE T_RND(dword) {
+///   RETURN L_RND(lower_t(dword))
+/// }
+/// DEFINE F_RND(X0, X1, X2, X3, round_key) {
+///   RETURN X0 ^ T_RND(X1 ^ X2 ^ X3 ^ round_key)
+/// }
+/// FOR i:= 0 to 0
+///   P[0] := __B.xmm[i].dword[0]
+///   P[1] := __B.xmm[i].dword[1]
+///   P[2] := __B.xmm[i].dword[2]
+///   P[3] := __B.xmm[i].dword[3]
+///   C[0] := F_RND(P[0], P[1], P[2], P[3], __A.xmm[i].dword[0])
+///   C[1] := F_RND(P[1], P[2], P[3], C[0], __A.xmm[i].dword[1])
+///   C[2] := F_RND(P[2], P[3], C[0], C[1], __A.xmm[i].dword[2])
+///   C[3] := F_RND(P[3], C[0], C[1], C[2], __A.xmm[i].dword[3])
+///   DEST.xmm[i].dword[0] := C[0]
+///   DEST.xmm[i].dword[1] := C[1]
+///   DEST.xmm[i].dword[2] := C[2]
+///   DEST.xmm[i].dword[3] := C[3]
+/// ENDFOR
+/// DEST[MAX:128] := 0
+/// \endcode
+#define _mm_sm4rnds4_epi32(A, B)                                               \
+  (__m128i) __builtin_ia32_vsm4rnds4128((__v4su)A, (__v4su)B)
+
+/// This intrinisc performs four rounds of SM4 encryption. The intrinisc
+///    operates on independent 128-bit lanes. The calculated results are
+///    stored in \a dst.
+/// \headerfile <immintrin.h>
+///
+/// \code
+/// __m256i _mm256_sm4rnds4_epi32(__m256i __A, __m256i __B)
+/// \endcode
+///
+/// This intrinsic corresponds to the \c VSM4RNDS4 instruction.
+///
+/// \param __A
+///    A 256-bit vector of [8 x int].
+/// \param __B
+///    A 256-bit vector of [8 x int].
+/// \returns
+///    A 256-bit vector of [8 x int].
+///
+/// \code{.operation}
+/// DEFINE ROL32(dword, n) {
+///   count := n % 32
+///   dest := (dword << count) | (dword >> (32-count))
+///   RETURN dest
+/// }
+/// DEFINE lower_t(dword) {
+///   tmp.byte[0] := SBOX_BYTE(dword, 0)
+///   tmp.byte[1] := SBOX_BYTE(dword, 1)
+///   tmp.byte[2] := SBOX_BYTE(dword, 2)
+///   tmp.byte[3] := SBOX_BYTE(dword, 3)
+///   RETURN tmp
+/// }
+/// DEFINE L_RND(dword) {
+///   tmp := dword
+///   tmp := tmp ^ ROL32(dword, 2)
+///   tmp := tmp ^ ROL32(dword, 10)
+///   tmp := tmp ^ ROL32(dword, 18)
+///   tmp := tmp ^ ROL32(dword, 24)
+///   RETURN tmp
+/// }
+/// DEFINE T_RND(dword) {
+///   RETURN L_RND(lower_t(dword))
+/// }
+/// DEFINE F_RND(X0, X1, X2, X3, round_key) {
+///   RETURN X0 ^ T_RND(X1 ^ X2 ^ X3 ^ round_key)
+/// }
+/// FOR i:= 0 to 0
+///   P[0] := __B.xmm[i].dword[0]
+///   P[1] := __B.xmm[i].dword[1]
+///   P[2] := __B.xmm[i].dword[2]
+///   P[3] := __B.xmm[i].dword[3]
+///   C[0] := F_RND(P[0], P[1], P[2], P[3], __A.xmm[i].dword[0])
+///   C[1] := F_RND(P[1], P[2], P[3], C[0], __A.xmm[i].dword[1])
+///   C[2] := F_RND(P[2], P[3], C[0], C[1], __A.xmm[i].dword[2])
+///   C[3] := F_RND(P[3], C[0], C[1], C[2], __A.xmm[i].dword[3])
+///   DEST.xmm[i].dword[0] := C[0]
+///   DEST.xmm[i].dword[1] := C[1]
+///   DEST.xmm[i].dword[2] := C[2]
+///   DEST.xmm[i].dword[3] := C[3]
+/// ENDFOR
+/// DEST[MAX:256] := 0
+/// \endcode
+#define _mm256_sm4rnds4_epi32(A, B)                                            \
+  (__m256i) __builtin_ia32_vsm4rnds4256((__v8su)A, (__v8su)B)
+
+#endif // __SM4INTRIN_H

clang/test/CodeGen/X86/sm4-builtins.c

+// RUN: %clang_cc1 %s -ffreestanding -triple=x86_64-unknown-unknown -target-feature +sm4 -emit-llvm -o - -Wall -Werror | FileCheck %s
+// RUN: %clang_cc1 %s -ffreestanding -triple=i386-unknown-unknown -target-feature +sm4 -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include <immintrin.h>
+
+__m128i test_mm_sm4key4_epi32(__m128i __A, __m128i __B) {
+  // CHECK-LABEL: @test_mm_sm4key4_epi32(
+  // CHECK: call <4 x i32> @llvm.x86.vsm4key4128(<4 x i32> %{{.*}}, <4 x i32> %{{.*}})
+  return _mm_sm4key4_epi32(__A, __B);
+}
+
+__m256i test_mm256_sm4key4_epi32(__m256i __A, __m256i __B) {
+  // CHECK-LABEL: @test_mm256_sm4key4_epi32(
+  // CHECK: call <8 x i32> @llvm.x86.vsm4key4256(<8 x i32> %{{.*}}, <8 x i32> %{{.*}})
+  return _mm256_sm4key4_epi32(__A, __B);
+}
+
+__m128i test_mm_sm4rnds4_epi32(__m128i __A, __m128i __B) {
+  // CHECK-LABEL: @test_mm_sm4rnds4_epi32(
+  // CHECK: call <4 x i32> @llvm.x86.vsm4rnds4128(<4 x i32> %{{.*}}, <4 x i32> %{{.*}})
+  return _mm_sm4rnds4_epi32(__A, __B);
+}
+
+__m256i test_mm256_sm4rnds4_epi32(__m256i __A, __m256i __B) {
+  // CHECK-LABEL: @test_mm256_sm4rnds4_epi32(
+  // CHECK: call <8 x i32> @llvm.x86.vsm4rnds4256(<8 x i32> %{{.*}}, <8 x i32> %{{.*}})
+  return _mm256_sm4rnds4_epi32(__A, __B);
+}

clang/test/CodeGen/attr-target-x86.c

 // CHECK: qax{{.*}} #5
 // CHECK: qq{{.*}} #6
 // CHECK: lake{{.*}} #7
 // CHECK: use_before_def{{.*}} #7
 // CHECK: walrus{{.*}} #8
 // CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87" "tune-cpu"="i686"
 // CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
 // CHECK-NOT: tune-cpu
-// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sha512,-sm3,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686"
+// CHECK: #2 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-aes,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-gfni,-kl,-pclmul,-sha,-sha512,-sm3,-sm4,-sse2,-sse3,-sse4.1,-sse4.2,-sse4a,-ssse3,-vaes,-vpclmulqdq,-widekl,-xop" "tune-cpu"="i686"
 // CHECK: #3 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+crc32,+cx8,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87" "tune-cpu"="i686"
-// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-sha512,-sm3,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686"
+// CHECK: #4 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-avx,-avx2,-avx512bf16,-avx512bitalg,-avx512bw,-avx512cd,-avx512dq,-avx512er,-avx512f,-avx512fp16,-avx512ifma,-avx512pf,-avx512vbmi,-avx512vbmi2,-avx512vl,-avx512vnni,-avx512vp2intersect,-avx512vpopcntdq,-avxifma,-avxneconvert,-avxvnni,-avxvnniint8,-f16c,-fma,-fma4,-sha512,-sm3,-sm4,-sse4.1,-sse4.2,-vaes,-vpclmulqdq,-xop" "tune-cpu"="i686"
 // CHECK: #5 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cmov,+crc32,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt,-aes,-vaes"
 // CHECK-NOT: tune-cpu
 // CHECK: #6 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87,-3dnow,-3dnowa,-mmx"
 // CHECK: #7 = {{.*}}"target-cpu"="lakemont" "target-features"="+cx8,+mmx"
 // CHECK-NOT: tune-cpu
 // CHECK: #8 = {{.*}}"target-cpu"="i686" "target-features"="+cmov,+cx8,+x87" "tune-cpu"="sandybridge"
 
 // CHECK: "target-cpu"="x86-64-v2"
 // CHECK-SAME: "target-features"="+cmov,+crc32,+cx16,+cx8,+fxsr,+mmx,+popcnt,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87"
 // CHECK: "target-cpu"="x86-64-v3"
 // CHECK-SAME: "target-features"="+avx,+avx2,+bmi,+bmi2,+cmov,+crc32,+cx16,+cx8,+f16c,+fma,+fxsr,+lzcnt,+mmx,+movbe,+popcnt,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave"
 // CHECK: "target-cpu"="x86-64-v4"
 // CHECK-SAME: "target-features"="+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+bmi,+bmi2,+cmov,+crc32,+cx16,+cx8,+f16c,+fma,+fxsr,+lzcnt,+mmx,+movbe,+popcnt,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave"

clang/test/Driver/x86-target-features.c

 // SHA512: "-target-feature" "+sha512"
 // NO-SHA512: "-target-feature" "-sha512"
 
 // RUN: %clang --target=i386 -msm3 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=SM3 %s
 // RUN: %clang --target=i386 -mno-sm3 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-SM3 %s
 // SM3: "-target-feature" "+sm3"
 // NO-SM3: "-target-feature" "-sm3"
 
+// RUN: %clang --target=i386 -msm4 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=SM4 %s
+// RUN: %clang --target=i386 -mno-sm4 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-SM4 %s
+// SM4: "-target-feature" "+sm4"
+// NO-SM4: "-target-feature" "-sm4"
+
 // RUN: %clang --target=i386 -march=i386 -mcrc32 %s -### 2>&1 | FileCheck -check-prefix=CRC32 %s
 // RUN: %clang --target=i386 -march=i386 -mno-crc32 %s -### 2>&1 | FileCheck -check-prefix=NO-CRC32 %s
 // CRC32: "-target-feature" "+crc32"
 // NO-CRC32: "-target-feature" "-crc32"
 
 // RUN: %clang --target=i386 -march=i386 -mharden-sls=return %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=SLS-RET,NO-SLS %s
 // RUN: %clang --target=i386 -march=i386 -mharden-sls=indirect-jmp %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=SLS-IJMP,NO-SLS %s
 // RUN: %clang --target=i386 -march=i386 -mharden-sls=none -mharden-sls=all %s -### -o %t.o 2>&1 | FileCheck -check-prefixes=SLS-IJMP,SLS-RET %s

clang/test/Preprocessor/x86_target_features.c

 
 // NOSM3-NOT: #define __SM3__ 1
 
 // RUN: %clang -target i686-unknown-linux-gnu -march=atom -msm3 -mno-avx -x c -E -dM -o - %s | FileCheck  -check-prefix=SM3NOAVX %s
 
 // SM3NOAVX-NOT: #define __SM3__ 1
 // SM3NOAVX-NOT: #define __AVX__ 1
 
+// RUN: %clang -target i686-unknown-linux-gnu -march=atom -msm4 -x c -E -dM -o - %s | FileCheck  -check-prefix=SM4 %s
+
+// SM4: #define __AVX__ 1
+// SM4: #define __SM4__ 1
+
+// RUN: %clang -target i686-unknown-linux-gnu -march=atom -mno-sm4 -x c -E -dM -o - %s | FileCheck  -check-prefix=NOSM4 %s
+// NOSM4-NOT: #define __SM4__ 1
+
+// RUN: %clang -target i686-unknown-linux-gnu -march=atom -msm4 -mno-avx -x c -E -dM -o - %s | FileCheck  -check-prefix=SM4NOAVX %s
+
+// SM4NOAVX-NOT: #define __AVX__ 1
+// SM4NOAVX-NOT: #define __SM4__ 1
+
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mcrc32 -x c -E -dM -o - %s | FileCheck -check-prefix=CRC32 %s
 
 // CRC32: #define __CRC32__ 1
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-crc32 -x c -E -dM -o - %s | FileCheck -check-prefix=NOCRC32 %s
 
 // NOCRC32-NOT: #define __CRC32__ 1
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mrdpru -x c -E -dM -o - %s | FileCheck -check-prefix=RDPRU %s
 
 // RDPRU: #define __RDPRU__ 1
 
 // RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-rdpru -x c -E -dM -o - %s | FileCheck -check-prefix=NORDPRU %s
 
 // NORDPRU-NOT: #define __RDPRU__ 1

llvm/docs/ReleaseNotes.rst

 Changes to the X86 Backend
 --------------------------
 
 * ``__builtin_unpredictable`` (unpredictable metadata in LLVM IR), is handled by X86 Backend.
   ``X86CmovConversion`` pass now respects this builtin and does not convert CMOVs to branches.
 * Add support for the ``PBNDKB`` instruction.
 * Support ISA of ``SHA512``.
 * Support ISA of ``SM3``.
+* Support ISA of ``SM4``.
 
 Changes to the OCaml bindings
 -----------------------------
 
 Changes to the Python bindings
 ------------------------------
 
 * The python bindings have been removed.

llvm/include/llvm/IR/IntrinsicsX86.td

def int_x86_vsm3msg2
         [IntrNoMem]>;
   def int_x86_vsm3rnds2
       : ClangBuiltin<"__builtin_ia32_vsm3rnds2">,
         DefaultAttrsIntrinsic<[llvm_v4i32_ty],
         [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty],
         [ImmArg<ArgIndex<3>>, IntrNoMem]>;
 }
 //===----------------------------------------------------------------------===//
+// SM4 intrinsics
+let TargetPrefix = "x86" in {
+  def int_x86_vsm4key4128
+      : ClangBuiltin<"__builtin_ia32_vsm4key4128">,
+        DefaultAttrsIntrinsic<[llvm_v4i32_ty],
+        [llvm_v4i32_ty, llvm_v4i32_ty],
+        [IntrNoMem]>;
+  def int_x86_vsm4key4256
+      : ClangBuiltin<"__builtin_ia32_vsm4key4256">,
+        DefaultAttrsIntrinsic<[llvm_v8i32_ty],
+        [llvm_v8i32_ty, llvm_v8i32_ty],
+        [IntrNoMem]>;
+  def int_x86_vsm4rnds4128
+      : ClangBuiltin<"__builtin_ia32_vsm4rnds4128">,
+        DefaultAttrsIntrinsic<[llvm_v4i32_ty],
+        [llvm_v4i32_ty, llvm_v4i32_ty],
+        [IntrNoMem]>;
+  def int_x86_vsm4rnds4256
+      : ClangBuiltin<"__builtin_ia32_vsm4rnds4256">,
+        DefaultAttrsIntrinsic<[llvm_v8i32_ty],
+        [llvm_v8i32_ty, llvm_v8i32_ty],
+        [IntrNoMem]>;
+}
+//===----------------------------------------------------------------------===//
 // RAO-INT intrinsics
 let TargetPrefix = "x86" in {
   def int_x86_aadd32
       : ClangBuiltin<"__builtin_ia32_aadd32">,
         Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [IntrArgMemOnly]>;
   def int_x86_aadd64
       : ClangBuiltin<"__builtin_ia32_aadd64">,
         Intrinsic<[], [llvm_ptr_ty, llvm_i64_ty], [IntrArgMemOnly]>;

llvm/include/llvm/TargetParser/X86TargetParser.def

 X86_FEATURE       (X87,             "x87")
 X86_FEATURE       (XSAVE,           "xsave")
 X86_FEATURE       (XSAVEC,          "xsavec")
 X86_FEATURE       (XSAVEOPT,        "xsaveopt")
 X86_FEATURE       (XSAVES,          "xsaves")
 X86_FEATURE       (HRESET,          "hreset")
 X86_FEATURE       (RAOINT,          "raoint")
 X86_FEATURE       (AVX512FP16,      "avx512fp16")
-X86_FEATURE       (SM3,             "sm3")
 X86_FEATURE       (AMX_FP16,        "amx-fp16")
 X86_FEATURE       (CMPCCXADD,       "cmpccxadd")
 X86_FEATURE       (AVXNECONVERT,    "avxneconvert")
 X86_FEATURE       (AVXVNNI,         "avxvnni")
 X86_FEATURE       (AVXIFMA,         "avxifma")
 X86_FEATURE       (AVXVNNIINT8,     "avxvnniint8")
 X86_FEATURE       (SHA512,          "sha512")
+X86_FEATURE       (SM3,             "sm3")
+X86_FEATURE       (SM4,             "sm4")
 // These features aren't really CPU features, but the frontend can set them.
 X86_FEATURE       (RETPOLINE_EXTERNAL_THUNK,    "retpoline-external-thunk")
 X86_FEATURE       (RETPOLINE_INDIRECT_BRANCHES, "retpoline-indirect-branches")
 X86_FEATURE       (RETPOLINE_INDIRECT_CALLS,    "retpoline-indirect-calls")
 X86_FEATURE       (LVI_CFI,                     "lvi-cfi")
 X86_FEATURE       (LVI_LOAD_HARDENING,          "lvi-load-hardening")
 #undef X86_FEATURE_COMPAT
 #undef X86_FEATURE

llvm/lib/Target/X86/X86.td

def FeatureSHA512  : SubtargetFeature<"sha512", "HasSHA512", "true",
                                       [FeatureAVX]>;
 // Processor supports CET SHSTK - Control-Flow Enforcement Technology
 // using Shadow Stack
 def FeatureSHSTK   : SubtargetFeature<"shstk", "HasSHSTK", "true",
                        "Support CET Shadow-Stack instructions">;
 def FeatureSM3     : SubtargetFeature<"sm3", "HasSM3", "true",
                                       "Support SM3 instructions",
                                       [FeatureAVX]>;
+def FeatureSM4     : SubtargetFeature<"sm4", "HasSM4", "true",
+                                      "Support SM4 instructions",
+                                      [FeatureAVX]>;
 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
                                       "Support PRFCHW instructions">;
 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
                                       "Support RDSEED instruction">;
 def FeatureLAHFSAHF64 : SubtargetFeature<"sahf", "HasLAHFSAHF64", "true",
                            "Support LAHF and SAHF instructions in 64-bit mode">;
 def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
                                       "Enable MONITORX/MWAITX timer functionality">;

llvm/lib/Target/X86/X86InstrInfo.td

 def HasCLZERO    : Predicate<"Subtarget->hasCLZERO()">;
 def HasCLDEMOTE  : Predicate<"Subtarget->hasCLDEMOTE()">;
 def HasMOVDIRI   : Predicate<"Subtarget->hasMOVDIRI()">;
 def HasMOVDIR64B : Predicate<"Subtarget->hasMOVDIR64B()">;
 def HasPTWRITE   : Predicate<"Subtarget->hasPTWRITE()">;
 def FPStackf32   : Predicate<"!Subtarget->hasSSE1()">;
 def FPStackf64   : Predicate<"!Subtarget->hasSSE2()">;
 def HasSHSTK     : Predicate<"Subtarget->hasSHSTK()">;
+def HasSM4       : Predicate<"Subtarget->hasSM4()">;
 def HasCLFLUSH   : Predicate<"Subtarget->hasCLFLUSH()">;
 def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">;
 def HasCLWB      : Predicate<"Subtarget->hasCLWB()">;
 def HasWBNOINVD  : Predicate<"Subtarget->hasWBNOINVD()">;
 def HasRDPID     : Predicate<"Subtarget->hasRDPID()">;
 def HasRDPRU     : Predicate<"Subtarget->hasRDPRU()">;
 def HasWAITPKG   : Predicate<"Subtarget->hasWAITPKG()">;
 def HasINVPCID   : Predicate<"Subtarget->hasINVPCID()">;

llvm/lib/Target/X86/X86InstrSSE.td

 let Predicates = [HasSHA512], Constraints = "$src1 = $dst" in {
 def VSHA512MSG1rr : I<0xcc, MRMSrcReg, (outs VR256:$dst),
                      (ins VR256:$src1, VR128:$src2),
                      "vsha512msg1\t{$src2, $dst|$dst, $src2}",
                      [(set VR256:$dst,
                        (int_x86_vsha512msg1 VR256:$src1, VR128:$src2))]>, VEX_L,
                      VEX, T8XD, Sched<[WriteVecIMul]>;
 def VSHA512MSG2rr : I<0xcd, MRMSrcReg, (outs VR256:$dst),
                      (ins VR256:$src1, VR256:$src2),
                      "vsha512msg2\t{$src2, $dst|$dst, $src2}",
                      [(set VR256:$dst,
                        (int_x86_vsha512msg2 VR256:$src1, VR256:$src2))]>, VEX_L,
                      VEX, T8XD, Sched<[WriteVecIMul]>;
 def VSHA512RNDS2rr : I<0xcb, MRMSrcReg, (outs VR256:$dst),
                       (ins VR256:$src1, VR256:$src2, VR128:$src3),
                       "vsha512rnds2\t{$src3, $src2, $dst|$dst, $src2, $src3}",
                       [(set VR256:$dst,
def rm : Ii8<0xde, MRMSrcMem, (outs VR128:$dst),
                 VR128:$src2, (loadv4i32 addr:$src3), timm:$src4))]>,
               Sched<[WriteVecIMul]>;
   }
 }
 
 defm VSM3MSG1 : SM3_Base<"vsm3msg1">, T8PS;
 defm VSM3MSG2 : SM3_Base<"vsm3msg2">, T8PD;
 defm VSM3RNDS2 : VSM3RNDS2_Base, VEX_4V, TAPD;
+
+// FIXME: Is there a better scheduler class for SM4 than WriteVecIMul?
+let Predicates = [HasSM4] in {
+  multiclass SM4_Base<string OpStr, RegisterClass RC, string VL,
+                      PatFrag LD, X86MemOperand MemOp> {
+    def rr : I<0xda, MRMSrcReg, (outs RC:$dst),
+               (ins RC:$src1, RC:$src2),
+               !strconcat(OpStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+               [(set RC:$dst, (!cast<Intrinsic>("int_x86_"#OpStr#VL) RC:$src1,
+                  RC:$src2))]>,
+               Sched<[WriteVecIMul]>;
+    def rm : I<0xda, MRMSrcMem, (outs RC:$dst),
+               (ins RC:$src1, MemOp:$src2),
+               !strconcat(OpStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
+               [(set RC:$dst, (!cast<Intrinsic>("int_x86_"#OpStr#VL) RC:$src1,
+                 (LD addr:$src2)))]>,
+               Sched<[WriteVecIMul]>;
+  }
+}
+
+defm VSM4KEY4  : SM4_Base<"vsm4key4", VR128, "128", loadv4i32, i128mem>, T8XS, VEX_4V;
+defm VSM4KEY4Y : SM4_Base<"vsm4key4", VR256, "256", loadv8i32, i256mem>, T8XS, VEX_L, VEX_4V;
+defm VSM4RNDS4  : SM4_Base<"vsm4rnds4", VR128, "128", loadv4i32, i128mem>, T8XD, VEX_4V;
+defm VSM4RNDS4Y : SM4_Base<"vsm4rnds4", VR256, "256", loadv8i32, i256mem>, T8XD, VEX_L, VEX_4V;

llvm/lib/TargetParser/Host.cpp

#endif
   Features["amx-bf16"]   = HasLeaf7 && ((EDX >> 22) & 1) && HasAMXSave;
   Features["avx512fp16"] = HasLeaf7 && ((EDX >> 23) & 1) && HasAVX512Save;
   Features["amx-tile"]   = HasLeaf7 && ((EDX >> 24) & 1) && HasAMXSave;
   Features["amx-int8"]   = HasLeaf7 && ((EDX >> 25) & 1) && HasAMXSave;
   bool HasLeaf7Subleaf1 =
       MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
   Features["sha512"]     = HasLeaf7Subleaf1 && ((EAX >> 0) & 1);
   Features["sm3"]        = HasLeaf7Subleaf1 && ((EAX >> 1) & 1);
+  Features["sm4"]        = HasLeaf7Subleaf1 && ((EAX >> 2) & 1);
   Features["raoint"]     = HasLeaf7Subleaf1 && ((EAX >> 3) & 1);
   Features["avxvnni"]    = HasLeaf7Subleaf1 && ((EAX >> 4) & 1) && HasAVXSave;
   Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
   Features["amx-fp16"]   = HasLeaf7Subleaf1 && ((EAX >> 21) & 1) && HasAMXSave;
   Features["cmpccxadd"]  = HasLeaf7Subleaf1 && ((EAX >> 7) & 1);
   Features["hreset"]     = HasLeaf7Subleaf1 && ((EAX >> 22) & 1);
   Features["avxifma"]    = HasLeaf7Subleaf1 && ((EAX >> 23) & 1) && HasAVXSave;
   Features["avxvnniint8"] = HasLeaf7Subleaf1 && ((EDX >> 4) & 1) && HasAVXSave;

llvm/lib/TargetParser/X86TargetParser.cpp

 constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX;
 constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX;
 constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2;
 constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2;
 constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2;
 constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX;
 constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL;
 constexpr FeatureBitset ImpliedFeaturesSM3 = FeatureAVX;
+constexpr FeatureBitset ImpliedFeaturesSM4 = FeatureAVX;
 
 // AVX512 features.
 constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F;
 constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F;
 constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F;
 constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F;
 constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F;
 constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F;

llvm/test/CodeGen/X86/sm4-intrinsics.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+sm4 | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=i686-unknown-unknown --show-mc-encoding -mattr=+sm4 | FileCheck %s
+
+define <4 x i32> @test_int_x86_vsm4key4128(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: test_int_x86_vsm4key4128:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsm4key4 %xmm1, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x7a,0xda,0xc1]
+; CHECK-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i32> @llvm.x86.vsm4key4128(<4 x i32> %A, <4 x i32> %B)
+  ret <4 x i32> %ret
+}
+declare <4 x i32> @llvm.x86.vsm4key4128(<4 x i32> %A, <4 x i32> %B)
+
+define <8 x i32> @test_int_x86_vsm4key4256(<8 x i32> %A, <8 x i32> %B) {
+; CHECK-LABEL: test_int_x86_vsm4key4256:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsm4key4 %ymm1, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7e,0xda,0xc1]
+; CHECK-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <8 x i32> @llvm.x86.vsm4key4256(<8 x i32> %A, <8 x i32> %B)
+  ret <8 x i32> %ret
+}
+declare <8 x i32> @llvm.x86.vsm4key4256(<8 x i32> %A, <8 x i32> %B)
+
+define <4 x i32> @test_int_x86_vsm4rnds4128(<4 x i32> %A, <4 x i32> %B) {
+; CHECK-LABEL: test_int_x86_vsm4rnds4128:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsm4rnds4 %xmm1, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x7b,0xda,0xc1]
+; CHECK-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <4 x i32> @llvm.x86.vsm4rnds4128(<4 x i32> %A, <4 x i32> %B)
+  ret <4 x i32> %ret
+}
+declare <4 x i32> @llvm.x86.vsm4rnds4128(<4 x i32> %A, <4 x i32> %B)
+
+define <8 x i32> @test_int_x86_vsm4rnds4256(<8 x i32> %A, <8 x i32> %B) {
+; CHECK-LABEL: test_int_x86_vsm4rnds4256:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsm4rnds4 %ymm1, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7f,0xda,0xc1]
+; CHECK-NEXT:    ret{{[l|q]}} # encoding: [0xc3]
+  %ret = call <8 x i32> @llvm.x86.vsm4rnds4256(<8 x i32> %A, <8 x i32> %B)
+  ret <8 x i32> %ret
+}
+declare <8 x i32> @llvm.x86.vsm4rnds4256(<8 x i32> %A, <8 x i32> %B)

llvm/test/MC/Disassembler/X86/sm4-32.txt

+# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=i386-unknown-unknown --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:        vsm4key4 %ymm4, %ymm3, %ymm2
+# INTEL:      vsm4key4 ymm2, ymm3, ymm4
+0xc4,0xe2,0x66,0xda,0xd4
+
+# ATT:        vsm4key4 %xmm4, %xmm3, %xmm2
+# INTEL:      vsm4key4 xmm2, xmm3, xmm4
+0xc4,0xe2,0x62,0xda,0xd4
+
+# ATT:        vsm4key4  268435456(%esp,%esi,8), %ymm3, %ymm2
+# INTEL:      vsm4key4 ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456]
+0xc4,0xe2,0x66,0xda,0x94,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        vsm4key4  291(%edi,%eax,4), %ymm3, %ymm2
+# INTEL:      vsm4key4 ymm2, ymm3, ymmword ptr [edi + 4*eax + 291]
+0xc4,0xe2,0x66,0xda,0x94,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        vsm4key4  (%eax), %ymm3, %ymm2
+# INTEL:      vsm4key4 ymm2, ymm3, ymmword ptr [eax]
+0xc4,0xe2,0x66,0xda,0x10
+
+# ATT:        vsm4key4  -1024(,%ebp,2), %ymm3, %ymm2
+# INTEL:      vsm4key4 ymm2, ymm3, ymmword ptr [2*ebp - 1024]
+0xc4,0xe2,0x66,0xda,0x14,0x6d,0x00,0xfc,0xff,0xff
+
+# ATT:        vsm4key4  4064(%ecx), %ymm3, %ymm2
+# INTEL:      vsm4key4 ymm2, ymm3, ymmword ptr [ecx + 4064]
+0xc4,0xe2,0x66,0xda,0x91,0xe0,0x0f,0x00,0x00
+
+# ATT:        vsm4key4  -4096(%edx), %ymm3, %ymm2
+# INTEL:      vsm4key4 ymm2, ymm3, ymmword ptr [edx - 4096]
+0xc4,0xe2,0x66,0xda,0x92,0x00,0xf0,0xff,0xff
+
+# ATT:        vsm4key4  268435456(%esp,%esi,8), %xmm3, %xmm2
+# INTEL:      vsm4key4 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+0xc4,0xe2,0x62,0xda,0x94,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        vsm4key4  291(%edi,%eax,4), %xmm3, %xmm2
+# INTEL:      vsm4key4 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+0xc4,0xe2,0x62,0xda,0x94,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        vsm4key4  (%eax), %xmm3, %xmm2
+# INTEL:      vsm4key4 xmm2, xmm3, xmmword ptr [eax]
+0xc4,0xe2,0x62,0xda,0x10
+
+# ATT:        vsm4key4  -512(,%ebp,2), %xmm3, %xmm2
+# INTEL:      vsm4key4 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+0xc4,0xe2,0x62,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        vsm4key4  2032(%ecx), %xmm3, %xmm2
+# INTEL:      vsm4key4 xmm2, xmm3, xmmword ptr [ecx + 2032]
+0xc4,0xe2,0x62,0xda,0x91,0xf0,0x07,0x00,0x00
+
+# ATT:        vsm4key4  -2048(%edx), %xmm3, %xmm2
+# INTEL:      vsm4key4 xmm2, xmm3, xmmword ptr [edx - 2048]
+0xc4,0xe2,0x62,0xda,0x92,0x00,0xf8,0xff,0xff
+
+# ATT:        vsm4rnds4 %ymm4, %ymm3, %ymm2
+# INTEL:      vsm4rnds4 ymm2, ymm3, ymm4
+0xc4,0xe2,0x67,0xda,0xd4
+
+# ATT:        vsm4rnds4 %xmm4, %xmm3, %xmm2
+# INTEL:      vsm4rnds4 xmm2, xmm3, xmm4
+0xc4,0xe2,0x63,0xda,0xd4
+
+# ATT:        vsm4rnds4  268435456(%esp,%esi,8), %ymm3, %ymm2
+# INTEL:      vsm4rnds4 ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456]
+0xc4,0xe2,0x67,0xda,0x94,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        vsm4rnds4  291(%edi,%eax,4), %ymm3, %ymm2
+# INTEL:      vsm4rnds4 ymm2, ymm3, ymmword ptr [edi + 4*eax + 291]
+0xc4,0xe2,0x67,0xda,0x94,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        vsm4rnds4  (%eax), %ymm3, %ymm2
+# INTEL:      vsm4rnds4 ymm2, ymm3, ymmword ptr [eax]
+0xc4,0xe2,0x67,0xda,0x10
+
+# ATT:        vsm4rnds4  -1024(,%ebp,2), %ymm3, %ymm2
+# INTEL:      vsm4rnds4 ymm2, ymm3, ymmword ptr [2*ebp - 1024]
+0xc4,0xe2,0x67,0xda,0x14,0x6d,0x00,0xfc,0xff,0xff
+
+# ATT:        vsm4rnds4  4064(%ecx), %ymm3, %ymm2
+# INTEL:      vsm4rnds4 ymm2, ymm3, ymmword ptr [ecx + 4064]
+0xc4,0xe2,0x67,0xda,0x91,0xe0,0x0f,0x00,0x00
+
+# ATT:        vsm4rnds4  -4096(%edx), %ymm3, %ymm2
+# INTEL:      vsm4rnds4 ymm2, ymm3, ymmword ptr [edx - 4096]
+0xc4,0xe2,0x67,0xda,0x92,0x00,0xf0,0xff,0xff
+
+# ATT:        vsm4rnds4  268435456(%esp,%esi,8), %xmm3, %xmm2
+# INTEL:      vsm4rnds4 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+0xc4,0xe2,0x63,0xda,0x94,0xf4,0x00,0x00,0x00,0x10
+
+# ATT:        vsm4rnds4  291(%edi,%eax,4), %xmm3, %xmm2
+# INTEL:      vsm4rnds4 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+0xc4,0xe2,0x63,0xda,0x94,0x87,0x23,0x01,0x00,0x00
+
+# ATT:        vsm4rnds4  (%eax), %xmm3, %xmm2
+# INTEL:      vsm4rnds4 xmm2, xmm3, xmmword ptr [eax]
+0xc4,0xe2,0x63,0xda,0x10
+
+# ATT:        vsm4rnds4  -512(,%ebp,2), %xmm3, %xmm2
+# INTEL:      vsm4rnds4 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+0xc4,0xe2,0x63,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:        vsm4rnds4  2032(%ecx), %xmm3, %xmm2
+# INTEL:      vsm4rnds4 xmm2, xmm3, xmmword ptr [ecx + 2032]
+0xc4,0xe2,0x63,0xda,0x91,0xf0,0x07,0x00,0x00
+
+# ATT:        vsm4rnds4  -2048(%edx), %xmm3, %xmm2
+# INTEL:      vsm4rnds4 xmm2, xmm3, xmmword ptr [edx - 2048]
+0xc4,0xe2,0x63,0xda,0x92,0x00,0xf8,0xff,0xff

llvm/test/MC/Disassembler/X86/sm4-64.txt

+# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
+# RUN: llvm-mc --disassemble %s -triple=x86_64 --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
+
+# ATT:   vsm4key4 %ymm4, %ymm13, %ymm12
+# INTEL: vsm4key4 ymm12, ymm13, ymm4
+0xc4,0x62,0x16,0xda,0xe4
+
+# ATT:   vsm4key4 %xmm4, %xmm13, %xmm12
+# INTEL: vsm4key4 xmm12, xmm13, xmm4
+0xc4,0x62,0x12,0xda,0xe4
+
+# ATT:   vsm4key4  268435456(%rbp,%r14,8), %ymm13, %ymm12
+# INTEL: vsm4key4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+0xc4,0x22,0x16,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10
+
+# ATT:   vsm4key4  291(%r8,%rax,4), %ymm13, %ymm12
+# INTEL: vsm4key4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+0xc4,0x42,0x16,0xda,0xa4,0x80,0x23,0x01,0x00,0x00
+
+# ATT:   vsm4key4  (%rip), %ymm13, %ymm12
+# INTEL: vsm4key4 ymm12, ymm13, ymmword ptr [rip]
+0xc4,0x62,0x16,0xda,0x25,0x00,0x00,0x00,0x00
+
+# ATT:   vsm4key4  -1024(,%rbp,2), %ymm13, %ymm12
+# INTEL: vsm4key4 ymm12, ymm13, ymmword ptr [2*rbp - 1024]
+0xc4,0x62,0x16,0xda,0x24,0x6d,0x00,0xfc,0xff,0xff
+
+# ATT:   vsm4key4  4064(%rcx), %ymm13, %ymm12
+# INTEL: vsm4key4 ymm12, ymm13, ymmword ptr [rcx + 4064]
+0xc4,0x62,0x16,0xda,0xa1,0xe0,0x0f,0x00,0x00
+
+# ATT:   vsm4key4  -4096(%rdx), %ymm13, %ymm12
+# INTEL: vsm4key4 ymm12, ymm13, ymmword ptr [rdx - 4096]
+0xc4,0x62,0x16,0xda,0xa2,0x00,0xf0,0xff,0xff
+
+# ATT:   vsm4key4  268435456(%rbp,%r14,8), %xmm13, %xmm12
+# INTEL: vsm4key4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+0xc4,0x22,0x12,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10
+
+# ATT:   vsm4key4  291(%r8,%rax,4), %xmm13, %xmm12
+# INTEL: vsm4key4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+0xc4,0x42,0x12,0xda,0xa4,0x80,0x23,0x01,0x00,0x00
+
+# ATT:   vsm4key4  (%rip), %xmm13, %xmm12
+# INTEL: vsm4key4 xmm12, xmm13, xmmword ptr [rip]
+0xc4,0x62,0x12,0xda,0x25,0x00,0x00,0x00,0x00
+
+# ATT:   vsm4key4  -512(,%rbp,2), %xmm13, %xmm12
+# INTEL: vsm4key4 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+0xc4,0x62,0x12,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:   vsm4key4  2032(%rcx), %xmm13, %xmm12
+# INTEL: vsm4key4 xmm12, xmm13, xmmword ptr [rcx + 2032]
+0xc4,0x62,0x12,0xda,0xa1,0xf0,0x07,0x00,0x00
+
+# ATT:   vsm4key4  -2048(%rdx), %xmm13, %xmm12
+# INTEL: vsm4key4 xmm12, xmm13, xmmword ptr [rdx - 2048]
+0xc4,0x62,0x12,0xda,0xa2,0x00,0xf8,0xff,0xff
+
+# ATT:   vsm4rnds4 %ymm4, %ymm13, %ymm12
+# INTEL: vsm4rnds4 ymm12, ymm13, ymm4
+0xc4,0x62,0x17,0xda,0xe4
+
+# ATT:   vsm4rnds4 %xmm4, %xmm13, %xmm12
+# INTEL: vsm4rnds4 xmm12, xmm13, xmm4
+0xc4,0x62,0x13,0xda,0xe4
+
+# ATT:   vsm4rnds4  268435456(%rbp,%r14,8), %ymm13, %ymm12
+# INTEL: vsm4rnds4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+0xc4,0x22,0x17,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10
+
+# ATT:   vsm4rnds4  291(%r8,%rax,4), %ymm13, %ymm12
+# INTEL: vsm4rnds4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+0xc4,0x42,0x17,0xda,0xa4,0x80,0x23,0x01,0x00,0x00
+
+# ATT:   vsm4rnds4  (%rip), %ymm13, %ymm12
+# INTEL: vsm4rnds4 ymm12, ymm13, ymmword ptr [rip]
+0xc4,0x62,0x17,0xda,0x25,0x00,0x00,0x00,0x00
+
+# ATT:   vsm4rnds4  -1024(,%rbp,2), %ymm13, %ymm12
+# INTEL: vsm4rnds4 ymm12, ymm13, ymmword ptr [2*rbp - 1024]
+0xc4,0x62,0x17,0xda,0x24,0x6d,0x00,0xfc,0xff,0xff
+
+# ATT:   vsm4rnds4  4064(%rcx), %ymm13, %ymm12
+# INTEL: vsm4rnds4 ymm12, ymm13, ymmword ptr [rcx + 4064]
+0xc4,0x62,0x17,0xda,0xa1,0xe0,0x0f,0x00,0x00
+
+# ATT:   vsm4rnds4  -4096(%rdx), %ymm13, %ymm12
+# INTEL: vsm4rnds4 ymm12, ymm13, ymmword ptr [rdx - 4096]
+0xc4,0x62,0x17,0xda,0xa2,0x00,0xf0,0xff,0xff
+
+# ATT:   vsm4rnds4  268435456(%rbp,%r14,8), %xmm13, %xmm12
+# INTEL: vsm4rnds4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+0xc4,0x22,0x13,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10
+
+# ATT:   vsm4rnds4  291(%r8,%rax,4), %xmm13, %xmm12
+# INTEL: vsm4rnds4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+0xc4,0x42,0x13,0xda,0xa4,0x80,0x23,0x01,0x00,0x00
+
+# ATT:   vsm4rnds4  (%rip), %xmm13, %xmm12
+# INTEL: vsm4rnds4 xmm12, xmm13, xmmword ptr [rip]
+0xc4,0x62,0x13,0xda,0x25,0x00,0x00,0x00,0x00
+
+# ATT:   vsm4rnds4  -512(,%rbp,2), %xmm13, %xmm12
+# INTEL: vsm4rnds4 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+0xc4,0x62,0x13,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff
+
+# ATT:   vsm4rnds4  2032(%rcx), %xmm13, %xmm12
+# INTEL: vsm4rnds4 xmm12, xmm13, xmmword ptr [rcx + 2032]
+0xc4,0x62,0x13,0xda,0xa1,0xf0,0x07,0x00,0x00
+
+# ATT:   vsm4rnds4  -2048(%rdx), %xmm13, %xmm12
+# INTEL: vsm4rnds4 xmm12, xmm13, xmmword ptr [rdx - 2048]
+0xc4,0x62,0x13,0xda,0xa2,0x00,0xf8,0xff,0xff
+

llvm/test/MC/X86/sm4-32-att.s

+// RUN: llvm-mc -triple i686-unknown-unknown --show-encoding %s | FileCheck %s
+
+// CHECK:      vsm4key4 %ymm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0xd4]
+               vsm4key4 %ymm4, %ymm3, %ymm2
+
+// CHECK:      vsm4key4 %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0xd4]
+               vsm4key4 %xmm4, %xmm3, %xmm2
+
+// CHECK:      vsm4key4  268435456(%esp,%esi,8), %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+               vsm4key4  268435456(%esp,%esi,8), %ymm3, %ymm2
+
+// CHECK:      vsm4key4  291(%edi,%eax,4), %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+               vsm4key4  291(%edi,%eax,4), %ymm3, %ymm2
+
+// CHECK:      vsm4key4  (%eax), %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x10]
+               vsm4key4  (%eax), %ymm3, %ymm2
+
+// CHECK:      vsm4key4  -1024(,%ebp,2), %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x14,0x6d,0x00,0xfc,0xff,0xff]
+               vsm4key4  -1024(,%ebp,2), %ymm3, %ymm2
+
+// CHECK:      vsm4key4  4064(%ecx), %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x91,0xe0,0x0f,0x00,0x00]
+               vsm4key4  4064(%ecx), %ymm3, %ymm2
+
+// CHECK:      vsm4key4  -4096(%edx), %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x92,0x00,0xf0,0xff,0xff]
+               vsm4key4  -4096(%edx), %ymm3, %ymm2
+
+// CHECK:      vsm4key4  268435456(%esp,%esi,8), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+               vsm4key4  268435456(%esp,%esi,8), %xmm3, %xmm2
+
+// CHECK:      vsm4key4  291(%edi,%eax,4), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+               vsm4key4  291(%edi,%eax,4), %xmm3, %xmm2
+
+// CHECK:      vsm4key4  (%eax), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x10]
+               vsm4key4  (%eax), %xmm3, %xmm2
+
+// CHECK:      vsm4key4  -512(,%ebp,2), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+               vsm4key4  -512(,%ebp,2), %xmm3, %xmm2
+
+// CHECK:      vsm4key4  2032(%ecx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x91,0xf0,0x07,0x00,0x00]
+               vsm4key4  2032(%ecx), %xmm3, %xmm2
+
+// CHECK:      vsm4key4  -2048(%edx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x92,0x00,0xf8,0xff,0xff]
+               vsm4key4  -2048(%edx), %xmm3, %xmm2
+
+// CHECK:      vsm4rnds4 %ymm4, %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0xd4]
+               vsm4rnds4 %ymm4, %ymm3, %ymm2
+
+// CHECK:      vsm4rnds4 %xmm4, %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0xd4]
+               vsm4rnds4 %xmm4, %xmm3, %xmm2
+
+// CHECK:      vsm4rnds4  268435456(%esp,%esi,8), %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+               vsm4rnds4  268435456(%esp,%esi,8), %ymm3, %ymm2
+
+// CHECK:      vsm4rnds4  291(%edi,%eax,4), %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+               vsm4rnds4  291(%edi,%eax,4), %ymm3, %ymm2
+
+// CHECK:      vsm4rnds4  (%eax), %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x10]
+               vsm4rnds4  (%eax), %ymm3, %ymm2
+
+// CHECK:      vsm4rnds4  -1024(,%ebp,2), %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x14,0x6d,0x00,0xfc,0xff,0xff]
+               vsm4rnds4  -1024(,%ebp,2), %ymm3, %ymm2
+
+// CHECK:      vsm4rnds4  4064(%ecx), %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x91,0xe0,0x0f,0x00,0x00]
+               vsm4rnds4  4064(%ecx), %ymm3, %ymm2
+
+// CHECK:      vsm4rnds4  -4096(%edx), %ymm3, %ymm2
+// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x92,0x00,0xf0,0xff,0xff]
+               vsm4rnds4  -4096(%edx), %ymm3, %ymm2
+
+// CHECK:      vsm4rnds4  268435456(%esp,%esi,8), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+               vsm4rnds4  268435456(%esp,%esi,8), %xmm3, %xmm2
+
+// CHECK:      vsm4rnds4  291(%edi,%eax,4), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+               vsm4rnds4  291(%edi,%eax,4), %xmm3, %xmm2
+
+// CHECK:      vsm4rnds4  (%eax), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x10]
+               vsm4rnds4  (%eax), %xmm3, %xmm2
+
+// CHECK:      vsm4rnds4  -512(,%ebp,2), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+               vsm4rnds4  -512(,%ebp,2), %xmm3, %xmm2
+
+// CHECK:      vsm4rnds4  2032(%ecx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x91,0xf0,0x07,0x00,0x00]
+               vsm4rnds4  2032(%ecx), %xmm3, %xmm2
+
+// CHECK:      vsm4rnds4  -2048(%edx), %xmm3, %xmm2
+// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x92,0x00,0xf8,0xff,0xff]
+               vsm4rnds4  -2048(%edx), %xmm3, %xmm2
+

llvm/test/MC/X86/sm4-32-intel.s

+// RUN: llvm-mc -triple i686-unknown-unknown -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:      vsm4key4 ymm2, ymm3, ymm4
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0xd4]
+               vsm4key4 ymm2, ymm3, ymm4
+
+// CHECK:      vsm4key4 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0xd4]
+               vsm4key4 xmm2, xmm3, xmm4
+
+// CHECK:      vsm4key4 ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456]
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+               vsm4key4 ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456]
+
+// CHECK:      vsm4key4 ymm2, ymm3, ymmword ptr [edi + 4*eax + 291]
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+               vsm4key4 ymm2, ymm3, ymmword ptr [edi + 4*eax + 291]
+
+// CHECK:      vsm4key4 ymm2, ymm3, ymmword ptr [eax]
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x10]
+               vsm4key4 ymm2, ymm3, ymmword ptr [eax]
+
+// CHECK:      vsm4key4 ymm2, ymm3, ymmword ptr [2*ebp - 1024]
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x14,0x6d,0x00,0xfc,0xff,0xff]
+               vsm4key4 ymm2, ymm3, ymmword ptr [2*ebp - 1024]
+
+// CHECK:      vsm4key4 ymm2, ymm3, ymmword ptr [ecx + 4064]
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x91,0xe0,0x0f,0x00,0x00]
+               vsm4key4 ymm2, ymm3, ymmword ptr [ecx + 4064]
+
+// CHECK:      vsm4key4 ymm2, ymm3, ymmword ptr [edx - 4096]
+// CHECK: encoding: [0xc4,0xe2,0x66,0xda,0x92,0x00,0xf0,0xff,0xff]
+               vsm4key4 ymm2, ymm3, ymmword ptr [edx - 4096]
+
+// CHECK:      vsm4key4 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+               vsm4key4 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+
+// CHECK:      vsm4key4 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+               vsm4key4 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+
+// CHECK:      vsm4key4 xmm2, xmm3, xmmword ptr [eax]
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x10]
+               vsm4key4 xmm2, xmm3, xmmword ptr [eax]
+
+// CHECK:      vsm4key4 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+               vsm4key4 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+
+// CHECK:      vsm4key4 xmm2, xmm3, xmmword ptr [ecx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x91,0xf0,0x07,0x00,0x00]
+               vsm4key4 xmm2, xmm3, xmmword ptr [ecx + 2032]
+
+// CHECK:      vsm4key4 xmm2, xmm3, xmmword ptr [edx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x62,0xda,0x92,0x00,0xf8,0xff,0xff]
+               vsm4key4 xmm2, xmm3, xmmword ptr [edx - 2048]
+
+// CHECK:      vsm4rnds4 ymm2, ymm3, ymm4
+// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0xd4]
+               vsm4rnds4 ymm2, ymm3, ymm4
+
+// CHECK:      vsm4rnds4 xmm2, xmm3, xmm4
+// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0xd4]
+               vsm4rnds4 xmm2, xmm3, xmm4
+
+// CHECK:      vsm4rnds4 ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456]
+// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+               vsm4rnds4 ymm2, ymm3, ymmword ptr [esp + 8*esi + 268435456]
+
+// CHECK:      vsm4rnds4 ymm2, ymm3, ymmword ptr [edi + 4*eax + 291]
+// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+               vsm4rnds4 ymm2, ymm3, ymmword ptr [edi + 4*eax + 291]
+
+// CHECK:      vsm4rnds4 ymm2, ymm3, ymmword ptr [eax]
+// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x10]
+               vsm4rnds4 ymm2, ymm3, ymmword ptr [eax]
+
+// CHECK:      vsm4rnds4 ymm2, ymm3, ymmword ptr [2*ebp - 1024]
+// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x14,0x6d,0x00,0xfc,0xff,0xff]
+               vsm4rnds4 ymm2, ymm3, ymmword ptr [2*ebp - 1024]
+
+// CHECK:      vsm4rnds4 ymm2, ymm3, ymmword ptr [ecx + 4064]
+// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x91,0xe0,0x0f,0x00,0x00]
+               vsm4rnds4 ymm2, ymm3, ymmword ptr [ecx + 4064]
+
+// CHECK:      vsm4rnds4 ymm2, ymm3, ymmword ptr [edx - 4096]
+// CHECK: encoding: [0xc4,0xe2,0x67,0xda,0x92,0x00,0xf0,0xff,0xff]
+               vsm4rnds4 ymm2, ymm3, ymmword ptr [edx - 4096]
+
+// CHECK:      vsm4rnds4 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x94,0xf4,0x00,0x00,0x00,0x10]
+               vsm4rnds4 xmm2, xmm3, xmmword ptr [esp + 8*esi + 268435456]
+
+// CHECK:      vsm4rnds4 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x94,0x87,0x23,0x01,0x00,0x00]
+               vsm4rnds4 xmm2, xmm3, xmmword ptr [edi + 4*eax + 291]
+
+// CHECK:      vsm4rnds4 xmm2, xmm3, xmmword ptr [eax]
+// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x10]
+               vsm4rnds4 xmm2, xmm3, xmmword ptr [eax]
+
+// CHECK:      vsm4rnds4 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x14,0x6d,0x00,0xfe,0xff,0xff]
+               vsm4rnds4 xmm2, xmm3, xmmword ptr [2*ebp - 512]
+
+// CHECK:      vsm4rnds4 xmm2, xmm3, xmmword ptr [ecx + 2032]
+// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x91,0xf0,0x07,0x00,0x00]
+               vsm4rnds4 xmm2, xmm3, xmmword ptr [ecx + 2032]
+
+// CHECK:      vsm4rnds4 xmm2, xmm3, xmmword ptr [edx - 2048]
+// CHECK: encoding: [0xc4,0xe2,0x63,0xda,0x92,0x00,0xf8,0xff,0xff]
+               vsm4rnds4 xmm2, xmm3, xmmword ptr [edx - 2048]

llvm/test/MC/X86/sm4-64-att.s

+// RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm4key4 %ymm4, %ymm13, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xe4]
+          vsm4key4 %ymm4, %ymm13, %ymm12
+
+// CHECK: vsm4key4 %xmm4, %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xe4]
+          vsm4key4 %xmm4, %xmm13, %xmm12
+
+// CHECK: vsm4key4  268435456(%rbp,%r14,8), %ymm13, %ymm12
+// CHECK: encoding: [0xc4,0x22,0x16,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+          vsm4key4  268435456(%rbp,%r14,8), %ymm13, %ymm12
+
+// CHECK: vsm4key4  291(%r8,%rax,4), %ymm13, %ymm12
+// CHECK: encoding: [0xc4,0x42,0x16,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+          vsm4key4  291(%r8,%rax,4), %ymm13, %ymm12
+
+// CHECK: vsm4key4  (%rip), %ymm13, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0x25,0x00,0x00,0x00,0x00]
+          vsm4key4  (%rip), %ymm13, %ymm12
+
+// CHECK: vsm4key4  -1024(,%rbp,2), %ymm13, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0x24,0x6d,0x00,0xfc,0xff,0xff]
+          vsm4key4  -1024(,%rbp,2), %ymm13, %ymm12
+
+// CHECK: vsm4key4  4064(%rcx), %ymm13, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xa1,0xe0,0x0f,0x00,0x00]
+          vsm4key4  4064(%rcx), %ymm13, %ymm12
+
+// CHECK: vsm4key4  -4096(%rdx), %ymm13, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xa2,0x00,0xf0,0xff,0xff]
+          vsm4key4  -4096(%rdx), %ymm13, %ymm12
+
+// CHECK: vsm4key4  268435456(%rbp,%r14,8), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x22,0x12,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+          vsm4key4  268435456(%rbp,%r14,8), %xmm13, %xmm12
+
+// CHECK: vsm4key4  291(%r8,%rax,4), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x42,0x12,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+          vsm4key4  291(%r8,%rax,4), %xmm13, %xmm12
+
+// CHECK: vsm4key4  (%rip), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0x25,0x00,0x00,0x00,0x00]
+          vsm4key4  (%rip), %xmm13, %xmm12
+
+// CHECK: vsm4key4  -512(,%rbp,2), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+          vsm4key4  -512(,%rbp,2), %xmm13, %xmm12
+
+// CHECK: vsm4key4  2032(%rcx), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xa1,0xf0,0x07,0x00,0x00]
+          vsm4key4  2032(%rcx), %xmm13, %xmm12
+
+// CHECK: vsm4key4  -2048(%rdx), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xa2,0x00,0xf8,0xff,0xff]
+          vsm4key4  -2048(%rdx), %xmm13, %xmm12
+
+// CHECK: vsm4rnds4 %ymm4, %ymm13, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x17,0xda,0xe4]
+          vsm4rnds4 %ymm4, %ymm13, %ymm12
+
+// CHECK: vsm4rnds4 %xmm4, %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x13,0xda,0xe4]
+          vsm4rnds4 %xmm4, %xmm13, %xmm12
+
+// CHECK: vsm4rnds4  268435456(%rbp,%r14,8), %ymm13, %ymm12
+// CHECK: encoding: [0xc4,0x22,0x17,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+          vsm4rnds4  268435456(%rbp,%r14,8), %ymm13, %ymm12
+
+// CHECK: vsm4rnds4  291(%r8,%rax,4), %ymm13, %ymm12
+// CHECK: encoding: [0xc4,0x42,0x17,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+          vsm4rnds4  291(%r8,%rax,4), %ymm13, %ymm12
+
+// CHECK: vsm4rnds4  (%rip), %ymm13, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x17,0xda,0x25,0x00,0x00,0x00,0x00]
+          vsm4rnds4  (%rip), %ymm13, %ymm12
+
+// CHECK: vsm4rnds4  -1024(,%rbp,2), %ymm13, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x17,0xda,0x24,0x6d,0x00,0xfc,0xff,0xff]
+          vsm4rnds4  -1024(,%rbp,2), %ymm13, %ymm12
+
+// CHECK: vsm4rnds4  4064(%rcx), %ymm13, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x17,0xda,0xa1,0xe0,0x0f,0x00,0x00]
+          vsm4rnds4  4064(%rcx), %ymm13, %ymm12
+
+// CHECK: vsm4rnds4  -4096(%rdx), %ymm13, %ymm12
+// CHECK: encoding: [0xc4,0x62,0x17,0xda,0xa2,0x00,0xf0,0xff,0xff]
+          vsm4rnds4  -4096(%rdx), %ymm13, %ymm12
+
+// CHECK: vsm4rnds4  268435456(%rbp,%r14,8), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x22,0x13,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+          vsm4rnds4  268435456(%rbp,%r14,8), %xmm13, %xmm12
+
+// CHECK: vsm4rnds4  291(%r8,%rax,4), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x42,0x13,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+          vsm4rnds4  291(%r8,%rax,4), %xmm13, %xmm12
+
+// CHECK: vsm4rnds4  (%rip), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x13,0xda,0x25,0x00,0x00,0x00,0x00]
+          vsm4rnds4  (%rip), %xmm13, %xmm12
+
+// CHECK: vsm4rnds4  -512(,%rbp,2), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x13,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+          vsm4rnds4  -512(,%rbp,2), %xmm13, %xmm12
+
+// CHECK: vsm4rnds4  2032(%rcx), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x13,0xda,0xa1,0xf0,0x07,0x00,0x00]
+          vsm4rnds4  2032(%rcx), %xmm13, %xmm12
+
+// CHECK: vsm4rnds4  -2048(%rdx), %xmm13, %xmm12
+// CHECK: encoding: [0xc4,0x62,0x13,0xda,0xa2,0x00,0xf8,0xff,0xff]
+          vsm4rnds4  -2048(%rdx), %xmm13, %xmm12
+

llvm/test/MC/X86/sm4-64-intel.s

+// RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK: vsm4key4 ymm12, ymm13, ymm4
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xe4]
+          vsm4key4 ymm12, ymm13, ymm4
+
+// CHECK: vsm4key4 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xe4]
+          vsm4key4 xmm12, xmm13, xmm4
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x16,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+          vsm4key4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x16,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+          vsm4key4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0x25,0x00,0x00,0x00,0x00]
+          vsm4key4 ymm12, ymm13, ymmword ptr [rip]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [2*rbp - 1024]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0x24,0x6d,0x00,0xfc,0xff,0xff]
+          vsm4key4 ymm12, ymm13, ymmword ptr [2*rbp - 1024]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rcx + 4064]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xa1,0xe0,0x0f,0x00,0x00]
+          vsm4key4 ymm12, ymm13, ymmword ptr [rcx + 4064]
+
+// CHECK: vsm4key4 ymm12, ymm13, ymmword ptr [rdx - 4096]
+// CHECK: encoding: [0xc4,0x62,0x16,0xda,0xa2,0x00,0xf0,0xff,0xff]
+          vsm4key4 ymm12, ymm13, ymmword ptr [rdx - 4096]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x12,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+          vsm4key4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x12,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+          vsm4key4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0x25,0x00,0x00,0x00,0x00]
+          vsm4key4 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+          vsm4key4 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xa1,0xf0,0x07,0x00,0x00]
+          vsm4key4 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm4key4 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x12,0xda,0xa2,0x00,0xf8,0xff,0xff]
+          vsm4key4 xmm12, xmm13, xmmword ptr [rdx - 2048]
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymm4
+// CHECK: encoding: [0xc4,0x62,0x17,0xda,0xe4]
+          vsm4rnds4 ymm12, ymm13, ymm4
+
+// CHECK: vsm4rnds4 xmm12, xmm13, xmm4
+// CHECK: encoding: [0xc4,0x62,0x13,0xda,0xe4]
+          vsm4rnds4 xmm12, xmm13, xmm4
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x17,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+          vsm4rnds4 ymm12, ymm13, ymmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x17,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+          vsm4rnds4 ymm12, ymm13, ymmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x17,0xda,0x25,0x00,0x00,0x00,0x00]
+          vsm4rnds4 ymm12, ymm13, ymmword ptr [rip]
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [2*rbp - 1024]
+// CHECK: encoding: [0xc4,0x62,0x17,0xda,0x24,0x6d,0x00,0xfc,0xff,0xff]
+          vsm4rnds4 ymm12, ymm13, ymmword ptr [2*rbp - 1024]
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [rcx + 4064]
+// CHECK: encoding: [0xc4,0x62,0x17,0xda,0xa1,0xe0,0x0f,0x00,0x00]
+          vsm4rnds4 ymm12, ymm13, ymmword ptr [rcx + 4064]
+
+// CHECK: vsm4rnds4 ymm12, ymm13, ymmword ptr [rdx - 4096]
+// CHECK: encoding: [0xc4,0x62,0x17,0xda,0xa2,0x00,0xf0,0xff,0xff]
+          vsm4rnds4 ymm12, ymm13, ymmword ptr [rdx - 4096]
+
+// CHECK: vsm4rnds4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+// CHECK: encoding: [0xc4,0x22,0x13,0xda,0xa4,0xf5,0x00,0x00,0x00,0x10]
+          vsm4rnds4 xmm12, xmm13, xmmword ptr [rbp + 8*r14 + 268435456]
+
+// CHECK: vsm4rnds4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+// CHECK: encoding: [0xc4,0x42,0x13,0xda,0xa4,0x80,0x23,0x01,0x00,0x00]
+          vsm4rnds4 xmm12, xmm13, xmmword ptr [r8 + 4*rax + 291]
+
+// CHECK: vsm4rnds4 xmm12, xmm13, xmmword ptr [rip]
+// CHECK: encoding: [0xc4,0x62,0x13,0xda,0x25,0x00,0x00,0x00,0x00]
+          vsm4rnds4 xmm12, xmm13, xmmword ptr [rip]
+
+// CHECK: vsm4rnds4 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+// CHECK: encoding: [0xc4,0x62,0x13,0xda,0x24,0x6d,0x00,0xfe,0xff,0xff]
+          vsm4rnds4 xmm12, xmm13, xmmword ptr [2*rbp - 512]
+
+// CHECK: vsm4rnds4 xmm12, xmm13, xmmword ptr [rcx + 2032]
+// CHECK: encoding: [0xc4,0x62,0x13,0xda,0xa1,0xf0,0x07,0x00,0x00]
+          vsm4rnds4 xmm12, xmm13, xmmword ptr [rcx + 2032]
+
+// CHECK: vsm4rnds4 xmm12, xmm13, xmmword ptr [rdx - 2048]
+// CHECK: encoding: [0xc4,0x62,0x13,0xda,0xa2,0x00,0xf8,0xff,0xff]
+          vsm4rnds4 xmm12, xmm13, xmmword ptr [rdx - 2048]
+

llvm/test/TableGen/x86-fold-tables.inc

   {X86::VSHUFPDZ256rri, X86::VSHUFPDZ256rmi, 0},
   {X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0},
   {X86::VSHUFPDrri, X86::VSHUFPDrmi, 0},
   {X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0},
   {X86::VSHUFPSZ128rri, X86::VSHUFPSZ128rmi, 0},
   {X86::VSHUFPSZ256rri, X86::VSHUFPSZ256rmi, 0},
   {X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0},
   {X86::VSHUFPSrri, X86::VSHUFPSrmi, 0},
+  {X86::VSM4KEY4Yrr, X86::VSM4KEY4Yrm, 0},
+  {X86::VSM4KEY4rr, X86::VSM4KEY4rm, 0},
+  {X86::VSM4RNDS4Yrr, X86::VSM4RNDS4Yrm, 0},
+  {X86::VSM4RNDS4rr, X86::VSM4RNDS4rm, 0},
   {X86::VSQRTPDZ128rkz, X86::VSQRTPDZ128mkz, 0},
   {X86::VSQRTPDZ256rkz, X86::VSQRTPDZ256mkz, 0},
   {X86::VSQRTPDZrkz, X86::VSQRTPDZmkz, 0},
   {X86::VSQRTPHZ128rkz, X86::VSQRTPHZ128mkz, 0},
   {X86::VSQRTPHZ256rkz, X86::VSQRTPHZ256mkz, 0},
   {X86::VSQRTPHZrkz, X86::VSQRTPHZmkz, 0},
   {X86::VSQRTPSZ128rkz, X86::VSQRTPSZ128mkz, 0},
   {X86::VSQRTPSZ256rkz, X86::VSQRTPSZ256mkz, 0},