[RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)

[liaolucy]

Summary

Improve D151719.
(xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
https://alive2.llvm.org/ce/z/BZNEia

[liaolucy]

Update, add hasOneUse()

[liaolucy]

[RISCV]Fold xor(setcc x, y, cond), 1 --> setcc (x, y, inverted(cond))

[liaolucy]

revert the last commit.sorry

[liaolucy]

[RISCV]Fold xor(setcc x, y, cond), 1 --> setcc (x, y, inverted(cond))

[liaolucy]

revert the last commit.

I tried to set the related parent but it always failed, gave up for now.
I'll post next patch later. (Fold xor(setcc x, y, cond), 1 --> setcc (x, y, inverted(cond)))

I'm sorry to bother you all.

[liaolucy]

Rebase and remove two temporary variables, clearer now.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

10319

Use APInt methods here. I don't think we're protected against types being larger than i64 here. So getSExtValue() might assert.

10320

Imm+1 is undefined behavior if Imm happens to be INT64_MAX. Another reason to use APInt.

[liaolucy]

address comments, use APInt methods, thanks.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISC-V DAG Lowering Implementation  -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the interfaces that RISC-V uses to lower LLVM code into a
static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
   if (N0.getOpcode() == RISCVISD::SLLW &&
       isAllOnesConstant(N1) && isOneConstant(N0.getOperand(0)) &&
       TLI.isOperationLegal(ISD::ROTL, MVT::i64)) {
     SDLoc DL(N);
     return DAG.getNode(RISCVISD::ROLW, DL, MVT::i64,
                        DAG.getConstant(~1, DL, MVT::i64), N0.getOperand(1));
   }
 
+  // Fold (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
+  if (N0.hasOneUse() && N0.getOpcode() == ISD::SETCC && isOneConstant(N1)) {
+    EVT VT = N0.getValueType();
+    SDLoc DL(N0);
+    SDValue N00 = N0.getOperand(0);
+    SDValue N01 = N0.getOperand(1);
+    auto *ConstN00 = dyn_cast<ConstantSDNode>(N00);
+    ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
+    if (ConstN00 && CC == ISD::SETLT) {
+      int64_t Imm = ConstN00->getSExtValue();
+      if (isInt<12>(Imm + 1))
+        return DAG.getSetCC(DL, VT, N01, DAG.getConstant(Imm + 1, DL, VT), CC);
+    }
+    // Fold xor(setcc x, y, cond), 1 --> setcc (x, y, inverted(cond))
+    if (!(CC == ISD::SETULT || CC == ISD::SETULE || CC == ISD::SETLT || CC == ISD::SETOEQ))
+      return DAG.getSetCC(DL, VT, N00, N01, ISD::getSetCCInverse(CC, VT));
+  }
+
   if (SDValue V = combineBinOpToReduce(N, DAG, Subtarget))
     return V;
   // fold (xor (select cond, 0, y), x) ->
   //      (select cond, x, (xor x, y))
   return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false, Subtarget);
 }
 
 // Replace (seteq (i64 (and X, 0xffffffff)), C1) with

llvm/test/CodeGen/RISCV/double-br-fcmp.ll

 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_ugt(double %a, double %b) nounwind {
 ; RV32IFD-LABEL: br_fcmp_ugt:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fle.d a0, fa0, fa1
-; RV32IFD-NEXT:    beqz a0, .LBB10_2
+; RV32IFD-NEXT:    flt.d a0, fa1, fa0
+; RV32IFD-NEXT:    bnez a0, .LBB10_2
 ; RV32IFD-NEXT:  # %bb.1: # %if.else
 ; RV32IFD-NEXT:    ret
 ; RV32IFD-NEXT:  .LBB10_2: # %if.then
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    call abort@plt
 ;
 ; RV64IFD-LABEL: br_fcmp_ugt:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fle.d a0, fa0, fa1
-; RV64IFD-NEXT:    beqz a0, .LBB10_2
+; RV64IFD-NEXT:    flt.d a0, fa1, fa0
+; RV64IFD-NEXT:    bnez a0, .LBB10_2
 ; RV64IFD-NEXT:  # %bb.1: # %if.else
 ; RV64IFD-NEXT:    ret
 ; RV64IFD-NEXT:  .LBB10_2: # %if.then
 ; RV64IFD-NEXT:    addi sp, sp, -16
 ; RV64IFD-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IFD-NEXT:    call abort@plt
 ;
 ; RV32IZFINXZDINX-LABEL: br_fcmp_ugt:
 ; RV32IZFINXZDINX:       # %bb.0:
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINXZDINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT:    sw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT:    sw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT:    lw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT:    lw a3, 4(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a0, 0(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a1, 4(sp)
 ; RV32IZFINXZDINX-NEXT:    lw a0, 0(sp)
 ; RV32IZFINXZDINX-NEXT:    lw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT:    fle.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT:    beqz a0, .LBB10_2
+; RV32IZFINXZDINX-NEXT:    sw a2, 0(sp)
+; RV32IZFINXZDINX-NEXT:    sw a3, 4(sp)
+; RV32IZFINXZDINX-NEXT:    lw a2, 0(sp)
+; RV32IZFINXZDINX-NEXT:    lw a3, 4(sp)
+; RV32IZFINXZDINX-NEXT:    flt.d a0, a2, a0
+; RV32IZFINXZDINX-NEXT:    bnez a0, .LBB10_2
 ; RV32IZFINXZDINX-NEXT:  # %bb.1: # %if.else
 ; RV32IZFINXZDINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, 16
 ; RV32IZFINXZDINX-NEXT:    ret
 ; RV32IZFINXZDINX-NEXT:  .LBB10_2: # %if.then
 ; RV32IZFINXZDINX-NEXT:    call abort@plt
 ;
 ; RV64IZFINXZDINX-LABEL: br_fcmp_ugt:
 ; RV64IZFINXZDINX:       # %bb.0:
-; RV64IZFINXZDINX-NEXT:    fle.d a0, a0, a1
-; RV64IZFINXZDINX-NEXT:    beqz a0, .LBB10_2
+; RV64IZFINXZDINX-NEXT:    flt.d a0, a1, a0
+; RV64IZFINXZDINX-NEXT:    bnez a0, .LBB10_2
 ; RV64IZFINXZDINX-NEXT:  # %bb.1: # %if.else
 ; RV64IZFINXZDINX-NEXT:    ret
 ; RV64IZFINXZDINX-NEXT:  .LBB10_2: # %if.then
 ; RV64IZFINXZDINX-NEXT:    addi sp, sp, -16
 ; RV64IZFINXZDINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFINXZDINX-NEXT:    call abort@plt
   %1 = fcmp ugt double %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_uge(double %a, double %b) nounwind {
 ; RV32IFD-LABEL: br_fcmp_uge:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa0, fa1
-; RV32IFD-NEXT:    beqz a0, .LBB11_2
+; RV32IFD-NEXT:    fle.d a0, fa1, fa0
+; RV32IFD-NEXT:    bnez a0, .LBB11_2
 ; RV32IFD-NEXT:  # %bb.1: # %if.else
 ; RV32IFD-NEXT:    ret
 ; RV32IFD-NEXT:  .LBB11_2: # %if.then
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    call abort@plt
 ;
 ; RV64IFD-LABEL: br_fcmp_uge:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa0, fa1
-; RV64IFD-NEXT:    beqz a0, .LBB11_2
+; RV64IFD-NEXT:    fle.d a0, fa1, fa0
+; RV64IFD-NEXT:    bnez a0, .LBB11_2
 ; RV64IFD-NEXT:  # %bb.1: # %if.else
 ; RV64IFD-NEXT:    ret
 ; RV64IFD-NEXT:  .LBB11_2: # %if.then
 ; RV64IFD-NEXT:    addi sp, sp, -16
 ; RV64IFD-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IFD-NEXT:    call abort@plt
 ;
 ; RV32IZFINXZDINX-LABEL: br_fcmp_uge:
 ; RV32IZFINXZDINX:       # %bb.0:
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINXZDINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT:    sw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT:    sw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT:    lw a2, 0(sp)
-; RV32IZFINXZDINX-NEXT:    lw a3, 4(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a0, 0(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a1, 4(sp)
 ; RV32IZFINXZDINX-NEXT:    lw a0, 0(sp)
 ; RV32IZFINXZDINX-NEXT:    lw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT:    flt.d a0, a0, a2
-; RV32IZFINXZDINX-NEXT:    beqz a0, .LBB11_2
+; RV32IZFINXZDINX-NEXT:    sw a2, 0(sp)
+; RV32IZFINXZDINX-NEXT:    sw a3, 4(sp)
+; RV32IZFINXZDINX-NEXT:    lw a2, 0(sp)
+; RV32IZFINXZDINX-NEXT:    lw a3, 4(sp)
+; RV32IZFINXZDINX-NEXT:    fle.d a0, a2, a0
+; RV32IZFINXZDINX-NEXT:    bnez a0, .LBB11_2
 ; RV32IZFINXZDINX-NEXT:  # %bb.1: # %if.else
 ; RV32IZFINXZDINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, 16
 ; RV32IZFINXZDINX-NEXT:    ret
 ; RV32IZFINXZDINX-NEXT:  .LBB11_2: # %if.then
 ; RV32IZFINXZDINX-NEXT:    call abort@plt
 ;
 ; RV64IZFINXZDINX-LABEL: br_fcmp_uge:
 ; RV64IZFINXZDINX:       # %bb.0:
-; RV64IZFINXZDINX-NEXT:    flt.d a0, a0, a1
-; RV64IZFINXZDINX-NEXT:    beqz a0, .LBB11_2
+; RV64IZFINXZDINX-NEXT:    fle.d a0, a1, a0
+; RV64IZFINXZDINX-NEXT:    bnez a0, .LBB11_2
 ; RV64IZFINXZDINX-NEXT:  # %bb.1: # %if.else
 ; RV64IZFINXZDINX-NEXT:    ret
 ; RV64IZFINXZDINX-NEXT:  .LBB11_2: # %if.then
 ; RV64IZFINXZDINX-NEXT:    addi sp, sp, -16
 ; RV64IZFINXZDINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFINXZDINX-NEXT:    call abort@plt
   %1 = fcmp uge double %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_ult(double %a, double %b) nounwind {
 ; RV32IFD-LABEL: br_fcmp_ult:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fle.d a0, fa1, fa0
-; RV32IFD-NEXT:    beqz a0, .LBB12_2
+; RV32IFD-NEXT:    flt.d a0, fa0, fa1
+; RV32IFD-NEXT:    bnez a0, .LBB12_2
 ; RV32IFD-NEXT:  # %bb.1: # %if.else
 ; RV32IFD-NEXT:    ret
 ; RV32IFD-NEXT:  .LBB12_2: # %if.then
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    call abort@plt
 ;
 ; RV64IFD-LABEL: br_fcmp_ult:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fle.d a0, fa1, fa0
-; RV64IFD-NEXT:    beqz a0, .LBB12_2
+; RV64IFD-NEXT:    flt.d a0, fa0, fa1
+; RV64IFD-NEXT:    bnez a0, .LBB12_2
 ; RV64IFD-NEXT:  # %bb.1: # %if.else
 ; RV64IFD-NEXT:    ret
 ; RV64IFD-NEXT:  .LBB12_2: # %if.then
 ; RV64IFD-NEXT:    addi sp, sp, -16
 ; RV64IFD-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IFD-NEXT:    call abort@plt
 ;
 ; RV32IZFINXZDINX-LABEL: br_fcmp_ult:
 ; RV32IZFINXZDINX:       # %bb.0:
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINXZDINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT:    sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT:    sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT:    lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT:    lw a1, 4(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a2, 0(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a3, 4(sp)
 ; RV32IZFINXZDINX-NEXT:    lw a2, 0(sp)
 ; RV32IZFINXZDINX-NEXT:    lw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT:    fle.d a0, a2, a0
-; RV32IZFINXZDINX-NEXT:    beqz a0, .LBB12_2
+; RV32IZFINXZDINX-NEXT:    sw a0, 0(sp)
+; RV32IZFINXZDINX-NEXT:    sw a1, 4(sp)
+; RV32IZFINXZDINX-NEXT:    lw a0, 0(sp)
+; RV32IZFINXZDINX-NEXT:    lw a1, 4(sp)
+; RV32IZFINXZDINX-NEXT:    flt.d a0, a0, a2
+; RV32IZFINXZDINX-NEXT:    bnez a0, .LBB12_2
 ; RV32IZFINXZDINX-NEXT:  # %bb.1: # %if.else
 ; RV32IZFINXZDINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, 16
 ; RV32IZFINXZDINX-NEXT:    ret
 ; RV32IZFINXZDINX-NEXT:  .LBB12_2: # %if.then
 ; RV32IZFINXZDINX-NEXT:    call abort@plt
 ;
 ; RV64IZFINXZDINX-LABEL: br_fcmp_ult:
 ; RV64IZFINXZDINX:       # %bb.0:
-; RV64IZFINXZDINX-NEXT:    fle.d a0, a1, a0
-; RV64IZFINXZDINX-NEXT:    beqz a0, .LBB12_2
+; RV64IZFINXZDINX-NEXT:    flt.d a0, a0, a1
+; RV64IZFINXZDINX-NEXT:    bnez a0, .LBB12_2
 ; RV64IZFINXZDINX-NEXT:  # %bb.1: # %if.else
 ; RV64IZFINXZDINX-NEXT:    ret
 ; RV64IZFINXZDINX-NEXT:  .LBB12_2: # %if.then
 ; RV64IZFINXZDINX-NEXT:    addi sp, sp, -16
 ; RV64IZFINXZDINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFINXZDINX-NEXT:    call abort@plt
   %1 = fcmp ult double %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_ule(double %a, double %b) nounwind {
 ; RV32IFD-LABEL: br_fcmp_ule:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    flt.d a0, fa1, fa0
-; RV32IFD-NEXT:    beqz a0, .LBB13_2
+; RV32IFD-NEXT:    fle.d a0, fa0, fa1
+; RV32IFD-NEXT:    bnez a0, .LBB13_2
 ; RV32IFD-NEXT:  # %bb.1: # %if.else
 ; RV32IFD-NEXT:    ret
 ; RV32IFD-NEXT:  .LBB13_2: # %if.then
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    call abort@plt
 ;
 ; RV64IFD-LABEL: br_fcmp_ule:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    flt.d a0, fa1, fa0
-; RV64IFD-NEXT:    beqz a0, .LBB13_2
+; RV64IFD-NEXT:    fle.d a0, fa0, fa1
+; RV64IFD-NEXT:    bnez a0, .LBB13_2
 ; RV64IFD-NEXT:  # %bb.1: # %if.else
 ; RV64IFD-NEXT:    ret
 ; RV64IFD-NEXT:  .LBB13_2: # %if.then
 ; RV64IFD-NEXT:    addi sp, sp, -16
 ; RV64IFD-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IFD-NEXT:    call abort@plt
 ;
 ; RV32IZFINXZDINX-LABEL: br_fcmp_ule:
 ; RV32IZFINXZDINX:       # %bb.0:
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINXZDINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT:    sw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT:    sw a1, 4(sp)
-; RV32IZFINXZDINX-NEXT:    lw a0, 0(sp)
-; RV32IZFINXZDINX-NEXT:    lw a1, 4(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a2, 0(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a3, 4(sp)
 ; RV32IZFINXZDINX-NEXT:    lw a2, 0(sp)
 ; RV32IZFINXZDINX-NEXT:    lw a3, 4(sp)
-; RV32IZFINXZDINX-NEXT:    flt.d a0, a2, a0
-; RV32IZFINXZDINX-NEXT:    beqz a0, .LBB13_2
+; RV32IZFINXZDINX-NEXT:    sw a0, 0(sp)
+; RV32IZFINXZDINX-NEXT:    sw a1, 4(sp)
+; RV32IZFINXZDINX-NEXT:    lw a0, 0(sp)
+; RV32IZFINXZDINX-NEXT:    lw a1, 4(sp)
+; RV32IZFINXZDINX-NEXT:    fle.d a0, a0, a2
+; RV32IZFINXZDINX-NEXT:    bnez a0, .LBB13_2
 ; RV32IZFINXZDINX-NEXT:  # %bb.1: # %if.else
 ; RV32IZFINXZDINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, 16
 ; RV32IZFINXZDINX-NEXT:    ret
 ; RV32IZFINXZDINX-NEXT:  .LBB13_2: # %if.then
 ; RV32IZFINXZDINX-NEXT:    call abort@plt
 ;
 ; RV64IZFINXZDINX-LABEL: br_fcmp_ule:
 ; RV64IZFINXZDINX:       # %bb.0:
-; RV64IZFINXZDINX-NEXT:    flt.d a0, a1, a0
-; RV64IZFINXZDINX-NEXT:    beqz a0, .LBB13_2
+; RV64IZFINXZDINX-NEXT:    fle.d a0, a0, a1
+; RV64IZFINXZDINX-NEXT:    bnez a0, .LBB13_2
 ; RV64IZFINXZDINX-NEXT:  # %bb.1: # %if.else
 ; RV64IZFINXZDINX-NEXT:    ret
 ; RV64IZFINXZDINX-NEXT:  .LBB13_2: # %if.then
 ; RV64IZFINXZDINX-NEXT:    addi sp, sp, -16
 ; RV64IZFINXZDINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFINXZDINX-NEXT:    call abort@plt
   %1 = fcmp ule double %a, %b
   br i1 %1, label %if.then, label %if.else

llvm/test/CodeGen/RISCV/double-convert.ll

 ; RV32IFD:       # %bb.0: # %start
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI12_0)
 ; RV32IFD-NEXT:    fld fa5, %lo(.LCPI12_0)(a0)
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
-; RV32IFD-NEXT:    fle.d s0, fa5, fa0
+; RV32IFD-NEXT:    flt.d s0, fa0, fa5
 ; RV32IFD-NEXT:    call __fixdfdi@plt
 ; RV32IFD-NEXT:    lui a4, 524288
 ; RV32IFD-NEXT:    lui a2, 524288
-; RV32IFD-NEXT:    beqz s0, .LBB12_2
+; RV32IFD-NEXT:    bnez s0, .LBB12_2
 ; RV32IFD-NEXT:  # %bb.1: # %start
 ; RV32IFD-NEXT:    mv a2, a1
 ; RV32IFD-NEXT:  .LBB12_2: # %start
 ; RV32IFD-NEXT:    lui a1, %hi(.LCPI12_1)
 ; RV32IFD-NEXT:    fld fa5, %lo(.LCPI12_1)(a1)
 ; RV32IFD-NEXT:    flt.d a3, fa5, fs0
 ; RV32IFD-NEXT:    beqz a3, .LBB12_4
 ; RV32IFD-NEXT:  # %bb.3:
 ; RV32IFD-NEXT:    addi a2, a4, -1
 ; RV32IFD-NEXT:  .LBB12_4: # %start
 ; RV32IFD-NEXT:    feq.d a1, fs0, fs0
 ; RV32IFD-NEXT:    neg a4, a1
 ; RV32IFD-NEXT:    and a1, a4, a2
 ; RV32IFD-NEXT:    neg a2, a3
-; RV32IFD-NEXT:    neg a3, s0
-; RV32IFD-NEXT:    and a0, a3, a0
+; RV32IFD-NEXT:    addi s0, s0, -1
+; RV32IFD-NEXT:    and a0, s0, a0
 ; RV32IFD-NEXT:    or a0, a2, a0
 ; RV32IFD-NEXT:    and a0, a4, a0
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;

 ; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s0, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s1, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    call __fixdfdi@plt
 ; RV32IZFINXZDINX-NEXT:    lui a2, %hi(.LCPI12_0)
 ; RV32IZFINXZDINX-NEXT:    lw a3, %lo(.LCPI12_0+4)(a2)
 ; RV32IZFINXZDINX-NEXT:    lw a2, %lo(.LCPI12_0)(a2)
-; RV32IZFINXZDINX-NEXT:    fle.d a2, a2, s0
+; RV32IZFINXZDINX-NEXT:    flt.d a2, s0, a2
 ; RV32IZFINXZDINX-NEXT:    lui a5, 524288
 ; RV32IZFINXZDINX-NEXT:    lui a3, 524288
-; RV32IZFINXZDINX-NEXT:    beqz a2, .LBB12_2
+; RV32IZFINXZDINX-NEXT:    bnez a2, .LBB12_2
 ; RV32IZFINXZDINX-NEXT:  # %bb.1: # %start
 ; RV32IZFINXZDINX-NEXT:    mv a3, a1
 ; RV32IZFINXZDINX-NEXT:  .LBB12_2: # %start
 ; RV32IZFINXZDINX-NEXT:    lui a1, %hi(.LCPI12_1)
 ; RV32IZFINXZDINX-NEXT:    lw a6, %lo(.LCPI12_1)(a1)
 ; RV32IZFINXZDINX-NEXT:    lw a7, %lo(.LCPI12_1+4)(a1)
 ; RV32IZFINXZDINX-NEXT:    flt.d a4, a6, s0
 ; RV32IZFINXZDINX-NEXT:    beqz a4, .LBB12_4
 ; RV32IZFINXZDINX-NEXT:  # %bb.3:
 ; RV32IZFINXZDINX-NEXT:    addi a3, a5, -1
 ; RV32IZFINXZDINX-NEXT:  .LBB12_4: # %start
 ; RV32IZFINXZDINX-NEXT:    feq.d a1, s0, s0
 ; RV32IZFINXZDINX-NEXT:    neg a5, a1
 ; RV32IZFINXZDINX-NEXT:    and a1, a5, a3
-; RV32IZFINXZDINX-NEXT:    neg a2, a2
+; RV32IZFINXZDINX-NEXT:    addi a2, a2, -1
 ; RV32IZFINXZDINX-NEXT:    and a0, a2, a0
 ; RV32IZFINXZDINX-NEXT:    neg a2, a4
 ; RV32IZFINXZDINX-NEXT:    or a0, a2, a0
 ; RV32IZFINXZDINX-NEXT:    and a0, a5, a0
 ; RV32IZFINXZDINX-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, 32

 ; RV32IFD-LABEL: fcvt_lu_d_sat:
 ; RV32IFD:       # %bb.0: # %start
 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
 ; RV32IFD-NEXT:    fcvt.d.w fa5, zero
-; RV32IFD-NEXT:    fle.d a0, fa5, fa0
-; RV32IFD-NEXT:    neg s0, a0
+; RV32IFD-NEXT:    flt.d a0, fa0, fa5
+; RV32IFD-NEXT:    addi s0, a0, -1
 ; RV32IFD-NEXT:    call __fixunsdfdi@plt
 ; RV32IFD-NEXT:    lui a2, %hi(.LCPI14_0)
 ; RV32IFD-NEXT:    fld fa5, %lo(.LCPI14_0)(a2)
 ; RV32IFD-NEXT:    and a0, s0, a0
 ; RV32IFD-NEXT:    flt.d a2, fa5, fs0
 ; RV32IFD-NEXT:    neg a2, a2
 ; RV32IFD-NEXT:    or a0, a2, a0
 ; RV32IFD-NEXT:    and a1, s0, a1

 ; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s0, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s1, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    call __fixunsdfdi@plt
 ; RV32IZFINXZDINX-NEXT:    fcvt.d.w a2, zero
 ; RV32IZFINXZDINX-NEXT:    lui a4, %hi(.LCPI14_0)
 ; RV32IZFINXZDINX-NEXT:    lw a5, %lo(.LCPI14_0+4)(a4)
 ; RV32IZFINXZDINX-NEXT:    lw a4, %lo(.LCPI14_0)(a4)
-; RV32IZFINXZDINX-NEXT:    fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT:    neg a2, a2
+; RV32IZFINXZDINX-NEXT:    flt.d a2, s0, a2
+; RV32IZFINXZDINX-NEXT:    addi a2, a2, -1
 ; RV32IZFINXZDINX-NEXT:    and a0, a2, a0
 ; RV32IZFINXZDINX-NEXT:    flt.d a3, a4, s0
 ; RV32IZFINXZDINX-NEXT:    neg a3, a3
 ; RV32IZFINXZDINX-NEXT:    or a0, a3, a0
 ; RV32IZFINXZDINX-NEXT:    and a1, a2, a1
 ; RV32IZFINXZDINX-NEXT:    or a1, a3, a1
 ; RV32IZFINXZDINX-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload

llvm/test/CodeGen/RISCV/double-fcmp.ll

; RV64I-NEXT:    ret
   %1 = fcmp ueq double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ugt(double %a, double %b) nounwind {
 ; CHECKIFD-LABEL: fcmp_ugt:
 ; CHECKIFD:       # %bb.0:
-; CHECKIFD-NEXT:    fle.d a0, fa0, fa1
-; CHECKIFD-NEXT:    xori a0, a0, 1
+; CHECKIFD-NEXT:    flt.d a0, fa1, fa0
 ; CHECKIFD-NEXT:    ret
 ;
 ; CHECKRV32IZFINXZDINX-LABEL: fcmp_ugt:
 ; CHECKRV32IZFINXZDINX:       # %bb.0:
 ; CHECKRV32IZFINXZDINX-NEXT:    addi sp, sp, -16
-; CHECKRV32IZFINXZDINX-NEXT:    sw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT:    sw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT:    lw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT:    lw a3, 12(sp)
 ; CHECKRV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
 ; CHECKRV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
 ; CHECKRV32IZFINXZDINX-NEXT:    lw a0, 8(sp)
 ; CHECKRV32IZFINXZDINX-NEXT:    lw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT:    fle.d a0, a0, a2
-; CHECKRV32IZFINXZDINX-NEXT:    xori a0, a0, 1
+; CHECKRV32IZFINXZDINX-NEXT:    sw a2, 8(sp)
+; CHECKRV32IZFINXZDINX-NEXT:    sw a3, 12(sp)
+; CHECKRV32IZFINXZDINX-NEXT:    lw a2, 8(sp)
+; CHECKRV32IZFINXZDINX-NEXT:    lw a3, 12(sp)
+; CHECKRV32IZFINXZDINX-NEXT:    flt.d a0, a2, a0
 ; CHECKRV32IZFINXZDINX-NEXT:    addi sp, sp, 16
 ; CHECKRV32IZFINXZDINX-NEXT:    ret
 ;
 ; CHECKRV64IZFINXZDINX-LABEL: fcmp_ugt:
 ; CHECKRV64IZFINXZDINX:       # %bb.0:
-; CHECKRV64IZFINXZDINX-NEXT:    fle.d a0, a0, a1
-; CHECKRV64IZFINXZDINX-NEXT:    xori a0, a0, 1
+; CHECKRV64IZFINXZDINX-NEXT:    flt.d a0, a1, a0
 ; CHECKRV64IZFINXZDINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ledf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
; RV64I-NEXT:    ret
   %1 = fcmp ugt double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uge(double %a, double %b) nounwind {
 ; CHECKIFD-LABEL: fcmp_uge:
 ; CHECKIFD:       # %bb.0:
-; CHECKIFD-NEXT:    flt.d a0, fa0, fa1
-; CHECKIFD-NEXT:    xori a0, a0, 1
+; CHECKIFD-NEXT:    fle.d a0, fa1, fa0
 ; CHECKIFD-NEXT:    ret
 ;
 ; CHECKRV32IZFINXZDINX-LABEL: fcmp_uge:
 ; CHECKRV32IZFINXZDINX:       # %bb.0:
 ; CHECKRV32IZFINXZDINX-NEXT:    addi sp, sp, -16
-; CHECKRV32IZFINXZDINX-NEXT:    sw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT:    sw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT:    lw a2, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT:    lw a3, 12(sp)
 ; CHECKRV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
 ; CHECKRV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
 ; CHECKRV32IZFINXZDINX-NEXT:    lw a0, 8(sp)
 ; CHECKRV32IZFINXZDINX-NEXT:    lw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT:    flt.d a0, a0, a2
-; CHECKRV32IZFINXZDINX-NEXT:    xori a0, a0, 1
+; CHECKRV32IZFINXZDINX-NEXT:    sw a2, 8(sp)
+; CHECKRV32IZFINXZDINX-NEXT:    sw a3, 12(sp)
+; CHECKRV32IZFINXZDINX-NEXT:    lw a2, 8(sp)
+; CHECKRV32IZFINXZDINX-NEXT:    lw a3, 12(sp)
+; CHECKRV32IZFINXZDINX-NEXT:    fle.d a0, a2, a0
 ; CHECKRV32IZFINXZDINX-NEXT:    addi sp, sp, 16
 ; CHECKRV32IZFINXZDINX-NEXT:    ret
 ;
 ; CHECKRV64IZFINXZDINX-LABEL: fcmp_uge:
 ; CHECKRV64IZFINXZDINX:       # %bb.0:
-; CHECKRV64IZFINXZDINX-NEXT:    flt.d a0, a0, a1
-; CHECKRV64IZFINXZDINX-NEXT:    xori a0, a0, 1
+; CHECKRV64IZFINXZDINX-NEXT:    fle.d a0, a1, a0
 ; CHECKRV64IZFINXZDINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltdf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
; RV64I-NEXT:    ret
   %1 = fcmp uge double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ult(double %a, double %b) nounwind {
 ; CHECKIFD-LABEL: fcmp_ult:
 ; CHECKIFD:       # %bb.0:
-; CHECKIFD-NEXT:    fle.d a0, fa1, fa0
-; CHECKIFD-NEXT:    xori a0, a0, 1
+; CHECKIFD-NEXT:    flt.d a0, fa0, fa1
 ; CHECKIFD-NEXT:    ret
 ;
 ; CHECKRV32IZFINXZDINX-LABEL: fcmp_ult:
 ; CHECKRV32IZFINXZDINX:       # %bb.0:
 ; CHECKRV32IZFINXZDINX-NEXT:    addi sp, sp, -16
-; CHECKRV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT:    lw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT:    lw a1, 12(sp)
 ; CHECKRV32IZFINXZDINX-NEXT:    sw a2, 8(sp)
 ; CHECKRV32IZFINXZDINX-NEXT:    sw a3, 12(sp)
 ; CHECKRV32IZFINXZDINX-NEXT:    lw a2, 8(sp)
 ; CHECKRV32IZFINXZDINX-NEXT:    lw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT:    fle.d a0, a2, a0
-; CHECKRV32IZFINXZDINX-NEXT:    xori a0, a0, 1
+; CHECKRV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
+; CHECKRV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
+; CHECKRV32IZFINXZDINX-NEXT:    lw a0, 8(sp)
+; CHECKRV32IZFINXZDINX-NEXT:    lw a1, 12(sp)
+; CHECKRV32IZFINXZDINX-NEXT:    flt.d a0, a0, a2
 ; CHECKRV32IZFINXZDINX-NEXT:    addi sp, sp, 16
 ; CHECKRV32IZFINXZDINX-NEXT:    ret
 ;
 ; CHECKRV64IZFINXZDINX-LABEL: fcmp_ult:
 ; CHECKRV64IZFINXZDINX:       # %bb.0:
-; CHECKRV64IZFINXZDINX-NEXT:    fle.d a0, a1, a0
-; CHECKRV64IZFINXZDINX-NEXT:    xori a0, a0, 1
+; CHECKRV64IZFINXZDINX-NEXT:    flt.d a0, a0, a1
 ; CHECKRV64IZFINXZDINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
; RV64I-NEXT:    ret
   %1 = fcmp ult double %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ule(double %a, double %b) nounwind {
 ; CHECKIFD-LABEL: fcmp_ule:
 ; CHECKIFD:       # %bb.0:
-; CHECKIFD-NEXT:    flt.d a0, fa1, fa0
-; CHECKIFD-NEXT:    xori a0, a0, 1
+; CHECKIFD-NEXT:    fle.d a0, fa0, fa1
 ; CHECKIFD-NEXT:    ret
 ;
 ; CHECKRV32IZFINXZDINX-LABEL: fcmp_ule:
 ; CHECKRV32IZFINXZDINX:       # %bb.0:
 ; CHECKRV32IZFINXZDINX-NEXT:    addi sp, sp, -16
-; CHECKRV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT:    lw a0, 8(sp)
-; CHECKRV32IZFINXZDINX-NEXT:    lw a1, 12(sp)
 ; CHECKRV32IZFINXZDINX-NEXT:    sw a2, 8(sp)
 ; CHECKRV32IZFINXZDINX-NEXT:    sw a3, 12(sp)
 ; CHECKRV32IZFINXZDINX-NEXT:    lw a2, 8(sp)
 ; CHECKRV32IZFINXZDINX-NEXT:    lw a3, 12(sp)
-; CHECKRV32IZFINXZDINX-NEXT:    flt.d a0, a2, a0
-; CHECKRV32IZFINXZDINX-NEXT:    xori a0, a0, 1
+; CHECKRV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
+; CHECKRV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
+; CHECKRV32IZFINXZDINX-NEXT:    lw a0, 8(sp)
+; CHECKRV32IZFINXZDINX-NEXT:    lw a1, 12(sp)
+; CHECKRV32IZFINXZDINX-NEXT:    fle.d a0, a0, a2
 ; CHECKRV32IZFINXZDINX-NEXT:    addi sp, sp, 16
 ; CHECKRV32IZFINXZDINX-NEXT:    ret
 ;
 ; CHECKRV64IZFINXZDINX-LABEL: fcmp_ule:
 ; CHECKRV64IZFINXZDINX:       # %bb.0:
-; CHECKRV64IZFINXZDINX-NEXT:    flt.d a0, a1, a0
-; CHECKRV64IZFINXZDINX-NEXT:    xori a0, a0, 1
+; CHECKRV64IZFINXZDINX-NEXT:    fle.d a0, a0, a1
 ; CHECKRV64IZFINXZDINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtdf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1

llvm/test/CodeGen/RISCV/double-previous-failure.ll

 ; RV32IFD-NEXT:    call test@plt
 ; RV32IFD-NEXT:    sw a0, 0(sp)
 ; RV32IFD-NEXT:    sw a1, 4(sp)
 ; RV32IFD-NEXT:    fld fa5, 0(sp)
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI1_0)
 ; RV32IFD-NEXT:    fld fa4, %lo(.LCPI1_0)(a0)
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI1_1)
 ; RV32IFD-NEXT:    fld fa3, %lo(.LCPI1_1)(a0)
-; RV32IFD-NEXT:    flt.d a0, fa5, fa4
-; RV32IFD-NEXT:    flt.d a1, fa3, fa5
-; RV32IFD-NEXT:    or a0, a0, a1
-; RV32IFD-NEXT:    beqz a0, .LBB1_2
+; RV32IFD-NEXT:    fle.d a0, fa4, fa5
+; RV32IFD-NEXT:    fle.d a1, fa5, fa3
+; RV32IFD-NEXT:    and a0, a0, a1
+; RV32IFD-NEXT:    bnez a0, .LBB1_2
 ; RV32IFD-NEXT:  # %bb.1: # %if.then
 ; RV32IFD-NEXT:    call abort@plt
 ; RV32IFD-NEXT:  .LBB1_2: # %if.end
+; RV32IFD-NEXT:    li a0, 0
 ; RV32IFD-NEXT:    call exit@plt
 ;
 ; RV32IZFINXZDINX-LABEL: main:
 ; RV32IZFINXZDINX:       # %bb.0: # %entry
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINXZDINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    lui a1, 262144
 ; RV32IZFINXZDINX-NEXT:    li a0, 0
 ; RV32IZFINXZDINX-NEXT:    call test@plt
 ; RV32IZFINXZDINX-NEXT:    sw a0, 0(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a1, 4(sp)
 ; RV32IZFINXZDINX-NEXT:    lw a0, 0(sp)
 ; RV32IZFINXZDINX-NEXT:    lw a1, 4(sp)
 ; RV32IZFINXZDINX-NEXT:    lui a2, %hi(.LCPI1_0)
 ; RV32IZFINXZDINX-NEXT:    lw a3, %lo(.LCPI1_0+4)(a2)
 ; RV32IZFINXZDINX-NEXT:    lw a2, %lo(.LCPI1_0)(a2)
 ; RV32IZFINXZDINX-NEXT:    lui a4, %hi(.LCPI1_1)
 ; RV32IZFINXZDINX-NEXT:    lw a5, %lo(.LCPI1_1+4)(a4)
 ; RV32IZFINXZDINX-NEXT:    lw a4, %lo(.LCPI1_1)(a4)
-; RV32IZFINXZDINX-NEXT:    flt.d a2, a0, a2
-; RV32IZFINXZDINX-NEXT:    flt.d a0, a4, a0
-; RV32IZFINXZDINX-NEXT:    or a0, a2, a0
-; RV32IZFINXZDINX-NEXT:    beqz a0, .LBB1_2
+; RV32IZFINXZDINX-NEXT:    fle.d a2, a2, a0
+; RV32IZFINXZDINX-NEXT:    fle.d a0, a0, a4
+; RV32IZFINXZDINX-NEXT:    and a0, a2, a0
+; RV32IZFINXZDINX-NEXT:    bnez a0, .LBB1_2
 ; RV32IZFINXZDINX-NEXT:  # %bb.1: # %if.then
 ; RV32IZFINXZDINX-NEXT:    call abort@plt
 ; RV32IZFINXZDINX-NEXT:  .LBB1_2: # %if.end
+; RV32IZFINXZDINX-NEXT:    li a0, 0
 ; RV32IZFINXZDINX-NEXT:    call exit@plt
 entry:
   %call = call double @test(double 2.000000e+00)
   %cmp = fcmp olt double %call, 2.400000e-01
   %cmp2 = fcmp ogt double %call, 2.600000e-01
   %or.cond = or i1 %cmp, %cmp2
   br i1 %or.cond, label %if.then, label %if.end
 

llvm/test/CodeGen/RISCV/double-round-conv-sat.ll

 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    call floor@plt
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI1_0)
 ; RV32IFD-NEXT:    fld fa5, %lo(.LCPI1_0)(a0)
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
-; RV32IFD-NEXT:    fle.d s0, fa5, fa0
+; RV32IFD-NEXT:    flt.d s0, fa0, fa5
 ; RV32IFD-NEXT:    call __fixdfdi@plt
 ; RV32IFD-NEXT:    lui a4, 524288
 ; RV32IFD-NEXT:    lui a2, 524288
-; RV32IFD-NEXT:    beqz s0, .LBB1_2
+; RV32IFD-NEXT:    bnez s0, .LBB1_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    mv a2, a1
 ; RV32IFD-NEXT:  .LBB1_2:
 ; RV32IFD-NEXT:    lui a1, %hi(.LCPI1_1)
 ; RV32IFD-NEXT:    fld fa5, %lo(.LCPI1_1)(a1)
 ; RV32IFD-NEXT:    flt.d a3, fa5, fs0
 ; RV32IFD-NEXT:    beqz a3, .LBB1_4
 ; RV32IFD-NEXT:  # %bb.3:
 ; RV32IFD-NEXT:    addi a2, a4, -1
 ; RV32IFD-NEXT:  .LBB1_4:
 ; RV32IFD-NEXT:    feq.d a1, fs0, fs0
 ; RV32IFD-NEXT:    neg a4, a1
 ; RV32IFD-NEXT:    and a1, a4, a2
 ; RV32IFD-NEXT:    neg a2, a3
-; RV32IFD-NEXT:    neg a3, s0
-; RV32IFD-NEXT:    and a0, a3, a0
+; RV32IFD-NEXT:    addi s0, s0, -1
+; RV32IFD-NEXT:    and a0, s0, a0
 ; RV32IFD-NEXT:    or a0, a2, a0
 ; RV32IFD-NEXT:    and a0, a4, a0
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;

 ; RV32IZFINXZDINX-NEXT:    call floor@plt
 ; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s2, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s3, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    lui a2, %hi(.LCPI1_0)
 ; RV32IZFINXZDINX-NEXT:    lw a3, %lo(.LCPI1_0+4)(a2)
 ; RV32IZFINXZDINX-NEXT:    lw a2, %lo(.LCPI1_0)(a2)
-; RV32IZFINXZDINX-NEXT:    fle.d s0, a2, s2
+; RV32IZFINXZDINX-NEXT:    flt.d s0, s2, a2
 ; RV32IZFINXZDINX-NEXT:    call __fixdfdi@plt
 ; RV32IZFINXZDINX-NEXT:    lui a4, 524288
 ; RV32IZFINXZDINX-NEXT:    lui a2, 524288
-; RV32IZFINXZDINX-NEXT:    beqz s0, .LBB1_2
+; RV32IZFINXZDINX-NEXT:    bnez s0, .LBB1_2
 ; RV32IZFINXZDINX-NEXT:  # %bb.1:
 ; RV32IZFINXZDINX-NEXT:    mv a2, a1
 ; RV32IZFINXZDINX-NEXT:  .LBB1_2:
 ; RV32IZFINXZDINX-NEXT:    lui a1, %hi(.LCPI1_1)
 ; RV32IZFINXZDINX-NEXT:    lw a6, %lo(.LCPI1_1)(a1)
 ; RV32IZFINXZDINX-NEXT:    lw a7, %lo(.LCPI1_1+4)(a1)
 ; RV32IZFINXZDINX-NEXT:    flt.d a3, a6, s2
 ; RV32IZFINXZDINX-NEXT:    beqz a3, .LBB1_4
 ; RV32IZFINXZDINX-NEXT:  # %bb.3:
 ; RV32IZFINXZDINX-NEXT:    addi a2, a4, -1
 ; RV32IZFINXZDINX-NEXT:  .LBB1_4:
 ; RV32IZFINXZDINX-NEXT:    feq.d a1, s2, s2
 ; RV32IZFINXZDINX-NEXT:    neg a4, a1
 ; RV32IZFINXZDINX-NEXT:    and a1, a4, a2
-; RV32IZFINXZDINX-NEXT:    neg a2, s0
-; RV32IZFINXZDINX-NEXT:    and a0, a2, a0
+; RV32IZFINXZDINX-NEXT:    addi s0, s0, -1
+; RV32IZFINXZDINX-NEXT:    and a0, s0, a0
 ; RV32IZFINXZDINX-NEXT:    neg a2, a3
 ; RV32IZFINXZDINX-NEXT:    or a0, a2, a0
 ; RV32IZFINXZDINX-NEXT:    and a0, a4, a0
 ; RV32IZFINXZDINX-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s2, 20(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s3, 16(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, 32

 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    call floor@plt
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI3_0)
 ; RV32IFD-NEXT:    fld fa5, %lo(.LCPI3_0)(a0)
 ; RV32IFD-NEXT:    flt.d a0, fa5, fa0
 ; RV32IFD-NEXT:    neg s0, a0
 ; RV32IFD-NEXT:    fcvt.d.w fa5, zero
-; RV32IFD-NEXT:    fle.d a0, fa5, fa0
-; RV32IFD-NEXT:    neg s1, a0
+; RV32IFD-NEXT:    flt.d a0, fa0, fa5
+; RV32IFD-NEXT:    addi s1, a0, -1
 ; RV32IFD-NEXT:    call __fixunsdfdi@plt
 ; RV32IFD-NEXT:    and a0, s1, a0
 ; RV32IFD-NEXT:    or a0, s0, a0
 ; RV32IFD-NEXT:    and a1, s1, a1
 ; RV32IFD-NEXT:    or a1, s0, a1
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload

 ; RV64IFD-NEXT:    ret
 ;
 ; RV32IZFINXZDINX-LABEL: test_floor_ui64:
 ; RV32IZFINXZDINX:       # %bb.0:
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, -32
 ; RV32IZFINXZDINX-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    call floor@plt
 ; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s0, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s1, 12(sp)
-; RV32IZFINXZDINX-NEXT:    fcvt.d.w a2, zero
-; RV32IZFINXZDINX-NEXT:    fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT:    neg s2, a2
 ; RV32IZFINXZDINX-NEXT:    call __fixunsdfdi@plt
-; RV32IZFINXZDINX-NEXT:    lui a2, %hi(.LCPI3_0)
-; RV32IZFINXZDINX-NEXT:    lw a3, %lo(.LCPI3_0+4)(a2)
-; RV32IZFINXZDINX-NEXT:    lw a2, %lo(.LCPI3_0)(a2)
-; RV32IZFINXZDINX-NEXT:    and a0, s2, a0
-; RV32IZFINXZDINX-NEXT:    flt.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT:    neg a2, a2
-; RV32IZFINXZDINX-NEXT:    or a0, a2, a0
-; RV32IZFINXZDINX-NEXT:    and a1, s2, a1
-; RV32IZFINXZDINX-NEXT:    or a1, a2, a1
+; RV32IZFINXZDINX-NEXT:    fcvt.d.w a2, zero
+; RV32IZFINXZDINX-NEXT:    lui a4, %hi(.LCPI3_0)
+; RV32IZFINXZDINX-NEXT:    lw a5, %lo(.LCPI3_0+4)(a4)
+; RV32IZFINXZDINX-NEXT:    lw a4, %lo(.LCPI3_0)(a4)
+; RV32IZFINXZDINX-NEXT:    flt.d a2, s0, a2
+; RV32IZFINXZDINX-NEXT:    addi a2, a2, -1
+; RV32IZFINXZDINX-NEXT:    and a0, a2, a0
+; RV32IZFINXZDINX-NEXT:    flt.d a3, a4, s0
+; RV32IZFINXZDINX-NEXT:    neg a3, a3
+; RV32IZFINXZDINX-NEXT:    or a0, a3, a0
+; RV32IZFINXZDINX-NEXT:    and a1, a2, a1
+; RV32IZFINXZDINX-NEXT:    or a1, a3, a1
 ; RV32IZFINXZDINX-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, 32
 ; RV32IZFINXZDINX-NEXT:    ret
 ;
 ; RV64IZFINXZDINX-LABEL: test_floor_ui64:
 ; RV64IZFINXZDINX:       # %bb.0:
 ; RV64IZFINXZDINX-NEXT:    fcvt.lu.d a1, a0, rdn
 ; RV64IZFINXZDINX-NEXT:    feq.d a0, a0, a0
 ; RV64IZFINXZDINX-NEXT:    seqz a0, a0

 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    call ceil@plt
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI5_0)
 ; RV32IFD-NEXT:    fld fa5, %lo(.LCPI5_0)(a0)
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
-; RV32IFD-NEXT:    fle.d s0, fa5, fa0
+; RV32IFD-NEXT:    flt.d s0, fa0, fa5
 ; RV32IFD-NEXT:    call __fixdfdi@plt
 ; RV32IFD-NEXT:    lui a4, 524288
 ; RV32IFD-NEXT:    lui a2, 524288
-; RV32IFD-NEXT:    beqz s0, .LBB5_2
+; RV32IFD-NEXT:    bnez s0, .LBB5_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    mv a2, a1
 ; RV32IFD-NEXT:  .LBB5_2:
 ; RV32IFD-NEXT:    lui a1, %hi(.LCPI5_1)
 ; RV32IFD-NEXT:    fld fa5, %lo(.LCPI5_1)(a1)
 ; RV32IFD-NEXT:    flt.d a3, fa5, fs0
 ; RV32IFD-NEXT:    beqz a3, .LBB5_4
 ; RV32IFD-NEXT:  # %bb.3:
 ; RV32IFD-NEXT:    addi a2, a4, -1
 ; RV32IFD-NEXT:  .LBB5_4:
 ; RV32IFD-NEXT:    feq.d a1, fs0, fs0
 ; RV32IFD-NEXT:    neg a4, a1
 ; RV32IFD-NEXT:    and a1, a4, a2
 ; RV32IFD-NEXT:    neg a2, a3
-; RV32IFD-NEXT:    neg a3, s0
-; RV32IFD-NEXT:    and a0, a3, a0
+; RV32IFD-NEXT:    addi s0, s0, -1
+; RV32IFD-NEXT:    and a0, s0, a0
 ; RV32IFD-NEXT:    or a0, a2, a0
 ; RV32IFD-NEXT:    and a0, a4, a0
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;

 ; RV32IZFINXZDINX-NEXT:    call ceil@plt
 ; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s2, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s3, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    lui a2, %hi(.LCPI5_0)
 ; RV32IZFINXZDINX-NEXT:    lw a3, %lo(.LCPI5_0+4)(a2)
 ; RV32IZFINXZDINX-NEXT:    lw a2, %lo(.LCPI5_0)(a2)
-; RV32IZFINXZDINX-NEXT:    fle.d s0, a2, s2
+; RV32IZFINXZDINX-NEXT:    flt.d s0, s2, a2
 ; RV32IZFINXZDINX-NEXT:    call __fixdfdi@plt
 ; RV32IZFINXZDINX-NEXT:    lui a4, 524288
 ; RV32IZFINXZDINX-NEXT:    lui a2, 524288
-; RV32IZFINXZDINX-NEXT:    beqz s0, .LBB5_2
+; RV32IZFINXZDINX-NEXT:    bnez s0, .LBB5_2
 ; RV32IZFINXZDINX-NEXT:  # %bb.1:
 ; RV32IZFINXZDINX-NEXT:    mv a2, a1
 ; RV32IZFINXZDINX-NEXT:  .LBB5_2:
 ; RV32IZFINXZDINX-NEXT:    lui a1, %hi(.LCPI5_1)
 ; RV32IZFINXZDINX-NEXT:    lw a6, %lo(.LCPI5_1)(a1)
 ; RV32IZFINXZDINX-NEXT:    lw a7, %lo(.LCPI5_1+4)(a1)
 ; RV32IZFINXZDINX-NEXT:    flt.d a3, a6, s2
 ; RV32IZFINXZDINX-NEXT:    beqz a3, .LBB5_4
 ; RV32IZFINXZDINX-NEXT:  # %bb.3:
 ; RV32IZFINXZDINX-NEXT:    addi a2, a4, -1
 ; RV32IZFINXZDINX-NEXT:  .LBB5_4:
 ; RV32IZFINXZDINX-NEXT:    feq.d a1, s2, s2
 ; RV32IZFINXZDINX-NEXT:    neg a4, a1
 ; RV32IZFINXZDINX-NEXT:    and a1, a4, a2
-; RV32IZFINXZDINX-NEXT:    neg a2, s0
-; RV32IZFINXZDINX-NEXT:    and a0, a2, a0
+; RV32IZFINXZDINX-NEXT:    addi s0, s0, -1
+; RV32IZFINXZDINX-NEXT:    and a0, s0, a0
 ; RV32IZFINXZDINX-NEXT:    neg a2, a3
 ; RV32IZFINXZDINX-NEXT:    or a0, a2, a0
 ; RV32IZFINXZDINX-NEXT:    and a0, a4, a0
 ; RV32IZFINXZDINX-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s2, 20(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s3, 16(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, 32

 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    call ceil@plt
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI7_0)
 ; RV32IFD-NEXT:    fld fa5, %lo(.LCPI7_0)(a0)
 ; RV32IFD-NEXT:    flt.d a0, fa5, fa0
 ; RV32IFD-NEXT:    neg s0, a0
 ; RV32IFD-NEXT:    fcvt.d.w fa5, zero
-; RV32IFD-NEXT:    fle.d a0, fa5, fa0
-; RV32IFD-NEXT:    neg s1, a0
+; RV32IFD-NEXT:    flt.d a0, fa0, fa5
+; RV32IFD-NEXT:    addi s1, a0, -1
 ; RV32IFD-NEXT:    call __fixunsdfdi@plt
 ; RV32IFD-NEXT:    and a0, s1, a0
 ; RV32IFD-NEXT:    or a0, s0, a0
 ; RV32IFD-NEXT:    and a1, s1, a1
 ; RV32IFD-NEXT:    or a1, s0, a1
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload

 ; RV64IFD-NEXT:    ret
 ;
 ; RV32IZFINXZDINX-LABEL: test_ceil_ui64:
 ; RV32IZFINXZDINX:       # %bb.0:
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, -32
 ; RV32IZFINXZDINX-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    call ceil@plt
 ; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s0, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s1, 12(sp)
-; RV32IZFINXZDINX-NEXT:    fcvt.d.w a2, zero
-; RV32IZFINXZDINX-NEXT:    fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT:    neg s2, a2
 ; RV32IZFINXZDINX-NEXT:    call __fixunsdfdi@plt
-; RV32IZFINXZDINX-NEXT:    lui a2, %hi(.LCPI7_0)
-; RV32IZFINXZDINX-NEXT:    lw a3, %lo(.LCPI7_0+4)(a2)
-; RV32IZFINXZDINX-NEXT:    lw a2, %lo(.LCPI7_0)(a2)
-; RV32IZFINXZDINX-NEXT:    and a0, s2, a0
-; RV32IZFINXZDINX-NEXT:    flt.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT:    neg a2, a2
-; RV32IZFINXZDINX-NEXT:    or a0, a2, a0
-; RV32IZFINXZDINX-NEXT:    and a1, s2, a1
-; RV32IZFINXZDINX-NEXT:    or a1, a2, a1
+; RV32IZFINXZDINX-NEXT:    fcvt.d.w a2, zero
+; RV32IZFINXZDINX-NEXT:    lui a4, %hi(.LCPI7_0)
+; RV32IZFINXZDINX-NEXT:    lw a5, %lo(.LCPI7_0+4)(a4)
+; RV32IZFINXZDINX-NEXT:    lw a4, %lo(.LCPI7_0)(a4)
+; RV32IZFINXZDINX-NEXT:    flt.d a2, s0, a2
+; RV32IZFINXZDINX-NEXT:    addi a2, a2, -1
+; RV32IZFINXZDINX-NEXT:    and a0, a2, a0
+; RV32IZFINXZDINX-NEXT:    flt.d a3, a4, s0
+; RV32IZFINXZDINX-NEXT:    neg a3, a3
+; RV32IZFINXZDINX-NEXT:    or a0, a3, a0
+; RV32IZFINXZDINX-NEXT:    and a1, a2, a1
+; RV32IZFINXZDINX-NEXT:    or a1, a3, a1
 ; RV32IZFINXZDINX-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, 32
 ; RV32IZFINXZDINX-NEXT:    ret
 ;
 ; RV64IZFINXZDINX-LABEL: test_ceil_ui64:
 ; RV64IZFINXZDINX:       # %bb.0:
 ; RV64IZFINXZDINX-NEXT:    fcvt.lu.d a1, a0, rup
 ; RV64IZFINXZDINX-NEXT:    feq.d a0, a0, a0
 ; RV64IZFINXZDINX-NEXT:    seqz a0, a0

 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    call trunc@plt
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI9_0)
 ; RV32IFD-NEXT:    fld fa5, %lo(.LCPI9_0)(a0)
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
-; RV32IFD-NEXT:    fle.d s0, fa5, fa0
+; RV32IFD-NEXT:    flt.d s0, fa0, fa5
 ; RV32IFD-NEXT:    call __fixdfdi@plt
 ; RV32IFD-NEXT:    lui a4, 524288
 ; RV32IFD-NEXT:    lui a2, 524288
-; RV32IFD-NEXT:    beqz s0, .LBB9_2
+; RV32IFD-NEXT:    bnez s0, .LBB9_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    mv a2, a1
 ; RV32IFD-NEXT:  .LBB9_2:
 ; RV32IFD-NEXT:    lui a1, %hi(.LCPI9_1)
 ; RV32IFD-NEXT:    fld fa5, %lo(.LCPI9_1)(a1)
 ; RV32IFD-NEXT:    flt.d a3, fa5, fs0
 ; RV32IFD-NEXT:    beqz a3, .LBB9_4
 ; RV32IFD-NEXT:  # %bb.3:
 ; RV32IFD-NEXT:    addi a2, a4, -1
 ; RV32IFD-NEXT:  .LBB9_4:
 ; RV32IFD-NEXT:    feq.d a1, fs0, fs0
 ; RV32IFD-NEXT:    neg a4, a1
 ; RV32IFD-NEXT:    and a1, a4, a2
 ; RV32IFD-NEXT:    neg a2, a3
-; RV32IFD-NEXT:    neg a3, s0
-; RV32IFD-NEXT:    and a0, a3, a0
+; RV32IFD-NEXT:    addi s0, s0, -1
+; RV32IFD-NEXT:    and a0, s0, a0
 ; RV32IFD-NEXT:    or a0, a2, a0
 ; RV32IFD-NEXT:    and a0, a4, a0
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;

 ; RV32IZFINXZDINX-NEXT:    call trunc@plt
 ; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s2, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s3, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    lui a2, %hi(.LCPI9_0)
 ; RV32IZFINXZDINX-NEXT:    lw a3, %lo(.LCPI9_0+4)(a2)
 ; RV32IZFINXZDINX-NEXT:    lw a2, %lo(.LCPI9_0)(a2)
-; RV32IZFINXZDINX-NEXT:    fle.d s0, a2, s2
+; RV32IZFINXZDINX-NEXT:    flt.d s0, s2, a2
 ; RV32IZFINXZDINX-NEXT:    call __fixdfdi@plt
 ; RV32IZFINXZDINX-NEXT:    lui a4, 524288
 ; RV32IZFINXZDINX-NEXT:    lui a2, 524288
-; RV32IZFINXZDINX-NEXT:    beqz s0, .LBB9_2
+; RV32IZFINXZDINX-NEXT:    bnez s0, .LBB9_2
 ; RV32IZFINXZDINX-NEXT:  # %bb.1:
 ; RV32IZFINXZDINX-NEXT:    mv a2, a1
 ; RV32IZFINXZDINX-NEXT:  .LBB9_2:
 ; RV32IZFINXZDINX-NEXT:    lui a1, %hi(.LCPI9_1)
 ; RV32IZFINXZDINX-NEXT:    lw a6, %lo(.LCPI9_1)(a1)
 ; RV32IZFINXZDINX-NEXT:    lw a7, %lo(.LCPI9_1+4)(a1)
 ; RV32IZFINXZDINX-NEXT:    flt.d a3, a6, s2
 ; RV32IZFINXZDINX-NEXT:    beqz a3, .LBB9_4
 ; RV32IZFINXZDINX-NEXT:  # %bb.3:
 ; RV32IZFINXZDINX-NEXT:    addi a2, a4, -1
 ; RV32IZFINXZDINX-NEXT:  .LBB9_4:
 ; RV32IZFINXZDINX-NEXT:    feq.d a1, s2, s2
 ; RV32IZFINXZDINX-NEXT:    neg a4, a1
 ; RV32IZFINXZDINX-NEXT:    and a1, a4, a2
-; RV32IZFINXZDINX-NEXT:    neg a2, s0
-; RV32IZFINXZDINX-NEXT:    and a0, a2, a0
+; RV32IZFINXZDINX-NEXT:    addi s0, s0, -1
+; RV32IZFINXZDINX-NEXT:    and a0, s0, a0
 ; RV32IZFINXZDINX-NEXT:    neg a2, a3
 ; RV32IZFINXZDINX-NEXT:    or a0, a2, a0
 ; RV32IZFINXZDINX-NEXT:    and a0, a4, a0
 ; RV32IZFINXZDINX-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s2, 20(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s3, 16(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, 32

 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    call trunc@plt
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI11_0)
 ; RV32IFD-NEXT:    fld fa5, %lo(.LCPI11_0)(a0)
 ; RV32IFD-NEXT:    flt.d a0, fa5, fa0
 ; RV32IFD-NEXT:    neg s0, a0
 ; RV32IFD-NEXT:    fcvt.d.w fa5, zero
-; RV32IFD-NEXT:    fle.d a0, fa5, fa0
-; RV32IFD-NEXT:    neg s1, a0
+; RV32IFD-NEXT:    flt.d a0, fa0, fa5
+; RV32IFD-NEXT:    addi s1, a0, -1
 ; RV32IFD-NEXT:    call __fixunsdfdi@plt
 ; RV32IFD-NEXT:    and a0, s1, a0
 ; RV32IFD-NEXT:    or a0, s0, a0
 ; RV32IFD-NEXT:    and a1, s1, a1
 ; RV32IFD-NEXT:    or a1, s0, a1
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload

 ; RV64IFD-NEXT:    ret
 ;
 ; RV32IZFINXZDINX-LABEL: test_trunc_ui64:
 ; RV32IZFINXZDINX:       # %bb.0:
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, -32
 ; RV32IZFINXZDINX-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    call trunc@plt
 ; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s0, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s1, 12(sp)
-; RV32IZFINXZDINX-NEXT:    fcvt.d.w a2, zero
-; RV32IZFINXZDINX-NEXT:    fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT:    neg s2, a2
 ; RV32IZFINXZDINX-NEXT:    call __fixunsdfdi@plt
-; RV32IZFINXZDINX-NEXT:    lui a2, %hi(.LCPI11_0)
-; RV32IZFINXZDINX-NEXT:    lw a3, %lo(.LCPI11_0+4)(a2)
-; RV32IZFINXZDINX-NEXT:    lw a2, %lo(.LCPI11_0)(a2)
-; RV32IZFINXZDINX-NEXT:    and a0, s2, a0
-; RV32IZFINXZDINX-NEXT:    flt.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT:    neg a2, a2
-; RV32IZFINXZDINX-NEXT:    or a0, a2, a0
-; RV32IZFINXZDINX-NEXT:    and a1, s2, a1
-; RV32IZFINXZDINX-NEXT:    or a1, a2, a1
+; RV32IZFINXZDINX-NEXT:    fcvt.d.w a2, zero
+; RV32IZFINXZDINX-NEXT:    lui a4, %hi(.LCPI11_0)
+; RV32IZFINXZDINX-NEXT:    lw a5, %lo(.LCPI11_0+4)(a4)
+; RV32IZFINXZDINX-NEXT:    lw a4, %lo(.LCPI11_0)(a4)
+; RV32IZFINXZDINX-NEXT:    flt.d a2, s0, a2
+; RV32IZFINXZDINX-NEXT:    addi a2, a2, -1
+; RV32IZFINXZDINX-NEXT:    and a0, a2, a0
+; RV32IZFINXZDINX-NEXT:    flt.d a3, a4, s0
+; RV32IZFINXZDINX-NEXT:    neg a3, a3
+; RV32IZFINXZDINX-NEXT:    or a0, a3, a0
+; RV32IZFINXZDINX-NEXT:    and a1, a2, a1
+; RV32IZFINXZDINX-NEXT:    or a1, a3, a1
 ; RV32IZFINXZDINX-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, 32
 ; RV32IZFINXZDINX-NEXT:    ret
 ;
 ; RV64IZFINXZDINX-LABEL: test_trunc_ui64:
 ; RV64IZFINXZDINX:       # %bb.0:
 ; RV64IZFINXZDINX-NEXT:    fcvt.lu.d a1, a0, rtz
 ; RV64IZFINXZDINX-NEXT:    feq.d a0, a0, a0
 ; RV64IZFINXZDINX-NEXT:    seqz a0, a0

 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    call round@plt
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI13_0)
 ; RV32IFD-NEXT:    fld fa5, %lo(.LCPI13_0)(a0)
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
-; RV32IFD-NEXT:    fle.d s0, fa5, fa0
+; RV32IFD-NEXT:    flt.d s0, fa0, fa5
 ; RV32IFD-NEXT:    call __fixdfdi@plt
 ; RV32IFD-NEXT:    lui a4, 524288
 ; RV32IFD-NEXT:    lui a2, 524288
-; RV32IFD-NEXT:    beqz s0, .LBB13_2
+; RV32IFD-NEXT:    bnez s0, .LBB13_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    mv a2, a1
 ; RV32IFD-NEXT:  .LBB13_2:
 ; RV32IFD-NEXT:    lui a1, %hi(.LCPI13_1)
 ; RV32IFD-NEXT:    fld fa5, %lo(.LCPI13_1)(a1)
 ; RV32IFD-NEXT:    flt.d a3, fa5, fs0
 ; RV32IFD-NEXT:    beqz a3, .LBB13_4
 ; RV32IFD-NEXT:  # %bb.3:
 ; RV32IFD-NEXT:    addi a2, a4, -1
 ; RV32IFD-NEXT:  .LBB13_4:
 ; RV32IFD-NEXT:    feq.d a1, fs0, fs0
 ; RV32IFD-NEXT:    neg a4, a1
 ; RV32IFD-NEXT:    and a1, a4, a2
 ; RV32IFD-NEXT:    neg a2, a3
-; RV32IFD-NEXT:    neg a3, s0
-; RV32IFD-NEXT:    and a0, a3, a0
+; RV32IFD-NEXT:    addi s0, s0, -1
+; RV32IFD-NEXT:    and a0, s0, a0
 ; RV32IFD-NEXT:    or a0, a2, a0
 ; RV32IFD-NEXT:    and a0, a4, a0
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;

 ; RV32IZFINXZDINX-NEXT:    call round@plt
 ; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s2, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s3, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    lui a2, %hi(.LCPI13_0)
 ; RV32IZFINXZDINX-NEXT:    lw a3, %lo(.LCPI13_0+4)(a2)
 ; RV32IZFINXZDINX-NEXT:    lw a2, %lo(.LCPI13_0)(a2)
-; RV32IZFINXZDINX-NEXT:    fle.d s0, a2, s2
+; RV32IZFINXZDINX-NEXT:    flt.d s0, s2, a2
 ; RV32IZFINXZDINX-NEXT:    call __fixdfdi@plt
 ; RV32IZFINXZDINX-NEXT:    lui a4, 524288
 ; RV32IZFINXZDINX-NEXT:    lui a2, 524288
-; RV32IZFINXZDINX-NEXT:    beqz s0, .LBB13_2
+; RV32IZFINXZDINX-NEXT:    bnez s0, .LBB13_2
 ; RV32IZFINXZDINX-NEXT:  # %bb.1:
 ; RV32IZFINXZDINX-NEXT:    mv a2, a1
 ; RV32IZFINXZDINX-NEXT:  .LBB13_2:
 ; RV32IZFINXZDINX-NEXT:    lui a1, %hi(.LCPI13_1)
 ; RV32IZFINXZDINX-NEXT:    lw a6, %lo(.LCPI13_1)(a1)
 ; RV32IZFINXZDINX-NEXT:    lw a7, %lo(.LCPI13_1+4)(a1)
 ; RV32IZFINXZDINX-NEXT:    flt.d a3, a6, s2
 ; RV32IZFINXZDINX-NEXT:    beqz a3, .LBB13_4
 ; RV32IZFINXZDINX-NEXT:  # %bb.3:
 ; RV32IZFINXZDINX-NEXT:    addi a2, a4, -1
 ; RV32IZFINXZDINX-NEXT:  .LBB13_4:
 ; RV32IZFINXZDINX-NEXT:    feq.d a1, s2, s2
 ; RV32IZFINXZDINX-NEXT:    neg a4, a1
 ; RV32IZFINXZDINX-NEXT:    and a1, a4, a2
-; RV32IZFINXZDINX-NEXT:    neg a2, s0
-; RV32IZFINXZDINX-NEXT:    and a0, a2, a0
+; RV32IZFINXZDINX-NEXT:    addi s0, s0, -1
+; RV32IZFINXZDINX-NEXT:    and a0, s0, a0
 ; RV32IZFINXZDINX-NEXT:    neg a2, a3
 ; RV32IZFINXZDINX-NEXT:    or a0, a2, a0
 ; RV32IZFINXZDINX-NEXT:    and a0, a4, a0
 ; RV32IZFINXZDINX-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s2, 20(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s3, 16(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, 32

 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    call round@plt
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI15_0)
 ; RV32IFD-NEXT:    fld fa5, %lo(.LCPI15_0)(a0)
 ; RV32IFD-NEXT:    flt.d a0, fa5, fa0
 ; RV32IFD-NEXT:    neg s0, a0
 ; RV32IFD-NEXT:    fcvt.d.w fa5, zero
-; RV32IFD-NEXT:    fle.d a0, fa5, fa0
-; RV32IFD-NEXT:    neg s1, a0
+; RV32IFD-NEXT:    flt.d a0, fa0, fa5
+; RV32IFD-NEXT:    addi s1, a0, -1
 ; RV32IFD-NEXT:    call __fixunsdfdi@plt
 ; RV32IFD-NEXT:    and a0, s1, a0
 ; RV32IFD-NEXT:    or a0, s0, a0
 ; RV32IFD-NEXT:    and a1, s1, a1
 ; RV32IFD-NEXT:    or a1, s0, a1
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload

 ; RV64IFD-NEXT:    ret
 ;
 ; RV32IZFINXZDINX-LABEL: test_round_ui64:
 ; RV32IZFINXZDINX:       # %bb.0:
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, -32
 ; RV32IZFINXZDINX-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    call round@plt
 ; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s0, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s1, 12(sp)
-; RV32IZFINXZDINX-NEXT:    fcvt.d.w a2, zero
-; RV32IZFINXZDINX-NEXT:    fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT:    neg s2, a2
 ; RV32IZFINXZDINX-NEXT:    call __fixunsdfdi@plt
-; RV32IZFINXZDINX-NEXT:    lui a2, %hi(.LCPI15_0)
-; RV32IZFINXZDINX-NEXT:    lw a3, %lo(.LCPI15_0+4)(a2)
-; RV32IZFINXZDINX-NEXT:    lw a2, %lo(.LCPI15_0)(a2)
-; RV32IZFINXZDINX-NEXT:    and a0, s2, a0
-; RV32IZFINXZDINX-NEXT:    flt.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT:    neg a2, a2
-; RV32IZFINXZDINX-NEXT:    or a0, a2, a0
-; RV32IZFINXZDINX-NEXT:    and a1, s2, a1
-; RV32IZFINXZDINX-NEXT:    or a1, a2, a1
+; RV32IZFINXZDINX-NEXT:    fcvt.d.w a2, zero
+; RV32IZFINXZDINX-NEXT:    lui a4, %hi(.LCPI15_0)
+; RV32IZFINXZDINX-NEXT:    lw a5, %lo(.LCPI15_0+4)(a4)
+; RV32IZFINXZDINX-NEXT:    lw a4, %lo(.LCPI15_0)(a4)
+; RV32IZFINXZDINX-NEXT:    flt.d a2, s0, a2
+; RV32IZFINXZDINX-NEXT:    addi a2, a2, -1
+; RV32IZFINXZDINX-NEXT:    and a0, a2, a0
+; RV32IZFINXZDINX-NEXT:    flt.d a3, a4, s0
+; RV32IZFINXZDINX-NEXT:    neg a3, a3
+; RV32IZFINXZDINX-NEXT:    or a0, a3, a0
+; RV32IZFINXZDINX-NEXT:    and a1, a2, a1
+; RV32IZFINXZDINX-NEXT:    or a1, a3, a1
 ; RV32IZFINXZDINX-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, 32
 ; RV32IZFINXZDINX-NEXT:    ret
 ;
 ; RV64IZFINXZDINX-LABEL: test_round_ui64:
 ; RV64IZFINXZDINX:       # %bb.0:
 ; RV64IZFINXZDINX-NEXT:    fcvt.lu.d a1, a0, rmm
 ; RV64IZFINXZDINX-NEXT:    feq.d a0, a0, a0
 ; RV64IZFINXZDINX-NEXT:    seqz a0, a0

 ; RV32IFD-NEXT:    addi sp, sp, -16
 ; RV32IFD-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IFD-NEXT:    call roundeven@plt
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI17_0)
 ; RV32IFD-NEXT:    fld fa5, %lo(.LCPI17_0)(a0)
 ; RV32IFD-NEXT:    fmv.d fs0, fa0
-; RV32IFD-NEXT:    fle.d s0, fa5, fa0
+; RV32IFD-NEXT:    flt.d s0, fa0, fa5
 ; RV32IFD-NEXT:    call __fixdfdi@plt
 ; RV32IFD-NEXT:    lui a4, 524288
 ; RV32IFD-NEXT:    lui a2, 524288
-; RV32IFD-NEXT:    beqz s0, .LBB17_2
+; RV32IFD-NEXT:    bnez s0, .LBB17_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    mv a2, a1
 ; RV32IFD-NEXT:  .LBB17_2:
 ; RV32IFD-NEXT:    lui a1, %hi(.LCPI17_1)
 ; RV32IFD-NEXT:    fld fa5, %lo(.LCPI17_1)(a1)
 ; RV32IFD-NEXT:    flt.d a3, fa5, fs0
 ; RV32IFD-NEXT:    beqz a3, .LBB17_4
 ; RV32IFD-NEXT:  # %bb.3:
 ; RV32IFD-NEXT:    addi a2, a4, -1
 ; RV32IFD-NEXT:  .LBB17_4:
 ; RV32IFD-NEXT:    feq.d a1, fs0, fs0
 ; RV32IFD-NEXT:    neg a4, a1
 ; RV32IFD-NEXT:    and a1, a4, a2
 ; RV32IFD-NEXT:    neg a2, a3
-; RV32IFD-NEXT:    neg a3, s0
-; RV32IFD-NEXT:    and a0, a3, a0
+; RV32IFD-NEXT:    addi s0, s0, -1
+; RV32IFD-NEXT:    and a0, s0, a0
 ; RV32IFD-NEXT:    or a0, a2, a0
 ; RV32IFD-NEXT:    and a0, a4, a0
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;

 ; RV32IZFINXZDINX-NEXT:    call roundeven@plt
 ; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s2, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s3, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    lui a2, %hi(.LCPI17_0)
 ; RV32IZFINXZDINX-NEXT:    lw a3, %lo(.LCPI17_0+4)(a2)
 ; RV32IZFINXZDINX-NEXT:    lw a2, %lo(.LCPI17_0)(a2)
-; RV32IZFINXZDINX-NEXT:    fle.d s0, a2, s2
+; RV32IZFINXZDINX-NEXT:    flt.d s0, s2, a2
 ; RV32IZFINXZDINX-NEXT:    call __fixdfdi@plt
 ; RV32IZFINXZDINX-NEXT:    lui a4, 524288
 ; RV32IZFINXZDINX-NEXT:    lui a2, 524288
-; RV32IZFINXZDINX-NEXT:    beqz s0, .LBB17_2
+; RV32IZFINXZDINX-NEXT:    bnez s0, .LBB17_2
 ; RV32IZFINXZDINX-NEXT:  # %bb.1:
 ; RV32IZFINXZDINX-NEXT:    mv a2, a1
 ; RV32IZFINXZDINX-NEXT:  .LBB17_2:
 ; RV32IZFINXZDINX-NEXT:    lui a1, %hi(.LCPI17_1)
 ; RV32IZFINXZDINX-NEXT:    lw a6, %lo(.LCPI17_1)(a1)
 ; RV32IZFINXZDINX-NEXT:    lw a7, %lo(.LCPI17_1+4)(a1)
 ; RV32IZFINXZDINX-NEXT:    flt.d a3, a6, s2
 ; RV32IZFINXZDINX-NEXT:    beqz a3, .LBB17_4
 ; RV32IZFINXZDINX-NEXT:  # %bb.3:
 ; RV32IZFINXZDINX-NEXT:    addi a2, a4, -1
 ; RV32IZFINXZDINX-NEXT:  .LBB17_4:
 ; RV32IZFINXZDINX-NEXT:    feq.d a1, s2, s2
 ; RV32IZFINXZDINX-NEXT:    neg a4, a1
 ; RV32IZFINXZDINX-NEXT:    and a1, a4, a2
-; RV32IZFINXZDINX-NEXT:    neg a2, s0
-; RV32IZFINXZDINX-NEXT:    and a0, a2, a0
+; RV32IZFINXZDINX-NEXT:    addi s0, s0, -1
+; RV32IZFINXZDINX-NEXT:    and a0, s0, a0
 ; RV32IZFINXZDINX-NEXT:    neg a2, a3
 ; RV32IZFINXZDINX-NEXT:    or a0, a2, a0
 ; RV32IZFINXZDINX-NEXT:    and a0, a4, a0
 ; RV32IZFINXZDINX-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s2, 20(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s3, 16(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, 32

 ; RV32IFD-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IFD-NEXT:    call roundeven@plt
 ; RV32IFD-NEXT:    lui a0, %hi(.LCPI19_0)
 ; RV32IFD-NEXT:    fld fa5, %lo(.LCPI19_0)(a0)
 ; RV32IFD-NEXT:    flt.d a0, fa5, fa0
 ; RV32IFD-NEXT:    neg s0, a0
 ; RV32IFD-NEXT:    fcvt.d.w fa5, zero
-; RV32IFD-NEXT:    fle.d a0, fa5, fa0
-; RV32IFD-NEXT:    neg s1, a0
+; RV32IFD-NEXT:    flt.d a0, fa0, fa5
+; RV32IFD-NEXT:    addi s1, a0, -1
 ; RV32IFD-NEXT:    call __fixunsdfdi@plt
 ; RV32IFD-NEXT:    and a0, s1, a0
 ; RV32IFD-NEXT:    or a0, s0, a0
 ; RV32IFD-NEXT:    and a1, s1, a1
 ; RV32IFD-NEXT:    or a1, s0, a1
 ; RV32IFD-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload

 ; RV64IFD-NEXT:    ret
 ;
 ; RV32IZFINXZDINX-LABEL: test_roundeven_ui64:
 ; RV32IZFINXZDINX:       # %bb.0:
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, -32
 ; RV32IZFINXZDINX-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
-; RV32IZFINXZDINX-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32IZFINXZDINX-NEXT:    call roundeven@plt
 ; RV32IZFINXZDINX-NEXT:    sw a0, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s0, 8(sp)
 ; RV32IZFINXZDINX-NEXT:    lw s1, 12(sp)
-; RV32IZFINXZDINX-NEXT:    fcvt.d.w a2, zero
-; RV32IZFINXZDINX-NEXT:    fle.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT:    neg s2, a2
 ; RV32IZFINXZDINX-NEXT:    call __fixunsdfdi@plt
-; RV32IZFINXZDINX-NEXT:    lui a2, %hi(.LCPI19_0)
-; RV32IZFINXZDINX-NEXT:    lw a3, %lo(.LCPI19_0+4)(a2)
-; RV32IZFINXZDINX-NEXT:    lw a2, %lo(.LCPI19_0)(a2)
-; RV32IZFINXZDINX-NEXT:    and a0, s2, a0
-; RV32IZFINXZDINX-NEXT:    flt.d a2, a2, s0
-; RV32IZFINXZDINX-NEXT:    neg a2, a2
-; RV32IZFINXZDINX-NEXT:    or a0, a2, a0
-; RV32IZFINXZDINX-NEXT:    and a1, s2, a1
-; RV32IZFINXZDINX-NEXT:    or a1, a2, a1
+; RV32IZFINXZDINX-NEXT:    fcvt.d.w a2, zero
+; RV32IZFINXZDINX-NEXT:    lui a4, %hi(.LCPI19_0)
+; RV32IZFINXZDINX-NEXT:    lw a5, %lo(.LCPI19_0+4)(a4)
+; RV32IZFINXZDINX-NEXT:    lw a4, %lo(.LCPI19_0)(a4)
+; RV32IZFINXZDINX-NEXT:    flt.d a2, s0, a2
+; RV32IZFINXZDINX-NEXT:    addi a2, a2, -1
+; RV32IZFINXZDINX-NEXT:    and a0, a2, a0
+; RV32IZFINXZDINX-NEXT:    flt.d a3, a4, s0
+; RV32IZFINXZDINX-NEXT:    neg a3, a3
+; RV32IZFINXZDINX-NEXT:    or a0, a3, a0
+; RV32IZFINXZDINX-NEXT:    and a1, a2, a1
+; RV32IZFINXZDINX-NEXT:    or a1, a3, a1
 ; RV32IZFINXZDINX-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
-; RV32IZFINXZDINX-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
 ; RV32IZFINXZDINX-NEXT:    addi sp, sp, 32
 ; RV32IZFINXZDINX-NEXT:    ret
 ;
 ; RV64IZFINXZDINX-LABEL: test_roundeven_ui64:
 ; RV64IZFINXZDINX:       # %bb.0:
 ; RV64IZFINXZDINX-NEXT:    fcvt.lu.d a1, a0, rne
 ; RV64IZFINXZDINX-NEXT:    feq.d a0, a0, a0
 ; RV64IZFINXZDINX-NEXT:    seqz a0, a0

llvm/test/CodeGen/RISCV/double-select-fcmp.ll

; CHECKRV64ZDINX-NEXT:    ret
   %1 = fcmp ueq double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 define double @select_fcmp_ugt(double %a, double %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ugt:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fle.d a0, fa0, fa1
-; CHECK-NEXT:    beqz a0, .LBB9_2
+; CHECK-NEXT:    flt.d a0, fa1, fa0
+; CHECK-NEXT:    bnez a0, .LBB9_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.d fa0, fa1
 ; CHECK-NEXT:  .LBB9_2:
 ; CHECK-NEXT:    ret
 ;
 ; CHECKRV32ZDINX-LABEL: select_fcmp_ugt:
 ; CHECKRV32ZDINX:       # %bb.0:
 ; CHECKRV32ZDINX-NEXT:    addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT:    sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT:    sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT:    lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT:    lw a3, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    sw a0, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    sw a1, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a0, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT:    fle.d a4, a0, a2
-; CHECKRV32ZDINX-NEXT:    beqz a4, .LBB9_2
+; CHECKRV32ZDINX-NEXT:    sw a2, 8(sp)
+; CHECKRV32ZDINX-NEXT:    sw a3, 12(sp)
+; CHECKRV32ZDINX-NEXT:    lw a2, 8(sp)
+; CHECKRV32ZDINX-NEXT:    lw a3, 12(sp)
+; CHECKRV32ZDINX-NEXT:    flt.d a4, a2, a0
+; CHECKRV32ZDINX-NEXT:    bnez a4, .LBB9_2
 ; CHECKRV32ZDINX-NEXT:  # %bb.1:
 ; CHECKRV32ZDINX-NEXT:    mv a0, a2
 ; CHECKRV32ZDINX-NEXT:  .LBB9_2:
 ; CHECKRV32ZDINX-NEXT:    sw a0, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    sw a1, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a0, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a1, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    addi sp, sp, 16
 ; CHECKRV32ZDINX-NEXT:    ret
 ;
 ; CHECKRV64ZDINX-LABEL: select_fcmp_ugt:
 ; CHECKRV64ZDINX:       # %bb.0:
-; CHECKRV64ZDINX-NEXT:    fle.d a2, a0, a1
-; CHECKRV64ZDINX-NEXT:    beqz a2, .LBB9_2
+; CHECKRV64ZDINX-NEXT:    flt.d a2, a1, a0
+; CHECKRV64ZDINX-NEXT:    bnez a2, .LBB9_2
 ; CHECKRV64ZDINX-NEXT:  # %bb.1:
 ; CHECKRV64ZDINX-NEXT:    mv a0, a1
 ; CHECKRV64ZDINX-NEXT:  .LBB9_2:
 ; CHECKRV64ZDINX-NEXT:    ret
   %1 = fcmp ugt double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 define double @select_fcmp_uge(double %a, double %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    flt.d a0, fa0, fa1
-; CHECK-NEXT:    beqz a0, .LBB10_2
+; CHECK-NEXT:    fle.d a0, fa1, fa0
+; CHECK-NEXT:    bnez a0, .LBB10_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.d fa0, fa1
 ; CHECK-NEXT:  .LBB10_2:
 ; CHECK-NEXT:    ret
 ;
 ; CHECKRV32ZDINX-LABEL: select_fcmp_uge:
 ; CHECKRV32ZDINX:       # %bb.0:
 ; CHECKRV32ZDINX-NEXT:    addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT:    sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT:    sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT:    lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT:    lw a3, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    sw a0, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    sw a1, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a0, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT:    flt.d a4, a0, a2
-; CHECKRV32ZDINX-NEXT:    beqz a4, .LBB10_2
+; CHECKRV32ZDINX-NEXT:    sw a2, 8(sp)
+; CHECKRV32ZDINX-NEXT:    sw a3, 12(sp)
+; CHECKRV32ZDINX-NEXT:    lw a2, 8(sp)
+; CHECKRV32ZDINX-NEXT:    lw a3, 12(sp)
+; CHECKRV32ZDINX-NEXT:    fle.d a4, a2, a0
+; CHECKRV32ZDINX-NEXT:    bnez a4, .LBB10_2
 ; CHECKRV32ZDINX-NEXT:  # %bb.1:
 ; CHECKRV32ZDINX-NEXT:    mv a0, a2
 ; CHECKRV32ZDINX-NEXT:  .LBB10_2:
 ; CHECKRV32ZDINX-NEXT:    sw a0, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    sw a1, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a0, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a1, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    addi sp, sp, 16
 ; CHECKRV32ZDINX-NEXT:    ret
 ;
 ; CHECKRV64ZDINX-LABEL: select_fcmp_uge:
 ; CHECKRV64ZDINX:       # %bb.0:
-; CHECKRV64ZDINX-NEXT:    flt.d a2, a0, a1
-; CHECKRV64ZDINX-NEXT:    beqz a2, .LBB10_2
+; CHECKRV64ZDINX-NEXT:    fle.d a2, a1, a0
+; CHECKRV64ZDINX-NEXT:    bnez a2, .LBB10_2
 ; CHECKRV64ZDINX-NEXT:  # %bb.1:
 ; CHECKRV64ZDINX-NEXT:    mv a0, a1
 ; CHECKRV64ZDINX-NEXT:  .LBB10_2:
 ; CHECKRV64ZDINX-NEXT:    ret
   %1 = fcmp uge double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 define double @select_fcmp_ult(double %a, double %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ult:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fle.d a0, fa1, fa0
-; CHECK-NEXT:    beqz a0, .LBB11_2
+; CHECK-NEXT:    flt.d a0, fa0, fa1
+; CHECK-NEXT:    bnez a0, .LBB11_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.d fa0, fa1
 ; CHECK-NEXT:  .LBB11_2:
 ; CHECK-NEXT:    ret
 ;
 ; CHECKRV32ZDINX-LABEL: select_fcmp_ult:
 ; CHECKRV32ZDINX:       # %bb.0:
 ; CHECKRV32ZDINX-NEXT:    addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT:    sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT:    sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT:    lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT:    lw a1, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    sw a2, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    sw a3, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a2, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT:    fle.d a4, a2, a0
-; CHECKRV32ZDINX-NEXT:    beqz a4, .LBB11_2
+; CHECKRV32ZDINX-NEXT:    sw a0, 8(sp)
+; CHECKRV32ZDINX-NEXT:    sw a1, 12(sp)
+; CHECKRV32ZDINX-NEXT:    lw a0, 8(sp)
+; CHECKRV32ZDINX-NEXT:    lw a1, 12(sp)
+; CHECKRV32ZDINX-NEXT:    flt.d a4, a0, a2
+; CHECKRV32ZDINX-NEXT:    bnez a4, .LBB11_2
 ; CHECKRV32ZDINX-NEXT:  # %bb.1:
 ; CHECKRV32ZDINX-NEXT:    mv a0, a2
 ; CHECKRV32ZDINX-NEXT:  .LBB11_2:
 ; CHECKRV32ZDINX-NEXT:    sw a0, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    sw a1, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a0, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a1, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    addi sp, sp, 16
 ; CHECKRV32ZDINX-NEXT:    ret
 ;
 ; CHECKRV64ZDINX-LABEL: select_fcmp_ult:
 ; CHECKRV64ZDINX:       # %bb.0:
-; CHECKRV64ZDINX-NEXT:    fle.d a2, a1, a0
-; CHECKRV64ZDINX-NEXT:    beqz a2, .LBB11_2
+; CHECKRV64ZDINX-NEXT:    flt.d a2, a0, a1
+; CHECKRV64ZDINX-NEXT:    bnez a2, .LBB11_2
 ; CHECKRV64ZDINX-NEXT:  # %bb.1:
 ; CHECKRV64ZDINX-NEXT:    mv a0, a1
 ; CHECKRV64ZDINX-NEXT:  .LBB11_2:
 ; CHECKRV64ZDINX-NEXT:    ret
   %1 = fcmp ult double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
 
 define double @select_fcmp_ule(double %a, double %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ule:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    flt.d a0, fa1, fa0
-; CHECK-NEXT:    beqz a0, .LBB12_2
+; CHECK-NEXT:    fle.d a0, fa0, fa1
+; CHECK-NEXT:    bnez a0, .LBB12_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.d fa0, fa1
 ; CHECK-NEXT:  .LBB12_2:
 ; CHECK-NEXT:    ret
 ;
 ; CHECKRV32ZDINX-LABEL: select_fcmp_ule:
 ; CHECKRV32ZDINX:       # %bb.0:
 ; CHECKRV32ZDINX-NEXT:    addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT:    sw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT:    sw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT:    lw a0, 8(sp)
-; CHECKRV32ZDINX-NEXT:    lw a1, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    sw a2, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    sw a3, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a2, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT:    flt.d a4, a2, a0
-; CHECKRV32ZDINX-NEXT:    beqz a4, .LBB12_2
+; CHECKRV32ZDINX-NEXT:    sw a0, 8(sp)
+; CHECKRV32ZDINX-NEXT:    sw a1, 12(sp)
+; CHECKRV32ZDINX-NEXT:    lw a0, 8(sp)
+; CHECKRV32ZDINX-NEXT:    lw a1, 12(sp)
+; CHECKRV32ZDINX-NEXT:    fle.d a4, a0, a2
+; CHECKRV32ZDINX-NEXT:    bnez a4, .LBB12_2
 ; CHECKRV32ZDINX-NEXT:  # %bb.1:
 ; CHECKRV32ZDINX-NEXT:    mv a0, a2
 ; CHECKRV32ZDINX-NEXT:  .LBB12_2:
 ; CHECKRV32ZDINX-NEXT:    sw a0, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    sw a1, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a0, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a1, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    addi sp, sp, 16
 ; CHECKRV32ZDINX-NEXT:    ret
 ;
 ; CHECKRV64ZDINX-LABEL: select_fcmp_ule:
 ; CHECKRV64ZDINX:       # %bb.0:
-; CHECKRV64ZDINX-NEXT:    flt.d a2, a1, a0
-; CHECKRV64ZDINX-NEXT:    beqz a2, .LBB12_2
+; CHECKRV64ZDINX-NEXT:    fle.d a2, a0, a1
+; CHECKRV64ZDINX-NEXT:    bnez a2, .LBB12_2
 ; CHECKRV64ZDINX-NEXT:  # %bb.1:
 ; CHECKRV64ZDINX-NEXT:    mv a0, a1
 ; CHECKRV64ZDINX-NEXT:  .LBB12_2:
 ; CHECKRV64ZDINX-NEXT:    ret
   %1 = fcmp ule double %a, %b
   %2 = select i1 %1, double %a, double %b
   ret double %2
 }
; CHECKRV64ZDINX-NEXT:    ret
   %1 = fcmp fast oeq double %a, %b
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }
 
 define signext i32 @select_fcmp_uge_negone_zero(double %a, double %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge_negone_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fle.d a0, fa0, fa1
-; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    flt.d a0, fa1, fa0
+; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
 ;
 ; CHECKRV32ZDINX-LABEL: select_fcmp_uge_negone_zero:
 ; CHECKRV32ZDINX:       # %bb.0:
 ; CHECKRV32ZDINX-NEXT:    addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT:    sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT:    sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT:    lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT:    lw a3, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    sw a0, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    sw a1, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a0, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT:    fle.d a0, a0, a2
-; CHECKRV32ZDINX-NEXT:    addi a0, a0, -1
+; CHECKRV32ZDINX-NEXT:    sw a2, 8(sp)
+; CHECKRV32ZDINX-NEXT:    sw a3, 12(sp)
+; CHECKRV32ZDINX-NEXT:    lw a2, 8(sp)
+; CHECKRV32ZDINX-NEXT:    lw a3, 12(sp)
+; CHECKRV32ZDINX-NEXT:    flt.d a0, a2, a0
+; CHECKRV32ZDINX-NEXT:    neg a0, a0
 ; CHECKRV32ZDINX-NEXT:    addi sp, sp, 16
 ; CHECKRV32ZDINX-NEXT:    ret
 ;
 ; CHECKRV64ZDINX-LABEL: select_fcmp_uge_negone_zero:
 ; CHECKRV64ZDINX:       # %bb.0:
-; CHECKRV64ZDINX-NEXT:    fle.d a0, a0, a1
-; CHECKRV64ZDINX-NEXT:    addi a0, a0, -1
+; CHECKRV64ZDINX-NEXT:    flt.d a0, a1, a0
+; CHECKRV64ZDINX-NEXT:    neg a0, a0
 ; CHECKRV64ZDINX-NEXT:    ret
   %1 = fcmp ugt double %a, %b
   %2 = select i1 %1, i32 -1, i32 0
   ret i32 %2
 }
 
 define signext i32 @select_fcmp_uge_1_2(double %a, double %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge_1_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fle.d a0, fa0, fa1
-; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    flt.d a0, fa1, fa0
+; CHECK-NEXT:    li a1, 2
+; CHECK-NEXT:    sub a0, a1, a0
 ; CHECK-NEXT:    ret
 ;
 ; CHECKRV32ZDINX-LABEL: select_fcmp_uge_1_2:
 ; CHECKRV32ZDINX:       # %bb.0:
 ; CHECKRV32ZDINX-NEXT:    addi sp, sp, -16
-; CHECKRV32ZDINX-NEXT:    sw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT:    sw a3, 12(sp)
-; CHECKRV32ZDINX-NEXT:    lw a2, 8(sp)
-; CHECKRV32ZDINX-NEXT:    lw a3, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    sw a0, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    sw a1, 12(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a0, 8(sp)
 ; CHECKRV32ZDINX-NEXT:    lw a1, 12(sp)
-; CHECKRV32ZDINX-NEXT:    fle.d a0, a0, a2
-; CHECKRV32ZDINX-NEXT:    addi a0, a0, 1
+; CHECKRV32ZDINX-NEXT:    sw a2, 8(sp)
+; CHECKRV32ZDINX-NEXT:    sw a3, 12(sp)
+; CHECKRV32ZDINX-NEXT:    lw a2, 8(sp)
+; CHECKRV32ZDINX-NEXT:    lw a3, 12(sp)
+; CHECKRV32ZDINX-NEXT:    flt.d a0, a2, a0
+; CHECKRV32ZDINX-NEXT:    li a1, 2
+; CHECKRV32ZDINX-NEXT:    sub a0, a1, a0
 ; CHECKRV32ZDINX-NEXT:    addi sp, sp, 16
 ; CHECKRV32ZDINX-NEXT:    ret
 ;
 ; CHECKRV64ZDINX-LABEL: select_fcmp_uge_1_2:
 ; CHECKRV64ZDINX:       # %bb.0:
-; CHECKRV64ZDINX-NEXT:    fle.d a0, a0, a1
-; CHECKRV64ZDINX-NEXT:    addi a0, a0, 1
+; CHECKRV64ZDINX-NEXT:    flt.d a0, a1, a0
+; CHECKRV64ZDINX-NEXT:    li a1, 2
+; CHECKRV64ZDINX-NEXT:    sub a0, a1, a0
 ; CHECKRV64ZDINX-NEXT:    ret
   %1 = fcmp ugt double %a, %b
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/double-select-icmp.ll

; RV64ZDINX-NEXT:    ret
   %1 = icmp slt i32 %a, 1
   %2 = select i1 %1, double 1.000000e+00, double 0.000000e+00
   ret double %2
 }
 
 define double @select_icmp_sgt_zero(i32 signext %a) {
 ; CHECK-LABEL: select_icmp_sgt_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sgtz a0, a0
-; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    slti a0, a0, 1
 ; CHECK-NEXT:    fcvt.d.w fa0, a0
 ; CHECK-NEXT:    ret
 ;
 ; RV32ZDINX-LABEL: select_icmp_sgt_zero:
 ; RV32ZDINX:       # %bb.0:
 ; RV32ZDINX-NEXT:    addi sp, sp, -16
 ; RV32ZDINX-NEXT:    .cfi_def_cfa_offset 16
-; RV32ZDINX-NEXT:    sgtz a0, a0
-; RV32ZDINX-NEXT:    xori a0, a0, 1
+; RV32ZDINX-NEXT:    slti a0, a0, 1
 ; RV32ZDINX-NEXT:    fcvt.d.w a0, a0
 ; RV32ZDINX-NEXT:    sw a0, 8(sp)
 ; RV32ZDINX-NEXT:    sw a1, 12(sp)
 ; RV32ZDINX-NEXT:    lw a0, 8(sp)
 ; RV32ZDINX-NEXT:    lw a1, 12(sp)
 ; RV32ZDINX-NEXT:    addi sp, sp, 16
 ; RV32ZDINX-NEXT:    ret
 ;
 ; RV64ZDINX-LABEL: select_icmp_sgt_zero:
 ; RV64ZDINX:       # %bb.0:
-; RV64ZDINX-NEXT:    sgtz a0, a0
-; RV64ZDINX-NEXT:    xori a0, a0, 1
+; RV64ZDINX-NEXT:    slti a0, a0, 1
 ; RV64ZDINX-NEXT:    fcvt.d.w a0, a0
 ; RV64ZDINX-NEXT:    ret
   %1 = icmp sgt i32 %a, 0
   %2 = select i1 %1, double 0.000000e+00, double 1.000000e+00
   ret double %2
 }
 

llvm/test/CodeGen/RISCV/float-br-fcmp.ll

 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_ugt(float %a, float %b) nounwind {
 ; RV32IF-LABEL: br_fcmp_ugt:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa0, fa1
-; RV32IF-NEXT:    beqz a0, .LBB10_2
+; RV32IF-NEXT:    flt.s a0, fa1, fa0
+; RV32IF-NEXT:    bnez a0, .LBB10_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB10_2: # %if.then
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call abort@plt
 ;
 ; RV64IF-LABEL: br_fcmp_ugt:
 ; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa0, fa1
-; RV64IF-NEXT:    beqz a0, .LBB10_2
+; RV64IF-NEXT:    flt.s a0, fa1, fa0
+; RV64IF-NEXT:    bnez a0, .LBB10_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB10_2: # %if.then
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call abort@plt
 ;
 ; RV32IZFINX-LABEL: br_fcmp_ugt:
 ; RV32IZFINX:       # %bb.0:
-; RV32IZFINX-NEXT:    fle.s a0, a0, a1
-; RV32IZFINX-NEXT:    beqz a0, .LBB10_2
+; RV32IZFINX-NEXT:    flt.s a0, a1, a0
+; RV32IZFINX-NEXT:    bnez a0, .LBB10_2
 ; RV32IZFINX-NEXT:  # %bb.1: # %if.else
 ; RV32IZFINX-NEXT:    ret
 ; RV32IZFINX-NEXT:  .LBB10_2: # %if.then
 ; RV32IZFINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    call abort@plt
 ;
 ; RV64IZFINX-LABEL: br_fcmp_ugt:
 ; RV64IZFINX:       # %bb.0:
-; RV64IZFINX-NEXT:    fle.s a0, a0, a1
-; RV64IZFINX-NEXT:    beqz a0, .LBB10_2
+; RV64IZFINX-NEXT:    flt.s a0, a1, a0
+; RV64IZFINX-NEXT:    bnez a0, .LBB10_2
 ; RV64IZFINX-NEXT:  # %bb.1: # %if.else
 ; RV64IZFINX-NEXT:    ret
 ; RV64IZFINX-NEXT:  .LBB10_2: # %if.then
 ; RV64IZFINX-NEXT:    addi sp, sp, -16
 ; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp ugt float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_uge(float %a, float %b) nounwind {
 ; RV32IF-LABEL: br_fcmp_uge:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa0, fa1
-; RV32IF-NEXT:    beqz a0, .LBB11_2
+; RV32IF-NEXT:    fle.s a0, fa1, fa0
+; RV32IF-NEXT:    bnez a0, .LBB11_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB11_2: # %if.then
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call abort@plt
 ;
 ; RV64IF-LABEL: br_fcmp_uge:
 ; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa0, fa1
-; RV64IF-NEXT:    beqz a0, .LBB11_2
+; RV64IF-NEXT:    fle.s a0, fa1, fa0
+; RV64IF-NEXT:    bnez a0, .LBB11_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB11_2: # %if.then
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call abort@plt
 ;
 ; RV32IZFINX-LABEL: br_fcmp_uge:
 ; RV32IZFINX:       # %bb.0:
-; RV32IZFINX-NEXT:    flt.s a0, a0, a1
-; RV32IZFINX-NEXT:    beqz a0, .LBB11_2
+; RV32IZFINX-NEXT:    fle.s a0, a1, a0
+; RV32IZFINX-NEXT:    bnez a0, .LBB11_2
 ; RV32IZFINX-NEXT:  # %bb.1: # %if.else
 ; RV32IZFINX-NEXT:    ret
 ; RV32IZFINX-NEXT:  .LBB11_2: # %if.then
 ; RV32IZFINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    call abort@plt
 ;
 ; RV64IZFINX-LABEL: br_fcmp_uge:
 ; RV64IZFINX:       # %bb.0:
-; RV64IZFINX-NEXT:    flt.s a0, a0, a1
-; RV64IZFINX-NEXT:    beqz a0, .LBB11_2
+; RV64IZFINX-NEXT:    fle.s a0, a1, a0
+; RV64IZFINX-NEXT:    bnez a0, .LBB11_2
 ; RV64IZFINX-NEXT:  # %bb.1: # %if.else
 ; RV64IZFINX-NEXT:    ret
 ; RV64IZFINX-NEXT:  .LBB11_2: # %if.then
 ; RV64IZFINX-NEXT:    addi sp, sp, -16
 ; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp uge float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_ult(float %a, float %b) nounwind {
 ; RV32IF-LABEL: br_fcmp_ult:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    fle.s a0, fa1, fa0
-; RV32IF-NEXT:    beqz a0, .LBB12_2
+; RV32IF-NEXT:    flt.s a0, fa0, fa1
+; RV32IF-NEXT:    bnez a0, .LBB12_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB12_2: # %if.then
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call abort@plt
 ;
 ; RV64IF-LABEL: br_fcmp_ult:
 ; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    fle.s a0, fa1, fa0
-; RV64IF-NEXT:    beqz a0, .LBB12_2
+; RV64IF-NEXT:    flt.s a0, fa0, fa1
+; RV64IF-NEXT:    bnez a0, .LBB12_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB12_2: # %if.then
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call abort@plt
 ;
 ; RV32IZFINX-LABEL: br_fcmp_ult:
 ; RV32IZFINX:       # %bb.0:
-; RV32IZFINX-NEXT:    fle.s a0, a1, a0
-; RV32IZFINX-NEXT:    beqz a0, .LBB12_2
+; RV32IZFINX-NEXT:    flt.s a0, a0, a1
+; RV32IZFINX-NEXT:    bnez a0, .LBB12_2
 ; RV32IZFINX-NEXT:  # %bb.1: # %if.else
 ; RV32IZFINX-NEXT:    ret
 ; RV32IZFINX-NEXT:  .LBB12_2: # %if.then
 ; RV32IZFINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    call abort@plt
 ;
 ; RV64IZFINX-LABEL: br_fcmp_ult:
 ; RV64IZFINX:       # %bb.0:
-; RV64IZFINX-NEXT:    fle.s a0, a1, a0
-; RV64IZFINX-NEXT:    beqz a0, .LBB12_2
+; RV64IZFINX-NEXT:    flt.s a0, a0, a1
+; RV64IZFINX-NEXT:    bnez a0, .LBB12_2
 ; RV64IZFINX-NEXT:  # %bb.1: # %if.else
 ; RV64IZFINX-NEXT:    ret
 ; RV64IZFINX-NEXT:  .LBB12_2: # %if.then
 ; RV64IZFINX-NEXT:    addi sp, sp, -16
 ; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp ult float %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_ule(float %a, float %b) nounwind {
 ; RV32IF-LABEL: br_fcmp_ule:
 ; RV32IF:       # %bb.0:
-; RV32IF-NEXT:    flt.s a0, fa1, fa0
-; RV32IF-NEXT:    beqz a0, .LBB13_2
+; RV32IF-NEXT:    fle.s a0, fa0, fa1
+; RV32IF-NEXT:    bnez a0, .LBB13_2
 ; RV32IF-NEXT:  # %bb.1: # %if.else
 ; RV32IF-NEXT:    ret
 ; RV32IF-NEXT:  .LBB13_2: # %if.then
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    call abort@plt
 ;
 ; RV64IF-LABEL: br_fcmp_ule:
 ; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    flt.s a0, fa1, fa0
-; RV64IF-NEXT:    beqz a0, .LBB13_2
+; RV64IF-NEXT:    fle.s a0, fa0, fa1
+; RV64IF-NEXT:    bnez a0, .LBB13_2
 ; RV64IF-NEXT:  # %bb.1: # %if.else
 ; RV64IF-NEXT:    ret
 ; RV64IF-NEXT:  .LBB13_2: # %if.then
 ; RV64IF-NEXT:    addi sp, sp, -16
 ; RV64IF-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IF-NEXT:    call abort@plt
 ;
 ; RV32IZFINX-LABEL: br_fcmp_ule:
 ; RV32IZFINX:       # %bb.0:
-; RV32IZFINX-NEXT:    flt.s a0, a1, a0
-; RV32IZFINX-NEXT:    beqz a0, .LBB13_2
+; RV32IZFINX-NEXT:    fle.s a0, a0, a1
+; RV32IZFINX-NEXT:    bnez a0, .LBB13_2
 ; RV32IZFINX-NEXT:  # %bb.1: # %if.else
 ; RV32IZFINX-NEXT:    ret
 ; RV32IZFINX-NEXT:  .LBB13_2: # %if.then
 ; RV32IZFINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    call abort@plt
 ;
 ; RV64IZFINX-LABEL: br_fcmp_ule:
 ; RV64IZFINX:       # %bb.0:
-; RV64IZFINX-NEXT:    flt.s a0, a1, a0
-; RV64IZFINX-NEXT:    beqz a0, .LBB13_2
+; RV64IZFINX-NEXT:    fle.s a0, a0, a1
+; RV64IZFINX-NEXT:    bnez a0, .LBB13_2
 ; RV64IZFINX-NEXT:  # %bb.1: # %if.else
 ; RV64IZFINX-NEXT:    ret
 ; RV64IZFINX-NEXT:  .LBB13_2: # %if.then
 ; RV64IZFINX-NEXT:    addi sp, sp, -16
 ; RV64IZFINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFINX-NEXT:    call abort@plt
   %1 = fcmp ule float %a, %b
   br i1 %1, label %if.then, label %if.else

llvm/test/CodeGen/RISCV/float-convert.ll

 ; RV32IF:       # %bb.0: # %start
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    lui a0, 913408
 ; RV32IF-NEXT:    fmv.w.x fa5, a0
-; RV32IF-NEXT:    fle.s s0, fa5, fa0
+; RV32IF-NEXT:    flt.s s0, fa0, fa5
 ; RV32IF-NEXT:    call __fixsfdi@plt
 ; RV32IF-NEXT:    lui a4, 524288
 ; RV32IF-NEXT:    lui a2, 524288
-; RV32IF-NEXT:    beqz s0, .LBB12_2
+; RV32IF-NEXT:    bnez s0, .LBB12_2
 ; RV32IF-NEXT:  # %bb.1: # %start
 ; RV32IF-NEXT:    mv a2, a1
 ; RV32IF-NEXT:  .LBB12_2: # %start
 ; RV32IF-NEXT:    lui a1, %hi(.LCPI12_0)
 ; RV32IF-NEXT:    flw fa5, %lo(.LCPI12_0)(a1)
 ; RV32IF-NEXT:    flt.s a3, fa5, fs0
 ; RV32IF-NEXT:    beqz a3, .LBB12_4
 ; RV32IF-NEXT:  # %bb.3:
 ; RV32IF-NEXT:    addi a2, a4, -1
 ; RV32IF-NEXT:  .LBB12_4: # %start
 ; RV32IF-NEXT:    feq.s a1, fs0, fs0
 ; RV32IF-NEXT:    neg a4, a1
 ; RV32IF-NEXT:    and a1, a4, a2
 ; RV32IF-NEXT:    neg a2, a3
-; RV32IF-NEXT:    neg a3, s0
-; RV32IF-NEXT:    and a0, a3, a0
+; RV32IF-NEXT:    addi s0, s0, -1
+; RV32IF-NEXT:    and a0, s0, a0
 ; RV32IF-NEXT:    or a0, a2, a0
 ; RV32IF-NEXT:    and a0, a4, a0
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;

 ; RV32IZFINX-LABEL: fcvt_l_s_sat:
 ; RV32IZFINX:       # %bb.0: # %start
 ; RV32IZFINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    mv s0, a0
 ; RV32IZFINX-NEXT:    lui a0, 913408
-; RV32IZFINX-NEXT:    fle.s s1, a0, s0
+; RV32IZFINX-NEXT:    flt.s s1, s0, a0
 ; RV32IZFINX-NEXT:    mv a0, s0
 ; RV32IZFINX-NEXT:    call __fixsfdi@plt
 ; RV32IZFINX-NEXT:    lui a4, 524288
 ; RV32IZFINX-NEXT:    lui a2, 524288
-; RV32IZFINX-NEXT:    beqz s1, .LBB12_2
+; RV32IZFINX-NEXT:    bnez s1, .LBB12_2
 ; RV32IZFINX-NEXT:  # %bb.1: # %start
 ; RV32IZFINX-NEXT:    mv a2, a1
 ; RV32IZFINX-NEXT:  .LBB12_2: # %start
 ; RV32IZFINX-NEXT:    lui a1, %hi(.LCPI12_0)
 ; RV32IZFINX-NEXT:    lw a1, %lo(.LCPI12_0)(a1)
 ; RV32IZFINX-NEXT:    flt.s a3, a1, s0
 ; RV32IZFINX-NEXT:    beqz a3, .LBB12_4
 ; RV32IZFINX-NEXT:  # %bb.3:
 ; RV32IZFINX-NEXT:    addi a2, a4, -1
 ; RV32IZFINX-NEXT:  .LBB12_4: # %start
 ; RV32IZFINX-NEXT:    feq.s a1, s0, s0
 ; RV32IZFINX-NEXT:    neg a4, a1
 ; RV32IZFINX-NEXT:    and a1, a4, a2
-; RV32IZFINX-NEXT:    neg a2, s1
-; RV32IZFINX-NEXT:    and a0, a2, a0
+; RV32IZFINX-NEXT:    addi s1, s1, -1
+; RV32IZFINX-NEXT:    and a0, s1, a0
 ; RV32IZFINX-NEXT:    neg a2, a3
 ; RV32IZFINX-NEXT:    or a0, a2, a0
 ; RV32IZFINX-NEXT:    and a0, a4, a0
 ; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    addi sp, sp, 16
 ; RV32IZFINX-NEXT:    ret

 ; RV32IF-LABEL: fcvt_lu_s_sat:
 ; RV32IF:       # %bb.0: # %start
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    fmv.w.x fa5, zero
-; RV32IF-NEXT:    fle.s a0, fa5, fa0
-; RV32IF-NEXT:    neg s0, a0
+; RV32IF-NEXT:    flt.s a0, fa0, fa5
+; RV32IF-NEXT:    addi s0, a0, -1
 ; RV32IF-NEXT:    call __fixunssfdi@plt
 ; RV32IF-NEXT:    lui a2, %hi(.LCPI14_0)
 ; RV32IF-NEXT:    flw fa5, %lo(.LCPI14_0)(a2)
 ; RV32IF-NEXT:    and a0, s0, a0
 ; RV32IF-NEXT:    flt.s a2, fa5, fs0
 ; RV32IF-NEXT:    neg a2, a2
 ; RV32IF-NEXT:    or a0, a2, a0
 ; RV32IF-NEXT:    and a1, s0, a1

 ;
 ; RV32IZFINX-LABEL: fcvt_lu_s_sat:
 ; RV32IZFINX:       # %bb.0: # %start
 ; RV32IZFINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    mv s0, a0
-; RV32IZFINX-NEXT:    fle.s a0, zero, a0
-; RV32IZFINX-NEXT:    neg s1, a0
+; RV32IZFINX-NEXT:    flt.s a0, a0, zero
+; RV32IZFINX-NEXT:    addi s1, a0, -1
 ; RV32IZFINX-NEXT:    mv a0, s0
 ; RV32IZFINX-NEXT:    call __fixunssfdi@plt
 ; RV32IZFINX-NEXT:    lui a2, %hi(.LCPI14_0)
 ; RV32IZFINX-NEXT:    lw a2, %lo(.LCPI14_0)(a2)
 ; RV32IZFINX-NEXT:    and a0, s1, a0
 ; RV32IZFINX-NEXT:    flt.s a2, a2, s0
 ; RV32IZFINX-NEXT:    neg a2, a2
 ; RV32IZFINX-NEXT:    or a0, a2, a0

llvm/test/CodeGen/RISCV/float-fcmp.ll

; RV64I-NEXT:    ret
   %1 = fcmp ueq float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ugt(float %a, float %b) nounwind {
 ; CHECKIF-LABEL: fcmp_ugt:
 ; CHECKIF:       # %bb.0:
-; CHECKIF-NEXT:    fle.s a0, fa0, fa1
-; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    flt.s a0, fa1, fa0
 ; CHECKIF-NEXT:    ret
 ;
 ; CHECKIZFINX-LABEL: fcmp_ugt:
 ; CHECKIZFINX:       # %bb.0:
-; CHECKIZFINX-NEXT:    fle.s a0, a0, a1
-; CHECKIZFINX-NEXT:    xori a0, a0, 1
+; CHECKIZFINX-NEXT:    flt.s a0, a1, a0
 ; CHECKIZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __lesf2@plt
 ; RV32I-NEXT:    sgtz a0, a0
; RV64I-NEXT:    ret
   %1 = fcmp ugt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uge(float %a, float %b) nounwind {
 ; CHECKIF-LABEL: fcmp_uge:
 ; CHECKIF:       # %bb.0:
-; CHECKIF-NEXT:    flt.s a0, fa0, fa1
-; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    fle.s a0, fa1, fa0
 ; CHECKIF-NEXT:    ret
 ;
 ; CHECKIZFINX-LABEL: fcmp_uge:
 ; CHECKIZFINX:       # %bb.0:
-; CHECKIZFINX-NEXT:    flt.s a0, a0, a1
-; CHECKIZFINX-NEXT:    xori a0, a0, 1
+; CHECKIZFINX-NEXT:    fle.s a0, a1, a0
 ; CHECKIZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __ltsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
; RV64I-NEXT:    ret
   %1 = fcmp uge float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ult(float %a, float %b) nounwind {
 ; CHECKIF-LABEL: fcmp_ult:
 ; CHECKIF:       # %bb.0:
-; CHECKIF-NEXT:    fle.s a0, fa1, fa0
-; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    flt.s a0, fa0, fa1
 ; CHECKIF-NEXT:    ret
 ;
 ; CHECKIZFINX-LABEL: fcmp_ult:
 ; CHECKIZFINX:       # %bb.0:
-; CHECKIZFINX-NEXT:    fle.s a0, a1, a0
-; CHECKIZFINX-NEXT:    xori a0, a0, 1
+; CHECKIZFINX-NEXT:    flt.s a0, a0, a1
 ; CHECKIZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gesf2@plt
 ; RV32I-NEXT:    slti a0, a0, 0
; RV64I-NEXT:    ret
   %1 = fcmp ult float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ule(float %a, float %b) nounwind {
 ; CHECKIF-LABEL: fcmp_ule:
 ; CHECKIF:       # %bb.0:
-; CHECKIF-NEXT:    flt.s a0, fa1, fa0
-; CHECKIF-NEXT:    xori a0, a0, 1
+; CHECKIF-NEXT:    fle.s a0, fa0, fa1
 ; CHECKIF-NEXT:    ret
 ;
 ; CHECKIZFINX-LABEL: fcmp_ule:
 ; CHECKIZFINX:       # %bb.0:
-; CHECKIZFINX-NEXT:    flt.s a0, a1, a0
-; CHECKIZFINX-NEXT:    xori a0, a0, 1
+; CHECKIZFINX-NEXT:    fle.s a0, a0, a1
 ; CHECKIZFINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __gtsf2@plt
 ; RV32I-NEXT:    slti a0, a0, 1

llvm/test/CodeGen/RISCV/float-round-conv-sat.ll

 ; RV32IF-NEXT:    beqz a0, .LBB1_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fcvt.w.s a0, fs0, rdn
 ; RV32IF-NEXT:    fcvt.s.w fa5, a0, rdn
 ; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
 ; RV32IF-NEXT:  .LBB1_2:
 ; RV32IF-NEXT:    lui a0, 913408
 ; RV32IF-NEXT:    fmv.w.x fa5, a0
-; RV32IF-NEXT:    fle.s s0, fa5, fs0
+; RV32IF-NEXT:    flt.s s0, fs0, fa5
 ; RV32IF-NEXT:    fmv.s fa0, fs0
 ; RV32IF-NEXT:    call __fixsfdi@plt
 ; RV32IF-NEXT:    lui a4, 524288
 ; RV32IF-NEXT:    lui a2, 524288
-; RV32IF-NEXT:    beqz s0, .LBB1_4
+; RV32IF-NEXT:    bnez s0, .LBB1_4
 ; RV32IF-NEXT:  # %bb.3:
 ; RV32IF-NEXT:    mv a2, a1
 ; RV32IF-NEXT:  .LBB1_4:
 ; RV32IF-NEXT:    lui a1, %hi(.LCPI1_0)
 ; RV32IF-NEXT:    flw fa5, %lo(.LCPI1_0)(a1)
 ; RV32IF-NEXT:    flt.s a3, fa5, fs0
 ; RV32IF-NEXT:    beqz a3, .LBB1_6
 ; RV32IF-NEXT:  # %bb.5:
 ; RV32IF-NEXT:    addi a2, a4, -1
 ; RV32IF-NEXT:  .LBB1_6:
 ; RV32IF-NEXT:    feq.s a1, fs0, fs0
 ; RV32IF-NEXT:    neg a4, a1
 ; RV32IF-NEXT:    and a1, a4, a2
-; RV32IF-NEXT:    neg a2, s0
-; RV32IF-NEXT:    and a0, a2, a0
+; RV32IF-NEXT:    addi s0, s0, -1
+; RV32IF-NEXT:    and a0, s0, a0
 ; RV32IF-NEXT:    neg a2, a3
 ; RV32IF-NEXT:    or a0, a2, a0
 ; RV32IF-NEXT:    and a0, a4, a0
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_floor_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rdn
 ; RV64IF-NEXT:    feq.s a1, fa0, fa0
 ; RV64IF-NEXT:    seqz a1, a1
 ; RV64IF-NEXT:    addi a1, a1, -1
 ; RV64IF-NEXT:    and a0, a1, a0
 ; RV64IF-NEXT:    ret
 ;
 ; RV32IZFINX-LABEL: test_floor_si64:
 ; RV32IZFINX:       # %bb.0:
 ; RV32IZFINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IZFINX-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    mv s0, a0
 ; RV32IZFINX-NEXT:    lui a0, 307200
 ; RV32IZFINX-NEXT:    fabs.s a1, s0
 ; RV32IZFINX-NEXT:    flt.s a0, a1, a0
 ; RV32IZFINX-NEXT:    beqz a0, .LBB1_2
 ; RV32IZFINX-NEXT:  # %bb.1:
 ; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rdn
 ; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rdn
 ; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
 ; RV32IZFINX-NEXT:  .LBB1_2:
-; RV32IZFINX-NEXT:    lui a0, 913408
-; RV32IZFINX-NEXT:    fle.s s1, a0, s0
-; RV32IZFINX-NEXT:    neg s2, s1
 ; RV32IZFINX-NEXT:    mv a0, s0
 ; RV32IZFINX-NEXT:    call __fixsfdi@plt
-; RV32IZFINX-NEXT:    lui a2, %hi(.LCPI1_0)
-; RV32IZFINX-NEXT:    lw a2, %lo(.LCPI1_0)(a2)
-; RV32IZFINX-NEXT:    and a0, s2, a0
-; RV32IZFINX-NEXT:    flt.s a4, a2, s0
+; RV32IZFINX-NEXT:    lui a2, 913408
+; RV32IZFINX-NEXT:    lui a3, %hi(.LCPI1_0)
+; RV32IZFINX-NEXT:    lw a3, %lo(.LCPI1_0)(a3)
+; RV32IZFINX-NEXT:    flt.s a6, s0, a2
+; RV32IZFINX-NEXT:    addi a2, a6, -1
+; RV32IZFINX-NEXT:    and a0, a2, a0
+; RV32IZFINX-NEXT:    flt.s a4, a3, s0
 ; RV32IZFINX-NEXT:    neg a2, a4
 ; RV32IZFINX-NEXT:    or a0, a2, a0
 ; RV32IZFINX-NEXT:    feq.s a2, s0, s0
 ; RV32IZFINX-NEXT:    neg a2, a2
 ; RV32IZFINX-NEXT:    lui a5, 524288
 ; RV32IZFINX-NEXT:    lui a3, 524288
-; RV32IZFINX-NEXT:    beqz s1, .LBB1_4
+; RV32IZFINX-NEXT:    bnez a6, .LBB1_4
 ; RV32IZFINX-NEXT:  # %bb.3:
 ; RV32IZFINX-NEXT:    mv a3, a1
 ; RV32IZFINX-NEXT:  .LBB1_4:
 ; RV32IZFINX-NEXT:    and a0, a2, a0
 ; RV32IZFINX-NEXT:    beqz a4, .LBB1_6
 ; RV32IZFINX-NEXT:  # %bb.5:
 ; RV32IZFINX-NEXT:    addi a3, a5, -1
 ; RV32IZFINX-NEXT:  .LBB1_6:
 ; RV32IZFINX-NEXT:    and a1, a2, a3
 ; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
-; RV32IZFINX-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    addi sp, sp, 16
 ; RV32IZFINX-NEXT:    ret
 ;
 ; RV64IZFINX-LABEL: test_floor_si64:
 ; RV64IZFINX:       # %bb.0:
 ; RV64IZFINX-NEXT:    fcvt.l.s a1, a0, rdn
 ; RV64IZFINX-NEXT:    feq.s a0, a0, a0
 ; RV64IZFINX-NEXT:    seqz a0, a0
; CHECKIZFINX-NEXT:    ret
   ret i32 %b
 }
 
 define i64 @test_floor_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_floor_ui64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IF-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    lui a0, 307200
 ; RV32IF-NEXT:    fmv.w.x fa5, a0
 ; RV32IF-NEXT:    fabs.s fa4, fa0
 ; RV32IF-NEXT:    flt.s a0, fa4, fa5
 ; RV32IF-NEXT:    beqz a0, .LBB3_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fcvt.w.s a0, fs0, rdn
 ; RV32IF-NEXT:    fcvt.s.w fa5, a0, rdn
 ; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
 ; RV32IF-NEXT:  .LBB3_2:
-; RV32IF-NEXT:    fmv.w.x fa5, zero
-; RV32IF-NEXT:    fle.s a0, fa5, fs0
-; RV32IF-NEXT:    neg s0, a0
 ; RV32IF-NEXT:    fmv.s fa0, fs0
 ; RV32IF-NEXT:    call __fixunssfdi@plt
+; RV32IF-NEXT:    fmv.w.x fa5, zero
 ; RV32IF-NEXT:    lui a2, %hi(.LCPI3_0)
-; RV32IF-NEXT:    flw fa5, %lo(.LCPI3_0)(a2)
-; RV32IF-NEXT:    and a0, s0, a0
-; RV32IF-NEXT:    flt.s a2, fa5, fs0
-; RV32IF-NEXT:    neg a2, a2
-; RV32IF-NEXT:    or a0, a2, a0
-; RV32IF-NEXT:    and a1, s0, a1
-; RV32IF-NEXT:    or a1, a2, a1
+; RV32IF-NEXT:    flw fa4, %lo(.LCPI3_0)(a2)
+; RV32IF-NEXT:    flt.s a2, fs0, fa5
+; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    and a0, a2, a0
+; RV32IF-NEXT:    flt.s a3, fa4, fs0
+; RV32IF-NEXT:    neg a3, a3
+; RV32IF-NEXT:    or a0, a3, a0
+; RV32IF-NEXT:    and a1, a2, a1
+; RV32IF-NEXT:    or a1, a3, a1
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IF-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_floor_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rdn
 ; RV64IF-NEXT:    feq.s a1, fa0, fa0
 ; RV64IF-NEXT:    seqz a1, a1
 ; RV64IF-NEXT:    addi a1, a1, -1
 ; RV64IF-NEXT:    and a0, a1, a0
 ; RV64IF-NEXT:    ret
 ;
 ; RV32IZFINX-LABEL: test_floor_ui64:
 ; RV32IZFINX:       # %bb.0:
 ; RV32IZFINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    mv s0, a0
 ; RV32IZFINX-NEXT:    lui a0, 307200
 ; RV32IZFINX-NEXT:    fabs.s a1, s0
 ; RV32IZFINX-NEXT:    flt.s a0, a1, a0
 ; RV32IZFINX-NEXT:    beqz a0, .LBB3_2
 ; RV32IZFINX-NEXT:  # %bb.1:
 ; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rdn
 ; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rdn
 ; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
 ; RV32IZFINX-NEXT:  .LBB3_2:
-; RV32IZFINX-NEXT:    fle.s a0, zero, s0
-; RV32IZFINX-NEXT:    neg s1, a0
 ; RV32IZFINX-NEXT:    mv a0, s0
 ; RV32IZFINX-NEXT:    call __fixunssfdi@plt
 ; RV32IZFINX-NEXT:    lui a2, %hi(.LCPI3_0)
 ; RV32IZFINX-NEXT:    lw a2, %lo(.LCPI3_0)(a2)
-; RV32IZFINX-NEXT:    and a0, s1, a0
+; RV32IZFINX-NEXT:    flt.s a3, s0, zero
+; RV32IZFINX-NEXT:    addi a3, a3, -1
+; RV32IZFINX-NEXT:    and a0, a3, a0
 ; RV32IZFINX-NEXT:    flt.s a2, a2, s0
 ; RV32IZFINX-NEXT:    neg a2, a2
 ; RV32IZFINX-NEXT:    or a0, a2, a0
-; RV32IZFINX-NEXT:    and a1, s1, a1
+; RV32IZFINX-NEXT:    and a1, a3, a1
 ; RV32IZFINX-NEXT:    or a1, a2, a1
 ; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    addi sp, sp, 16
 ; RV32IZFINX-NEXT:    ret
 ;
 ; RV64IZFINX-LABEL: test_floor_ui64:
 ; RV64IZFINX:       # %bb.0:
 ; RV64IZFINX-NEXT:    fcvt.lu.s a1, a0, rdn
 ; RV64IZFINX-NEXT:    feq.s a0, a0, a0
 ; RV64IZFINX-NEXT:    seqz a0, a0

 ; RV32IF-NEXT:    beqz a0, .LBB5_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fcvt.w.s a0, fs0, rup
 ; RV32IF-NEXT:    fcvt.s.w fa5, a0, rup
 ; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
 ; RV32IF-NEXT:  .LBB5_2:
 ; RV32IF-NEXT:    lui a0, 913408
 ; RV32IF-NEXT:    fmv.w.x fa5, a0
-; RV32IF-NEXT:    fle.s s0, fa5, fs0
+; RV32IF-NEXT:    flt.s s0, fs0, fa5
 ; RV32IF-NEXT:    fmv.s fa0, fs0
 ; RV32IF-NEXT:    call __fixsfdi@plt
 ; RV32IF-NEXT:    lui a4, 524288
 ; RV32IF-NEXT:    lui a2, 524288
-; RV32IF-NEXT:    beqz s0, .LBB5_4
+; RV32IF-NEXT:    bnez s0, .LBB5_4
 ; RV32IF-NEXT:  # %bb.3:
 ; RV32IF-NEXT:    mv a2, a1
 ; RV32IF-NEXT:  .LBB5_4:
 ; RV32IF-NEXT:    lui a1, %hi(.LCPI5_0)
 ; RV32IF-NEXT:    flw fa5, %lo(.LCPI5_0)(a1)
 ; RV32IF-NEXT:    flt.s a3, fa5, fs0
 ; RV32IF-NEXT:    beqz a3, .LBB5_6
 ; RV32IF-NEXT:  # %bb.5:
 ; RV32IF-NEXT:    addi a2, a4, -1
 ; RV32IF-NEXT:  .LBB5_6:
 ; RV32IF-NEXT:    feq.s a1, fs0, fs0
 ; RV32IF-NEXT:    neg a4, a1
 ; RV32IF-NEXT:    and a1, a4, a2
-; RV32IF-NEXT:    neg a2, s0
-; RV32IF-NEXT:    and a0, a2, a0
+; RV32IF-NEXT:    addi s0, s0, -1
+; RV32IF-NEXT:    and a0, s0, a0
 ; RV32IF-NEXT:    neg a2, a3
 ; RV32IF-NEXT:    or a0, a2, a0
 ; RV32IF-NEXT:    and a0, a4, a0
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_ceil_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rup
 ; RV64IF-NEXT:    feq.s a1, fa0, fa0
 ; RV64IF-NEXT:    seqz a1, a1
 ; RV64IF-NEXT:    addi a1, a1, -1
 ; RV64IF-NEXT:    and a0, a1, a0
 ; RV64IF-NEXT:    ret
 ;
 ; RV32IZFINX-LABEL: test_ceil_si64:
 ; RV32IZFINX:       # %bb.0:
 ; RV32IZFINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IZFINX-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    mv s0, a0
 ; RV32IZFINX-NEXT:    lui a0, 307200
 ; RV32IZFINX-NEXT:    fabs.s a1, s0
 ; RV32IZFINX-NEXT:    flt.s a0, a1, a0
 ; RV32IZFINX-NEXT:    beqz a0, .LBB5_2
 ; RV32IZFINX-NEXT:  # %bb.1:
 ; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rup
 ; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rup
 ; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
 ; RV32IZFINX-NEXT:  .LBB5_2:
-; RV32IZFINX-NEXT:    lui a0, 913408
-; RV32IZFINX-NEXT:    fle.s s1, a0, s0
-; RV32IZFINX-NEXT:    neg s2, s1
 ; RV32IZFINX-NEXT:    mv a0, s0
 ; RV32IZFINX-NEXT:    call __fixsfdi@plt
-; RV32IZFINX-NEXT:    lui a2, %hi(.LCPI5_0)
-; RV32IZFINX-NEXT:    lw a2, %lo(.LCPI5_0)(a2)
-; RV32IZFINX-NEXT:    and a0, s2, a0
-; RV32IZFINX-NEXT:    flt.s a4, a2, s0
+; RV32IZFINX-NEXT:    lui a2, 913408
+; RV32IZFINX-NEXT:    lui a3, %hi(.LCPI5_0)
+; RV32IZFINX-NEXT:    lw a3, %lo(.LCPI5_0)(a3)
+; RV32IZFINX-NEXT:    flt.s a6, s0, a2
+; RV32IZFINX-NEXT:    addi a2, a6, -1
+; RV32IZFINX-NEXT:    and a0, a2, a0
+; RV32IZFINX-NEXT:    flt.s a4, a3, s0
 ; RV32IZFINX-NEXT:    neg a2, a4
 ; RV32IZFINX-NEXT:    or a0, a2, a0
 ; RV32IZFINX-NEXT:    feq.s a2, s0, s0
 ; RV32IZFINX-NEXT:    neg a2, a2
 ; RV32IZFINX-NEXT:    lui a5, 524288
 ; RV32IZFINX-NEXT:    lui a3, 524288
-; RV32IZFINX-NEXT:    beqz s1, .LBB5_4
+; RV32IZFINX-NEXT:    bnez a6, .LBB5_4
 ; RV32IZFINX-NEXT:  # %bb.3:
 ; RV32IZFINX-NEXT:    mv a3, a1
 ; RV32IZFINX-NEXT:  .LBB5_4:
 ; RV32IZFINX-NEXT:    and a0, a2, a0
 ; RV32IZFINX-NEXT:    beqz a4, .LBB5_6
 ; RV32IZFINX-NEXT:  # %bb.5:
 ; RV32IZFINX-NEXT:    addi a3, a5, -1
 ; RV32IZFINX-NEXT:  .LBB5_6:
 ; RV32IZFINX-NEXT:    and a1, a2, a3
 ; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
-; RV32IZFINX-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    addi sp, sp, 16
 ; RV32IZFINX-NEXT:    ret
 ;
 ; RV64IZFINX-LABEL: test_ceil_si64:
 ; RV64IZFINX:       # %bb.0:
 ; RV64IZFINX-NEXT:    fcvt.l.s a1, a0, rup
 ; RV64IZFINX-NEXT:    feq.s a0, a0, a0
 ; RV64IZFINX-NEXT:    seqz a0, a0
; CHECKIZFINX-NEXT:    ret
   ret i32 %b
 }
 
 define i64 @test_ceil_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_ceil_ui64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IF-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    lui a0, 307200
 ; RV32IF-NEXT:    fmv.w.x fa5, a0
 ; RV32IF-NEXT:    fabs.s fa4, fa0
 ; RV32IF-NEXT:    flt.s a0, fa4, fa5
 ; RV32IF-NEXT:    beqz a0, .LBB7_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fcvt.w.s a0, fs0, rup
 ; RV32IF-NEXT:    fcvt.s.w fa5, a0, rup
 ; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
 ; RV32IF-NEXT:  .LBB7_2:
-; RV32IF-NEXT:    fmv.w.x fa5, zero
-; RV32IF-NEXT:    fle.s a0, fa5, fs0
-; RV32IF-NEXT:    neg s0, a0
 ; RV32IF-NEXT:    fmv.s fa0, fs0
 ; RV32IF-NEXT:    call __fixunssfdi@plt
+; RV32IF-NEXT:    fmv.w.x fa5, zero
 ; RV32IF-NEXT:    lui a2, %hi(.LCPI7_0)
-; RV32IF-NEXT:    flw fa5, %lo(.LCPI7_0)(a2)
-; RV32IF-NEXT:    and a0, s0, a0
-; RV32IF-NEXT:    flt.s a2, fa5, fs0
-; RV32IF-NEXT:    neg a2, a2
-; RV32IF-NEXT:    or a0, a2, a0
-; RV32IF-NEXT:    and a1, s0, a1
-; RV32IF-NEXT:    or a1, a2, a1
+; RV32IF-NEXT:    flw fa4, %lo(.LCPI7_0)(a2)
+; RV32IF-NEXT:    flt.s a2, fs0, fa5
+; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    and a0, a2, a0
+; RV32IF-NEXT:    flt.s a3, fa4, fs0
+; RV32IF-NEXT:    neg a3, a3
+; RV32IF-NEXT:    or a0, a3, a0
+; RV32IF-NEXT:    and a1, a2, a1
+; RV32IF-NEXT:    or a1, a3, a1
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IF-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_ceil_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rup
 ; RV64IF-NEXT:    feq.s a1, fa0, fa0
 ; RV64IF-NEXT:    seqz a1, a1
 ; RV64IF-NEXT:    addi a1, a1, -1
 ; RV64IF-NEXT:    and a0, a1, a0
 ; RV64IF-NEXT:    ret
 ;
 ; RV32IZFINX-LABEL: test_ceil_ui64:
 ; RV32IZFINX:       # %bb.0:
 ; RV32IZFINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    mv s0, a0
 ; RV32IZFINX-NEXT:    lui a0, 307200
 ; RV32IZFINX-NEXT:    fabs.s a1, s0
 ; RV32IZFINX-NEXT:    flt.s a0, a1, a0
 ; RV32IZFINX-NEXT:    beqz a0, .LBB7_2
 ; RV32IZFINX-NEXT:  # %bb.1:
 ; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rup
 ; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rup
 ; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
 ; RV32IZFINX-NEXT:  .LBB7_2:
-; RV32IZFINX-NEXT:    fle.s a0, zero, s0
-; RV32IZFINX-NEXT:    neg s1, a0
 ; RV32IZFINX-NEXT:    mv a0, s0
 ; RV32IZFINX-NEXT:    call __fixunssfdi@plt
 ; RV32IZFINX-NEXT:    lui a2, %hi(.LCPI7_0)
 ; RV32IZFINX-NEXT:    lw a2, %lo(.LCPI7_0)(a2)
-; RV32IZFINX-NEXT:    and a0, s1, a0
+; RV32IZFINX-NEXT:    flt.s a3, s0, zero
+; RV32IZFINX-NEXT:    addi a3, a3, -1
+; RV32IZFINX-NEXT:    and a0, a3, a0
 ; RV32IZFINX-NEXT:    flt.s a2, a2, s0
 ; RV32IZFINX-NEXT:    neg a2, a2
 ; RV32IZFINX-NEXT:    or a0, a2, a0
-; RV32IZFINX-NEXT:    and a1, s1, a1
+; RV32IZFINX-NEXT:    and a1, a3, a1
 ; RV32IZFINX-NEXT:    or a1, a2, a1
 ; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    addi sp, sp, 16
 ; RV32IZFINX-NEXT:    ret
 ;
 ; RV64IZFINX-LABEL: test_ceil_ui64:
 ; RV64IZFINX:       # %bb.0:
 ; RV64IZFINX-NEXT:    fcvt.lu.s a1, a0, rup
 ; RV64IZFINX-NEXT:    feq.s a0, a0, a0
 ; RV64IZFINX-NEXT:    seqz a0, a0

 ; RV32IF-NEXT:    beqz a0, .LBB9_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fcvt.w.s a0, fs0, rtz
 ; RV32IF-NEXT:    fcvt.s.w fa5, a0, rtz
 ; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
 ; RV32IF-NEXT:  .LBB9_2:
 ; RV32IF-NEXT:    lui a0, 913408
 ; RV32IF-NEXT:    fmv.w.x fa5, a0
-; RV32IF-NEXT:    fle.s s0, fa5, fs0
+; RV32IF-NEXT:    flt.s s0, fs0, fa5
 ; RV32IF-NEXT:    fmv.s fa0, fs0
 ; RV32IF-NEXT:    call __fixsfdi@plt
 ; RV32IF-NEXT:    lui a4, 524288
 ; RV32IF-NEXT:    lui a2, 524288
-; RV32IF-NEXT:    beqz s0, .LBB9_4
+; RV32IF-NEXT:    bnez s0, .LBB9_4
 ; RV32IF-NEXT:  # %bb.3:
 ; RV32IF-NEXT:    mv a2, a1
 ; RV32IF-NEXT:  .LBB9_4:
 ; RV32IF-NEXT:    lui a1, %hi(.LCPI9_0)
 ; RV32IF-NEXT:    flw fa5, %lo(.LCPI9_0)(a1)
 ; RV32IF-NEXT:    flt.s a3, fa5, fs0
 ; RV32IF-NEXT:    beqz a3, .LBB9_6
 ; RV32IF-NEXT:  # %bb.5:
 ; RV32IF-NEXT:    addi a2, a4, -1
 ; RV32IF-NEXT:  .LBB9_6:
 ; RV32IF-NEXT:    feq.s a1, fs0, fs0
 ; RV32IF-NEXT:    neg a4, a1
 ; RV32IF-NEXT:    and a1, a4, a2
-; RV32IF-NEXT:    neg a2, s0
-; RV32IF-NEXT:    and a0, a2, a0
+; RV32IF-NEXT:    addi s0, s0, -1
+; RV32IF-NEXT:    and a0, s0, a0
 ; RV32IF-NEXT:    neg a2, a3
 ; RV32IF-NEXT:    or a0, a2, a0
 ; RV32IF-NEXT:    and a0, a4, a0
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_trunc_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rtz
 ; RV64IF-NEXT:    feq.s a1, fa0, fa0
 ; RV64IF-NEXT:    seqz a1, a1
 ; RV64IF-NEXT:    addi a1, a1, -1
 ; RV64IF-NEXT:    and a0, a1, a0
 ; RV64IF-NEXT:    ret
 ;
 ; RV32IZFINX-LABEL: test_trunc_si64:
 ; RV32IZFINX:       # %bb.0:
 ; RV32IZFINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IZFINX-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    mv s0, a0
 ; RV32IZFINX-NEXT:    lui a0, 307200
 ; RV32IZFINX-NEXT:    fabs.s a1, s0
 ; RV32IZFINX-NEXT:    flt.s a0, a1, a0
 ; RV32IZFINX-NEXT:    beqz a0, .LBB9_2
 ; RV32IZFINX-NEXT:  # %bb.1:
 ; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rtz
 ; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rtz
 ; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
 ; RV32IZFINX-NEXT:  .LBB9_2:
-; RV32IZFINX-NEXT:    lui a0, 913408
-; RV32IZFINX-NEXT:    fle.s s1, a0, s0
-; RV32IZFINX-NEXT:    neg s2, s1
 ; RV32IZFINX-NEXT:    mv a0, s0
 ; RV32IZFINX-NEXT:    call __fixsfdi@plt
-; RV32IZFINX-NEXT:    lui a2, %hi(.LCPI9_0)
-; RV32IZFINX-NEXT:    lw a2, %lo(.LCPI9_0)(a2)
-; RV32IZFINX-NEXT:    and a0, s2, a0
-; RV32IZFINX-NEXT:    flt.s a4, a2, s0
+; RV32IZFINX-NEXT:    lui a2, 913408
+; RV32IZFINX-NEXT:    lui a3, %hi(.LCPI9_0)
+; RV32IZFINX-NEXT:    lw a3, %lo(.LCPI9_0)(a3)
+; RV32IZFINX-NEXT:    flt.s a6, s0, a2
+; RV32IZFINX-NEXT:    addi a2, a6, -1
+; RV32IZFINX-NEXT:    and a0, a2, a0
+; RV32IZFINX-NEXT:    flt.s a4, a3, s0
 ; RV32IZFINX-NEXT:    neg a2, a4
 ; RV32IZFINX-NEXT:    or a0, a2, a0
 ; RV32IZFINX-NEXT:    feq.s a2, s0, s0
 ; RV32IZFINX-NEXT:    neg a2, a2
 ; RV32IZFINX-NEXT:    lui a5, 524288
 ; RV32IZFINX-NEXT:    lui a3, 524288
-; RV32IZFINX-NEXT:    beqz s1, .LBB9_4
+; RV32IZFINX-NEXT:    bnez a6, .LBB9_4
 ; RV32IZFINX-NEXT:  # %bb.3:
 ; RV32IZFINX-NEXT:    mv a3, a1
 ; RV32IZFINX-NEXT:  .LBB9_4:
 ; RV32IZFINX-NEXT:    and a0, a2, a0
 ; RV32IZFINX-NEXT:    beqz a4, .LBB9_6
 ; RV32IZFINX-NEXT:  # %bb.5:
 ; RV32IZFINX-NEXT:    addi a3, a5, -1
 ; RV32IZFINX-NEXT:  .LBB9_6:
 ; RV32IZFINX-NEXT:    and a1, a2, a3
 ; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
-; RV32IZFINX-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    addi sp, sp, 16
 ; RV32IZFINX-NEXT:    ret
 ;
 ; RV64IZFINX-LABEL: test_trunc_si64:
 ; RV64IZFINX:       # %bb.0:
 ; RV64IZFINX-NEXT:    fcvt.l.s a1, a0, rtz
 ; RV64IZFINX-NEXT:    feq.s a0, a0, a0
 ; RV64IZFINX-NEXT:    seqz a0, a0
; CHECKIZFINX-NEXT:    ret
   ret i32 %b
 }
 
 define i64 @test_trunc_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_trunc_ui64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IF-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    lui a0, 307200
 ; RV32IF-NEXT:    fmv.w.x fa5, a0
 ; RV32IF-NEXT:    fabs.s fa4, fa0
 ; RV32IF-NEXT:    flt.s a0, fa4, fa5
 ; RV32IF-NEXT:    beqz a0, .LBB11_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fcvt.w.s a0, fs0, rtz
 ; RV32IF-NEXT:    fcvt.s.w fa5, a0, rtz
 ; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
 ; RV32IF-NEXT:  .LBB11_2:
-; RV32IF-NEXT:    fmv.w.x fa5, zero
-; RV32IF-NEXT:    fle.s a0, fa5, fs0
-; RV32IF-NEXT:    neg s0, a0
 ; RV32IF-NEXT:    fmv.s fa0, fs0
 ; RV32IF-NEXT:    call __fixunssfdi@plt
+; RV32IF-NEXT:    fmv.w.x fa5, zero
 ; RV32IF-NEXT:    lui a2, %hi(.LCPI11_0)
-; RV32IF-NEXT:    flw fa5, %lo(.LCPI11_0)(a2)
-; RV32IF-NEXT:    and a0, s0, a0
-; RV32IF-NEXT:    flt.s a2, fa5, fs0
-; RV32IF-NEXT:    neg a2, a2
-; RV32IF-NEXT:    or a0, a2, a0
-; RV32IF-NEXT:    and a1, s0, a1
-; RV32IF-NEXT:    or a1, a2, a1
+; RV32IF-NEXT:    flw fa4, %lo(.LCPI11_0)(a2)
+; RV32IF-NEXT:    flt.s a2, fs0, fa5
+; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    and a0, a2, a0
+; RV32IF-NEXT:    flt.s a3, fa4, fs0
+; RV32IF-NEXT:    neg a3, a3
+; RV32IF-NEXT:    or a0, a3, a0
+; RV32IF-NEXT:    and a1, a2, a1
+; RV32IF-NEXT:    or a1, a3, a1
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IF-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_trunc_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rtz
 ; RV64IF-NEXT:    feq.s a1, fa0, fa0
 ; RV64IF-NEXT:    seqz a1, a1
 ; RV64IF-NEXT:    addi a1, a1, -1
 ; RV64IF-NEXT:    and a0, a1, a0
 ; RV64IF-NEXT:    ret
 ;
 ; RV32IZFINX-LABEL: test_trunc_ui64:
 ; RV32IZFINX:       # %bb.0:
 ; RV32IZFINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    mv s0, a0
 ; RV32IZFINX-NEXT:    lui a0, 307200
 ; RV32IZFINX-NEXT:    fabs.s a1, s0
 ; RV32IZFINX-NEXT:    flt.s a0, a1, a0
 ; RV32IZFINX-NEXT:    beqz a0, .LBB11_2
 ; RV32IZFINX-NEXT:  # %bb.1:
 ; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rtz
 ; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rtz
 ; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
 ; RV32IZFINX-NEXT:  .LBB11_2:
-; RV32IZFINX-NEXT:    fle.s a0, zero, s0
-; RV32IZFINX-NEXT:    neg s1, a0
 ; RV32IZFINX-NEXT:    mv a0, s0
 ; RV32IZFINX-NEXT:    call __fixunssfdi@plt
 ; RV32IZFINX-NEXT:    lui a2, %hi(.LCPI11_0)
 ; RV32IZFINX-NEXT:    lw a2, %lo(.LCPI11_0)(a2)
-; RV32IZFINX-NEXT:    and a0, s1, a0
+; RV32IZFINX-NEXT:    flt.s a3, s0, zero
+; RV32IZFINX-NEXT:    addi a3, a3, -1
+; RV32IZFINX-NEXT:    and a0, a3, a0
 ; RV32IZFINX-NEXT:    flt.s a2, a2, s0
 ; RV32IZFINX-NEXT:    neg a2, a2
 ; RV32IZFINX-NEXT:    or a0, a2, a0
-; RV32IZFINX-NEXT:    and a1, s1, a1
+; RV32IZFINX-NEXT:    and a1, a3, a1
 ; RV32IZFINX-NEXT:    or a1, a2, a1
 ; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    addi sp, sp, 16
 ; RV32IZFINX-NEXT:    ret
 ;
 ; RV64IZFINX-LABEL: test_trunc_ui64:
 ; RV64IZFINX:       # %bb.0:
 ; RV64IZFINX-NEXT:    fcvt.lu.s a1, a0, rtz
 ; RV64IZFINX-NEXT:    feq.s a0, a0, a0
 ; RV64IZFINX-NEXT:    seqz a0, a0

 ; RV32IF-NEXT:    beqz a0, .LBB13_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fcvt.w.s a0, fs0, rmm
 ; RV32IF-NEXT:    fcvt.s.w fa5, a0, rmm
 ; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
 ; RV32IF-NEXT:  .LBB13_2:
 ; RV32IF-NEXT:    lui a0, 913408
 ; RV32IF-NEXT:    fmv.w.x fa5, a0
-; RV32IF-NEXT:    fle.s s0, fa5, fs0
+; RV32IF-NEXT:    flt.s s0, fs0, fa5
 ; RV32IF-NEXT:    fmv.s fa0, fs0
 ; RV32IF-NEXT:    call __fixsfdi@plt
 ; RV32IF-NEXT:    lui a4, 524288
 ; RV32IF-NEXT:    lui a2, 524288
-; RV32IF-NEXT:    beqz s0, .LBB13_4
+; RV32IF-NEXT:    bnez s0, .LBB13_4
 ; RV32IF-NEXT:  # %bb.3:
 ; RV32IF-NEXT:    mv a2, a1
 ; RV32IF-NEXT:  .LBB13_4:
 ; RV32IF-NEXT:    lui a1, %hi(.LCPI13_0)
 ; RV32IF-NEXT:    flw fa5, %lo(.LCPI13_0)(a1)
 ; RV32IF-NEXT:    flt.s a3, fa5, fs0
 ; RV32IF-NEXT:    beqz a3, .LBB13_6
 ; RV32IF-NEXT:  # %bb.5:
 ; RV32IF-NEXT:    addi a2, a4, -1
 ; RV32IF-NEXT:  .LBB13_6:
 ; RV32IF-NEXT:    feq.s a1, fs0, fs0
 ; RV32IF-NEXT:    neg a4, a1
 ; RV32IF-NEXT:    and a1, a4, a2
-; RV32IF-NEXT:    neg a2, s0
-; RV32IF-NEXT:    and a0, a2, a0
+; RV32IF-NEXT:    addi s0, s0, -1
+; RV32IF-NEXT:    and a0, s0, a0
 ; RV32IF-NEXT:    neg a2, a3
 ; RV32IF-NEXT:    or a0, a2, a0
 ; RV32IF-NEXT:    and a0, a4, a0
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_round_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rmm
 ; RV64IF-NEXT:    feq.s a1, fa0, fa0
 ; RV64IF-NEXT:    seqz a1, a1
 ; RV64IF-NEXT:    addi a1, a1, -1
 ; RV64IF-NEXT:    and a0, a1, a0
 ; RV64IF-NEXT:    ret
 ;
 ; RV32IZFINX-LABEL: test_round_si64:
 ; RV32IZFINX:       # %bb.0:
 ; RV32IZFINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IZFINX-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    mv s0, a0
 ; RV32IZFINX-NEXT:    lui a0, 307200
 ; RV32IZFINX-NEXT:    fabs.s a1, s0
 ; RV32IZFINX-NEXT:    flt.s a0, a1, a0
 ; RV32IZFINX-NEXT:    beqz a0, .LBB13_2
 ; RV32IZFINX-NEXT:  # %bb.1:
 ; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rmm
 ; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rmm
 ; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
 ; RV32IZFINX-NEXT:  .LBB13_2:
-; RV32IZFINX-NEXT:    lui a0, 913408
-; RV32IZFINX-NEXT:    fle.s s1, a0, s0
-; RV32IZFINX-NEXT:    neg s2, s1
 ; RV32IZFINX-NEXT:    mv a0, s0
 ; RV32IZFINX-NEXT:    call __fixsfdi@plt
-; RV32IZFINX-NEXT:    lui a2, %hi(.LCPI13_0)
-; RV32IZFINX-NEXT:    lw a2, %lo(.LCPI13_0)(a2)
-; RV32IZFINX-NEXT:    and a0, s2, a0
-; RV32IZFINX-NEXT:    flt.s a4, a2, s0
+; RV32IZFINX-NEXT:    lui a2, 913408
+; RV32IZFINX-NEXT:    lui a3, %hi(.LCPI13_0)
+; RV32IZFINX-NEXT:    lw a3, %lo(.LCPI13_0)(a3)
+; RV32IZFINX-NEXT:    flt.s a6, s0, a2
+; RV32IZFINX-NEXT:    addi a2, a6, -1
+; RV32IZFINX-NEXT:    and a0, a2, a0
+; RV32IZFINX-NEXT:    flt.s a4, a3, s0
 ; RV32IZFINX-NEXT:    neg a2, a4
 ; RV32IZFINX-NEXT:    or a0, a2, a0
 ; RV32IZFINX-NEXT:    feq.s a2, s0, s0
 ; RV32IZFINX-NEXT:    neg a2, a2
 ; RV32IZFINX-NEXT:    lui a5, 524288
 ; RV32IZFINX-NEXT:    lui a3, 524288
-; RV32IZFINX-NEXT:    beqz s1, .LBB13_4
+; RV32IZFINX-NEXT:    bnez a6, .LBB13_4
 ; RV32IZFINX-NEXT:  # %bb.3:
 ; RV32IZFINX-NEXT:    mv a3, a1
 ; RV32IZFINX-NEXT:  .LBB13_4:
 ; RV32IZFINX-NEXT:    and a0, a2, a0
 ; RV32IZFINX-NEXT:    beqz a4, .LBB13_6
 ; RV32IZFINX-NEXT:  # %bb.5:
 ; RV32IZFINX-NEXT:    addi a3, a5, -1
 ; RV32IZFINX-NEXT:  .LBB13_6:
 ; RV32IZFINX-NEXT:    and a1, a2, a3
 ; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
-; RV32IZFINX-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    addi sp, sp, 16
 ; RV32IZFINX-NEXT:    ret
 ;
 ; RV64IZFINX-LABEL: test_round_si64:
 ; RV64IZFINX:       # %bb.0:
 ; RV64IZFINX-NEXT:    fcvt.l.s a1, a0, rmm
 ; RV64IZFINX-NEXT:    feq.s a0, a0, a0
 ; RV64IZFINX-NEXT:    seqz a0, a0
; CHECKIZFINX-NEXT:    ret
   ret i32 %b
 }
 
 define i64 @test_round_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_round_ui64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IF-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    lui a0, 307200
 ; RV32IF-NEXT:    fmv.w.x fa5, a0
 ; RV32IF-NEXT:    fabs.s fa4, fa0
 ; RV32IF-NEXT:    flt.s a0, fa4, fa5
 ; RV32IF-NEXT:    beqz a0, .LBB15_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fcvt.w.s a0, fs0, rmm
 ; RV32IF-NEXT:    fcvt.s.w fa5, a0, rmm
 ; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
 ; RV32IF-NEXT:  .LBB15_2:
-; RV32IF-NEXT:    fmv.w.x fa5, zero
-; RV32IF-NEXT:    fle.s a0, fa5, fs0
-; RV32IF-NEXT:    neg s0, a0
 ; RV32IF-NEXT:    fmv.s fa0, fs0
 ; RV32IF-NEXT:    call __fixunssfdi@plt
+; RV32IF-NEXT:    fmv.w.x fa5, zero
 ; RV32IF-NEXT:    lui a2, %hi(.LCPI15_0)
-; RV32IF-NEXT:    flw fa5, %lo(.LCPI15_0)(a2)
-; RV32IF-NEXT:    and a0, s0, a0
-; RV32IF-NEXT:    flt.s a2, fa5, fs0
-; RV32IF-NEXT:    neg a2, a2
-; RV32IF-NEXT:    or a0, a2, a0
-; RV32IF-NEXT:    and a1, s0, a1
-; RV32IF-NEXT:    or a1, a2, a1
+; RV32IF-NEXT:    flw fa4, %lo(.LCPI15_0)(a2)
+; RV32IF-NEXT:    flt.s a2, fs0, fa5
+; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    and a0, a2, a0
+; RV32IF-NEXT:    flt.s a3, fa4, fs0
+; RV32IF-NEXT:    neg a3, a3
+; RV32IF-NEXT:    or a0, a3, a0
+; RV32IF-NEXT:    and a1, a2, a1
+; RV32IF-NEXT:    or a1, a3, a1
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IF-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_round_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rmm
 ; RV64IF-NEXT:    feq.s a1, fa0, fa0
 ; RV64IF-NEXT:    seqz a1, a1
 ; RV64IF-NEXT:    addi a1, a1, -1
 ; RV64IF-NEXT:    and a0, a1, a0
 ; RV64IF-NEXT:    ret
 ;
 ; RV32IZFINX-LABEL: test_round_ui64:
 ; RV32IZFINX:       # %bb.0:
 ; RV32IZFINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    mv s0, a0
 ; RV32IZFINX-NEXT:    lui a0, 307200
 ; RV32IZFINX-NEXT:    fabs.s a1, s0
 ; RV32IZFINX-NEXT:    flt.s a0, a1, a0
 ; RV32IZFINX-NEXT:    beqz a0, .LBB15_2
 ; RV32IZFINX-NEXT:  # %bb.1:
 ; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rmm
 ; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rmm
 ; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
 ; RV32IZFINX-NEXT:  .LBB15_2:
-; RV32IZFINX-NEXT:    fle.s a0, zero, s0
-; RV32IZFINX-NEXT:    neg s1, a0
 ; RV32IZFINX-NEXT:    mv a0, s0
 ; RV32IZFINX-NEXT:    call __fixunssfdi@plt
 ; RV32IZFINX-NEXT:    lui a2, %hi(.LCPI15_0)
 ; RV32IZFINX-NEXT:    lw a2, %lo(.LCPI15_0)(a2)
-; RV32IZFINX-NEXT:    and a0, s1, a0
+; RV32IZFINX-NEXT:    flt.s a3, s0, zero
+; RV32IZFINX-NEXT:    addi a3, a3, -1
+; RV32IZFINX-NEXT:    and a0, a3, a0
 ; RV32IZFINX-NEXT:    flt.s a2, a2, s0
 ; RV32IZFINX-NEXT:    neg a2, a2
 ; RV32IZFINX-NEXT:    or a0, a2, a0
-; RV32IZFINX-NEXT:    and a1, s1, a1
+; RV32IZFINX-NEXT:    and a1, a3, a1
 ; RV32IZFINX-NEXT:    or a1, a2, a1
 ; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    addi sp, sp, 16
 ; RV32IZFINX-NEXT:    ret
 ;
 ; RV64IZFINX-LABEL: test_round_ui64:
 ; RV64IZFINX:       # %bb.0:
 ; RV64IZFINX-NEXT:    fcvt.lu.s a1, a0, rmm
 ; RV64IZFINX-NEXT:    feq.s a0, a0, a0
 ; RV64IZFINX-NEXT:    seqz a0, a0

 ; RV32IF-NEXT:    beqz a0, .LBB17_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fcvt.w.s a0, fs0, rne
 ; RV32IF-NEXT:    fcvt.s.w fa5, a0, rne
 ; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
 ; RV32IF-NEXT:  .LBB17_2:
 ; RV32IF-NEXT:    lui a0, 913408
 ; RV32IF-NEXT:    fmv.w.x fa5, a0
-; RV32IF-NEXT:    fle.s s0, fa5, fs0
+; RV32IF-NEXT:    flt.s s0, fs0, fa5
 ; RV32IF-NEXT:    fmv.s fa0, fs0
 ; RV32IF-NEXT:    call __fixsfdi@plt
 ; RV32IF-NEXT:    lui a4, 524288
 ; RV32IF-NEXT:    lui a2, 524288
-; RV32IF-NEXT:    beqz s0, .LBB17_4
+; RV32IF-NEXT:    bnez s0, .LBB17_4
 ; RV32IF-NEXT:  # %bb.3:
 ; RV32IF-NEXT:    mv a2, a1
 ; RV32IF-NEXT:  .LBB17_4:
 ; RV32IF-NEXT:    lui a1, %hi(.LCPI17_0)
 ; RV32IF-NEXT:    flw fa5, %lo(.LCPI17_0)(a1)
 ; RV32IF-NEXT:    flt.s a3, fa5, fs0
 ; RV32IF-NEXT:    beqz a3, .LBB17_6
 ; RV32IF-NEXT:  # %bb.5:
 ; RV32IF-NEXT:    addi a2, a4, -1
 ; RV32IF-NEXT:  .LBB17_6:
 ; RV32IF-NEXT:    feq.s a1, fs0, fs0
 ; RV32IF-NEXT:    neg a4, a1
 ; RV32IF-NEXT:    and a1, a4, a2
-; RV32IF-NEXT:    neg a2, s0
-; RV32IF-NEXT:    and a0, a2, a0
+; RV32IF-NEXT:    addi s0, s0, -1
+; RV32IF-NEXT:    and a0, s0, a0
 ; RV32IF-NEXT:    neg a2, a3
 ; RV32IF-NEXT:    or a0, a2, a0
 ; RV32IF-NEXT:    and a0, a4, a0
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_roundeven_si64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.l.s a0, fa0, rne
 ; RV64IF-NEXT:    feq.s a1, fa0, fa0
 ; RV64IF-NEXT:    seqz a1, a1
 ; RV64IF-NEXT:    addi a1, a1, -1
 ; RV64IF-NEXT:    and a0, a1, a0
 ; RV64IF-NEXT:    ret
 ;
 ; RV32IZFINX-LABEL: test_roundeven_si64:
 ; RV32IZFINX:       # %bb.0:
 ; RV32IZFINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IZFINX-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    mv s0, a0
 ; RV32IZFINX-NEXT:    lui a0, 307200
 ; RV32IZFINX-NEXT:    fabs.s a1, s0
 ; RV32IZFINX-NEXT:    flt.s a0, a1, a0
 ; RV32IZFINX-NEXT:    beqz a0, .LBB17_2
 ; RV32IZFINX-NEXT:  # %bb.1:
 ; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rne
 ; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rne
 ; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
 ; RV32IZFINX-NEXT:  .LBB17_2:
-; RV32IZFINX-NEXT:    lui a0, 913408
-; RV32IZFINX-NEXT:    fle.s s1, a0, s0
-; RV32IZFINX-NEXT:    neg s2, s1
 ; RV32IZFINX-NEXT:    mv a0, s0
 ; RV32IZFINX-NEXT:    call __fixsfdi@plt
-; RV32IZFINX-NEXT:    lui a2, %hi(.LCPI17_0)
-; RV32IZFINX-NEXT:    lw a2, %lo(.LCPI17_0)(a2)
-; RV32IZFINX-NEXT:    and a0, s2, a0
-; RV32IZFINX-NEXT:    flt.s a4, a2, s0
+; RV32IZFINX-NEXT:    lui a2, 913408
+; RV32IZFINX-NEXT:    lui a3, %hi(.LCPI17_0)
+; RV32IZFINX-NEXT:    lw a3, %lo(.LCPI17_0)(a3)
+; RV32IZFINX-NEXT:    flt.s a6, s0, a2
+; RV32IZFINX-NEXT:    addi a2, a6, -1
+; RV32IZFINX-NEXT:    and a0, a2, a0
+; RV32IZFINX-NEXT:    flt.s a4, a3, s0
 ; RV32IZFINX-NEXT:    neg a2, a4
 ; RV32IZFINX-NEXT:    or a0, a2, a0
 ; RV32IZFINX-NEXT:    feq.s a2, s0, s0
 ; RV32IZFINX-NEXT:    neg a2, a2
 ; RV32IZFINX-NEXT:    lui a5, 524288
 ; RV32IZFINX-NEXT:    lui a3, 524288
-; RV32IZFINX-NEXT:    beqz s1, .LBB17_4
+; RV32IZFINX-NEXT:    bnez a6, .LBB17_4
 ; RV32IZFINX-NEXT:  # %bb.3:
 ; RV32IZFINX-NEXT:    mv a3, a1
 ; RV32IZFINX-NEXT:  .LBB17_4:
 ; RV32IZFINX-NEXT:    and a0, a2, a0
 ; RV32IZFINX-NEXT:    beqz a4, .LBB17_6
 ; RV32IZFINX-NEXT:  # %bb.5:
 ; RV32IZFINX-NEXT:    addi a3, a5, -1
 ; RV32IZFINX-NEXT:  .LBB17_6:
 ; RV32IZFINX-NEXT:    and a1, a2, a3
 ; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
-; RV32IZFINX-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    addi sp, sp, 16
 ; RV32IZFINX-NEXT:    ret
 ;
 ; RV64IZFINX-LABEL: test_roundeven_si64:
 ; RV64IZFINX:       # %bb.0:
 ; RV64IZFINX-NEXT:    fcvt.l.s a1, a0, rne
 ; RV64IZFINX-NEXT:    feq.s a0, a0, a0
 ; RV64IZFINX-NEXT:    seqz a0, a0
; CHECKIZFINX-NEXT:    ret
   ret i32 %b
 }
 
 define i64 @test_roundeven_ui64(float %x) nounwind {
 ; RV32IF-LABEL: test_roundeven_ui64:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi sp, sp, -16
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IF-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IF-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IF-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    fmv.s fs0, fa0
 ; RV32IF-NEXT:    lui a0, 307200
 ; RV32IF-NEXT:    fmv.w.x fa5, a0
 ; RV32IF-NEXT:    fabs.s fa4, fa0
 ; RV32IF-NEXT:    flt.s a0, fa4, fa5
 ; RV32IF-NEXT:    beqz a0, .LBB19_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    fcvt.w.s a0, fs0, rne
 ; RV32IF-NEXT:    fcvt.s.w fa5, a0, rne
 ; RV32IF-NEXT:    fsgnj.s fs0, fa5, fs0
 ; RV32IF-NEXT:  .LBB19_2:
-; RV32IF-NEXT:    fmv.w.x fa5, zero
-; RV32IF-NEXT:    fle.s a0, fa5, fs0
-; RV32IF-NEXT:    neg s0, a0
 ; RV32IF-NEXT:    fmv.s fa0, fs0
 ; RV32IF-NEXT:    call __fixunssfdi@plt
+; RV32IF-NEXT:    fmv.w.x fa5, zero
 ; RV32IF-NEXT:    lui a2, %hi(.LCPI19_0)
-; RV32IF-NEXT:    flw fa5, %lo(.LCPI19_0)(a2)
-; RV32IF-NEXT:    and a0, s0, a0
-; RV32IF-NEXT:    flt.s a2, fa5, fs0
-; RV32IF-NEXT:    neg a2, a2
-; RV32IF-NEXT:    or a0, a2, a0
-; RV32IF-NEXT:    and a1, s0, a1
-; RV32IF-NEXT:    or a1, a2, a1
+; RV32IF-NEXT:    flw fa4, %lo(.LCPI19_0)(a2)
+; RV32IF-NEXT:    flt.s a2, fs0, fa5
+; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    and a0, a2, a0
+; RV32IF-NEXT:    flt.s a3, fa4, fs0
+; RV32IF-NEXT:    neg a3, a3
+; RV32IF-NEXT:    or a0, a3, a0
+; RV32IF-NEXT:    and a1, a2, a1
+; RV32IF-NEXT:    or a1, a3, a1
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IF-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IF-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IF-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: test_roundeven_ui64:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.lu.s a0, fa0, rne
 ; RV64IF-NEXT:    feq.s a1, fa0, fa0
 ; RV64IF-NEXT:    seqz a1, a1
 ; RV64IF-NEXT:    addi a1, a1, -1
 ; RV64IF-NEXT:    and a0, a1, a0
 ; RV64IF-NEXT:    ret
 ;
 ; RV32IZFINX-LABEL: test_roundeven_ui64:
 ; RV32IZFINX:       # %bb.0:
 ; RV32IZFINX-NEXT:    addi sp, sp, -16
 ; RV32IZFINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZFINX-NEXT:    mv s0, a0
 ; RV32IZFINX-NEXT:    lui a0, 307200
 ; RV32IZFINX-NEXT:    fabs.s a1, s0
 ; RV32IZFINX-NEXT:    flt.s a0, a1, a0
 ; RV32IZFINX-NEXT:    beqz a0, .LBB19_2
 ; RV32IZFINX-NEXT:  # %bb.1:
 ; RV32IZFINX-NEXT:    fcvt.w.s a0, s0, rne
 ; RV32IZFINX-NEXT:    fcvt.s.w a0, a0, rne
 ; RV32IZFINX-NEXT:    fsgnj.s s0, a0, s0
 ; RV32IZFINX-NEXT:  .LBB19_2:
-; RV32IZFINX-NEXT:    fle.s a0, zero, s0
-; RV32IZFINX-NEXT:    neg s1, a0
 ; RV32IZFINX-NEXT:    mv a0, s0
 ; RV32IZFINX-NEXT:    call __fixunssfdi@plt
 ; RV32IZFINX-NEXT:    lui a2, %hi(.LCPI19_0)
 ; RV32IZFINX-NEXT:    lw a2, %lo(.LCPI19_0)(a2)
-; RV32IZFINX-NEXT:    and a0, s1, a0
+; RV32IZFINX-NEXT:    flt.s a3, s0, zero
+; RV32IZFINX-NEXT:    addi a3, a3, -1
+; RV32IZFINX-NEXT:    and a0, a3, a0
 ; RV32IZFINX-NEXT:    flt.s a2, a2, s0
 ; RV32IZFINX-NEXT:    neg a2, a2
 ; RV32IZFINX-NEXT:    or a0, a2, a0
-; RV32IZFINX-NEXT:    and a1, s1, a1
+; RV32IZFINX-NEXT:    and a1, a3, a1
 ; RV32IZFINX-NEXT:    or a1, a2, a1
 ; RV32IZFINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZFINX-NEXT:    addi sp, sp, 16
 ; RV32IZFINX-NEXT:    ret
 ;
 ; RV64IZFINX-LABEL: test_roundeven_ui64:
 ; RV64IZFINX:       # %bb.0:
 ; RV64IZFINX-NEXT:    fcvt.lu.s a1, a0, rne
 ; RV64IZFINX-NEXT:    feq.s a0, a0, a0
 ; RV64IZFINX-NEXT:    seqz a0, a0

llvm/test/CodeGen/RISCV/float-select-fcmp.ll

; CHECKZFINX-NEXT:    ret
   %1 = fcmp ueq float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ugt(float %a, float %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ugt:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fle.s a0, fa0, fa1
-; CHECK-NEXT:    beqz a0, .LBB9_2
+; CHECK-NEXT:    flt.s a0, fa1, fa0
+; CHECK-NEXT:    bnez a0, .LBB9_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.s fa0, fa1
 ; CHECK-NEXT:  .LBB9_2:
 ; CHECK-NEXT:    ret
 ;
 ; CHECKZFINX-LABEL: select_fcmp_ugt:
 ; CHECKZFINX:       # %bb.0:
-; CHECKZFINX-NEXT:    fle.s a2, a0, a1
-; CHECKZFINX-NEXT:    beqz a2, .LBB9_2
+; CHECKZFINX-NEXT:    flt.s a2, a1, a0
+; CHECKZFINX-NEXT:    bnez a2, .LBB9_2
 ; CHECKZFINX-NEXT:  # %bb.1:
 ; CHECKZFINX-NEXT:    mv a0, a1
 ; CHECKZFINX-NEXT:  .LBB9_2:
 ; CHECKZFINX-NEXT:    ret
   %1 = fcmp ugt float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_uge(float %a, float %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    flt.s a0, fa0, fa1
-; CHECK-NEXT:    beqz a0, .LBB10_2
+; CHECK-NEXT:    fle.s a0, fa1, fa0
+; CHECK-NEXT:    bnez a0, .LBB10_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.s fa0, fa1
 ; CHECK-NEXT:  .LBB10_2:
 ; CHECK-NEXT:    ret
 ;
 ; CHECKZFINX-LABEL: select_fcmp_uge:
 ; CHECKZFINX:       # %bb.0:
-; CHECKZFINX-NEXT:    flt.s a2, a0, a1
-; CHECKZFINX-NEXT:    beqz a2, .LBB10_2
+; CHECKZFINX-NEXT:    fle.s a2, a1, a0
+; CHECKZFINX-NEXT:    bnez a2, .LBB10_2
 ; CHECKZFINX-NEXT:  # %bb.1:
 ; CHECKZFINX-NEXT:    mv a0, a1
 ; CHECKZFINX-NEXT:  .LBB10_2:
 ; CHECKZFINX-NEXT:    ret
   %1 = fcmp uge float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ult(float %a, float %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ult:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fle.s a0, fa1, fa0
-; CHECK-NEXT:    beqz a0, .LBB11_2
+; CHECK-NEXT:    flt.s a0, fa0, fa1
+; CHECK-NEXT:    bnez a0, .LBB11_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.s fa0, fa1
 ; CHECK-NEXT:  .LBB11_2:
 ; CHECK-NEXT:    ret
 ;
 ; CHECKZFINX-LABEL: select_fcmp_ult:
 ; CHECKZFINX:       # %bb.0:
-; CHECKZFINX-NEXT:    fle.s a2, a1, a0
-; CHECKZFINX-NEXT:    beqz a2, .LBB11_2
+; CHECKZFINX-NEXT:    flt.s a2, a0, a1
+; CHECKZFINX-NEXT:    bnez a2, .LBB11_2
 ; CHECKZFINX-NEXT:  # %bb.1:
 ; CHECKZFINX-NEXT:    mv a0, a1
 ; CHECKZFINX-NEXT:  .LBB11_2:
 ; CHECKZFINX-NEXT:    ret
   %1 = fcmp ult float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ule(float %a, float %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ule:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    flt.s a0, fa1, fa0
-; CHECK-NEXT:    beqz a0, .LBB12_2
+; CHECK-NEXT:    fle.s a0, fa0, fa1
+; CHECK-NEXT:    bnez a0, .LBB12_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.s fa0, fa1
 ; CHECK-NEXT:  .LBB12_2:
 ; CHECK-NEXT:    ret
 ;
 ; CHECKZFINX-LABEL: select_fcmp_ule:
 ; CHECKZFINX:       # %bb.0:
-; CHECKZFINX-NEXT:    flt.s a2, a1, a0
-; CHECKZFINX-NEXT:    beqz a2, .LBB12_2
+; CHECKZFINX-NEXT:    fle.s a2, a0, a1
+; CHECKZFINX-NEXT:    bnez a2, .LBB12_2
 ; CHECKZFINX-NEXT:  # %bb.1:
 ; CHECKZFINX-NEXT:    mv a0, a1
 ; CHECKZFINX-NEXT:  .LBB12_2:
 ; CHECKZFINX-NEXT:    ret
   %1 = fcmp ule float %a, %b
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
; CHECKZFINX-NEXT:    ret
   %1 = fcmp fast oeq float %a, %b
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }
 
 define signext i32 @select_fcmp_uge_negone_zero(float %a, float %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge_negone_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fle.s a0, fa0, fa1
-; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    flt.s a0, fa1, fa0
+; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
 ;
 ; CHECKZFINX-LABEL: select_fcmp_uge_negone_zero:
 ; CHECKZFINX:       # %bb.0:
-; CHECKZFINX-NEXT:    fle.s a0, a0, a1
-; CHECKZFINX-NEXT:    addi a0, a0, -1
+; CHECKZFINX-NEXT:    flt.s a0, a1, a0
+; CHECKZFINX-NEXT:    neg a0, a0
 ; CHECKZFINX-NEXT:    ret
   %1 = fcmp ugt float %a, %b
   %2 = select i1 %1, i32 -1, i32 0
   ret i32 %2
 }
 
 define signext i32 @select_fcmp_uge_1_2(float %a, float %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge_1_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fle.s a0, fa0, fa1
-; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    flt.s a0, fa1, fa0
+; CHECK-NEXT:    li a1, 2
+; CHECK-NEXT:    sub a0, a1, a0
 ; CHECK-NEXT:    ret
 ;
 ; CHECKZFINX-LABEL: select_fcmp_uge_1_2:
 ; CHECKZFINX:       # %bb.0:
-; CHECKZFINX-NEXT:    fle.s a0, a0, a1
-; CHECKZFINX-NEXT:    addi a0, a0, 1
+; CHECKZFINX-NEXT:    flt.s a0, a1, a0
+; CHECKZFINX-NEXT:    li a1, 2
+; CHECKZFINX-NEXT:    sub a0, a1, a0
 ; CHECKZFINX-NEXT:    ret
   %1 = fcmp ugt float %a, %b
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/float-select-icmp.ll

; CHECKZFINX-NEXT:    ret
   %1 = icmp slt i32 %a, 1
   %2 = select i1 %1, float 1.000000e+00, float 0.000000e+00
   ret float %2
 }
 
 define float @select_icmp_sgt_zero(i32 signext %a) {
 ; CHECK-LABEL: select_icmp_sgt_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sgtz a0, a0
-; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    slti a0, a0, 1
 ; CHECK-NEXT:    fcvt.s.w fa0, a0
 ; CHECK-NEXT:    ret
 ;
 ; CHECKZFINX-LABEL: select_icmp_sgt_zero:
 ; CHECKZFINX:       # %bb.0:
-; CHECKZFINX-NEXT:    sgtz a0, a0
-; CHECKZFINX-NEXT:    xori a0, a0, 1
+; CHECKZFINX-NEXT:    slti a0, a0, 1
 ; CHECKZFINX-NEXT:    fcvt.s.w a0, a0
 ; CHECKZFINX-NEXT:    ret
   %1 = icmp sgt i32 %a, 0
   %2 = select i1 %1, float 0.000000e+00, float 1.000000e+00
   ret float %2
 }

llvm/test/CodeGen/RISCV/half-br-fcmp.ll

 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_ugt(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: br_fcmp_ugt:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fle.h a0, fa0, fa1
-; RV32IZFH-NEXT:    beqz a0, .LBB10_2
+; RV32IZFH-NEXT:    flt.h a0, fa1, fa0
+; RV32IZFH-NEXT:    bnez a0, .LBB10_2
 ; RV32IZFH-NEXT:  # %bb.1: # %if.else
 ; RV32IZFH-NEXT:    ret
 ; RV32IZFH-NEXT:  .LBB10_2: # %if.then
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    call abort@plt
 ;
 ; RV64IZFH-LABEL: br_fcmp_ugt:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fle.h a0, fa0, fa1
-; RV64IZFH-NEXT:    beqz a0, .LBB10_2
+; RV64IZFH-NEXT:    flt.h a0, fa1, fa0
+; RV64IZFH-NEXT:    bnez a0, .LBB10_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB10_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
 ; RV32IZHINX-LABEL: br_fcmp_ugt:
 ; RV32IZHINX:       # %bb.0:
-; RV32IZHINX-NEXT:    fle.h a0, a0, a1
-; RV32IZHINX-NEXT:    beqz a0, .LBB10_2
+; RV32IZHINX-NEXT:    flt.h a0, a1, a0
+; RV32IZHINX-NEXT:    bnez a0, .LBB10_2
 ; RV32IZHINX-NEXT:  # %bb.1: # %if.else
 ; RV32IZHINX-NEXT:    ret
 ; RV32IZHINX-NEXT:  .LBB10_2: # %if.then
 ; RV32IZHINX-NEXT:    addi sp, sp, -16
 ; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    call abort@plt
 ;
 ; RV64IZHINX-LABEL: br_fcmp_ugt:
 ; RV64IZHINX:       # %bb.0:
-; RV64IZHINX-NEXT:    fle.h a0, a0, a1
-; RV64IZHINX-NEXT:    beqz a0, .LBB10_2
+; RV64IZHINX-NEXT:    flt.h a0, a1, a0
+; RV64IZHINX-NEXT:    bnez a0, .LBB10_2
 ; RV64IZHINX-NEXT:  # %bb.1: # %if.else
 ; RV64IZHINX-NEXT:    ret
 ; RV64IZHINX-NEXT:  .LBB10_2: # %if.then
 ; RV64IZHINX-NEXT:    addi sp, sp, -16
 ; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZHINX-NEXT:    call abort@plt
 ;
 ; RV32IZFHMIN-LABEL: br_fcmp_ugt:
 ; RV32IZFHMIN:       # %bb.0:
-; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
-; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
-; RV32IZFHMIN-NEXT:    fle.s a0, fa4, fa5
-; RV32IZFHMIN-NEXT:    beqz a0, .LBB10_2
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa1
+; RV32IZFHMIN-NEXT:    flt.s a0, fa4, fa5
+; RV32IZFHMIN-NEXT:    bnez a0, .LBB10_2
 ; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZFHMIN-NEXT:    ret
 ; RV32IZFHMIN-NEXT:  .LBB10_2: # %if.then
 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    call abort@plt
 ;
 ; RV64IZFHMIN-LABEL: br_fcmp_ugt:
 ; RV64IZFHMIN:       # %bb.0:
-; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
-; RV64IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
-; RV64IZFHMIN-NEXT:    fle.s a0, fa4, fa5
-; RV64IZFHMIN-NEXT:    beqz a0, .LBB10_2
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa4, fa1
+; RV64IZFHMIN-NEXT:    flt.s a0, fa4, fa5
+; RV64IZFHMIN-NEXT:    bnez a0, .LBB10_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB10_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
 ;
 ; RV32IZHINXMIN-LABEL: br_fcmp_ugt:
 ; RV32IZHINXMIN:       # %bb.0:
-; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
 ; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
-; RV32IZHINXMIN-NEXT:    fle.s a0, a0, a1
-; RV32IZHINXMIN-NEXT:    beqz a0, .LBB10_2
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    flt.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:    bnez a0, .LBB10_2
 ; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZHINXMIN-NEXT:    ret
 ; RV32IZHINXMIN-NEXT:  .LBB10_2: # %if.then
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
 ; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    call abort@plt
 ;
 ; RV64IZHINXMIN-LABEL: br_fcmp_ugt:
 ; RV64IZHINXMIN:       # %bb.0:
-; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
 ; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
-; RV64IZHINXMIN-NEXT:    fle.s a0, a0, a1
-; RV64IZHINXMIN-NEXT:    beqz a0, .LBB10_2
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    flt.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:    bnez a0, .LBB10_2
 ; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZHINXMIN-NEXT:    ret
 ; RV64IZHINXMIN-NEXT:  .LBB10_2: # %if.then
 ; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
 ; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp ugt half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_uge(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: br_fcmp_uge:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV32IZFH-NEXT:    beqz a0, .LBB11_2
+; RV32IZFH-NEXT:    fle.h a0, fa1, fa0
+; RV32IZFH-NEXT:    bnez a0, .LBB11_2
 ; RV32IZFH-NEXT:  # %bb.1: # %if.else
 ; RV32IZFH-NEXT:    ret
 ; RV32IZFH-NEXT:  .LBB11_2: # %if.then
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    call abort@plt
 ;
 ; RV64IZFH-LABEL: br_fcmp_uge:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
-; RV64IZFH-NEXT:    beqz a0, .LBB11_2
+; RV64IZFH-NEXT:    fle.h a0, fa1, fa0
+; RV64IZFH-NEXT:    bnez a0, .LBB11_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB11_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
 ; RV32IZHINX-LABEL: br_fcmp_uge:
 ; RV32IZHINX:       # %bb.0:
-; RV32IZHINX-NEXT:    flt.h a0, a0, a1
-; RV32IZHINX-NEXT:    beqz a0, .LBB11_2
+; RV32IZHINX-NEXT:    fle.h a0, a1, a0
+; RV32IZHINX-NEXT:    bnez a0, .LBB11_2
 ; RV32IZHINX-NEXT:  # %bb.1: # %if.else
 ; RV32IZHINX-NEXT:    ret
 ; RV32IZHINX-NEXT:  .LBB11_2: # %if.then
 ; RV32IZHINX-NEXT:    addi sp, sp, -16
 ; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    call abort@plt
 ;
 ; RV64IZHINX-LABEL: br_fcmp_uge:
 ; RV64IZHINX:       # %bb.0:
-; RV64IZHINX-NEXT:    flt.h a0, a0, a1
-; RV64IZHINX-NEXT:    beqz a0, .LBB11_2
+; RV64IZHINX-NEXT:    fle.h a0, a1, a0
+; RV64IZHINX-NEXT:    bnez a0, .LBB11_2
 ; RV64IZHINX-NEXT:  # %bb.1: # %if.else
 ; RV64IZHINX-NEXT:    ret
 ; RV64IZHINX-NEXT:  .LBB11_2: # %if.then
 ; RV64IZHINX-NEXT:    addi sp, sp, -16
 ; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZHINX-NEXT:    call abort@plt
 ;
 ; RV32IZFHMIN-LABEL: br_fcmp_uge:
 ; RV32IZFHMIN:       # %bb.0:
-; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
-; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
-; RV32IZFHMIN-NEXT:    flt.s a0, fa4, fa5
-; RV32IZFHMIN-NEXT:    beqz a0, .LBB11_2
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa1
+; RV32IZFHMIN-NEXT:    fle.s a0, fa4, fa5
+; RV32IZFHMIN-NEXT:    bnez a0, .LBB11_2
 ; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZFHMIN-NEXT:    ret
 ; RV32IZFHMIN-NEXT:  .LBB11_2: # %if.then
 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    call abort@plt
 ;
 ; RV64IZFHMIN-LABEL: br_fcmp_uge:
 ; RV64IZFHMIN:       # %bb.0:
-; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
-; RV64IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
-; RV64IZFHMIN-NEXT:    flt.s a0, fa4, fa5
-; RV64IZFHMIN-NEXT:    beqz a0, .LBB11_2
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa4, fa1
+; RV64IZFHMIN-NEXT:    fle.s a0, fa4, fa5
+; RV64IZFHMIN-NEXT:    bnez a0, .LBB11_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB11_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
 ;
 ; RV32IZHINXMIN-LABEL: br_fcmp_uge:
 ; RV32IZHINXMIN:       # %bb.0:
-; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
 ; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
-; RV32IZHINXMIN-NEXT:    flt.s a0, a0, a1
-; RV32IZHINXMIN-NEXT:    beqz a0, .LBB11_2
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    fle.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:    bnez a0, .LBB11_2
 ; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZHINXMIN-NEXT:    ret
 ; RV32IZHINXMIN-NEXT:  .LBB11_2: # %if.then
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
 ; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    call abort@plt
 ;
 ; RV64IZHINXMIN-LABEL: br_fcmp_uge:
 ; RV64IZHINXMIN:       # %bb.0:
-; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
 ; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
-; RV64IZHINXMIN-NEXT:    flt.s a0, a0, a1
-; RV64IZHINXMIN-NEXT:    beqz a0, .LBB11_2
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    fle.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:    bnez a0, .LBB11_2
 ; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZHINXMIN-NEXT:    ret
 ; RV64IZHINXMIN-NEXT:  .LBB11_2: # %if.then
 ; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
 ; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp uge half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_ult(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: br_fcmp_ult:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV32IZFH-NEXT:    beqz a0, .LBB12_2
+; RV32IZFH-NEXT:    flt.h a0, fa0, fa1
+; RV32IZFH-NEXT:    bnez a0, .LBB12_2
 ; RV32IZFH-NEXT:  # %bb.1: # %if.else
 ; RV32IZFH-NEXT:    ret
 ; RV32IZFH-NEXT:  .LBB12_2: # %if.then
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    call abort@plt
 ;
 ; RV64IZFH-LABEL: br_fcmp_ult:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    fle.h a0, fa1, fa0
-; RV64IZFH-NEXT:    beqz a0, .LBB12_2
+; RV64IZFH-NEXT:    flt.h a0, fa0, fa1
+; RV64IZFH-NEXT:    bnez a0, .LBB12_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB12_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
 ; RV32IZHINX-LABEL: br_fcmp_ult:
 ; RV32IZHINX:       # %bb.0:
-; RV32IZHINX-NEXT:    fle.h a0, a1, a0
-; RV32IZHINX-NEXT:    beqz a0, .LBB12_2
+; RV32IZHINX-NEXT:    flt.h a0, a0, a1
+; RV32IZHINX-NEXT:    bnez a0, .LBB12_2
 ; RV32IZHINX-NEXT:  # %bb.1: # %if.else
 ; RV32IZHINX-NEXT:    ret
 ; RV32IZHINX-NEXT:  .LBB12_2: # %if.then
 ; RV32IZHINX-NEXT:    addi sp, sp, -16
 ; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    call abort@plt
 ;
 ; RV64IZHINX-LABEL: br_fcmp_ult:
 ; RV64IZHINX:       # %bb.0:
-; RV64IZHINX-NEXT:    fle.h a0, a1, a0
-; RV64IZHINX-NEXT:    beqz a0, .LBB12_2
+; RV64IZHINX-NEXT:    flt.h a0, a0, a1
+; RV64IZHINX-NEXT:    bnez a0, .LBB12_2
 ; RV64IZHINX-NEXT:  # %bb.1: # %if.else
 ; RV64IZHINX-NEXT:    ret
 ; RV64IZHINX-NEXT:  .LBB12_2: # %if.then
 ; RV64IZHINX-NEXT:    addi sp, sp, -16
 ; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZHINX-NEXT:    call abort@plt
 ;
 ; RV32IZFHMIN-LABEL: br_fcmp_ult:
 ; RV32IZFHMIN:       # %bb.0:
-; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
-; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa1
-; RV32IZFHMIN-NEXT:    fle.s a0, fa4, fa5
-; RV32IZFHMIN-NEXT:    beqz a0, .LBB12_2
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
+; RV32IZFHMIN-NEXT:    flt.s a0, fa4, fa5
+; RV32IZFHMIN-NEXT:    bnez a0, .LBB12_2
 ; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZFHMIN-NEXT:    ret
 ; RV32IZFHMIN-NEXT:  .LBB12_2: # %if.then
 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    call abort@plt
 ;
 ; RV64IZFHMIN-LABEL: br_fcmp_ult:
 ; RV64IZFHMIN:       # %bb.0:
-; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
-; RV64IZFHMIN-NEXT:    fcvt.s.h fa4, fa1
-; RV64IZFHMIN-NEXT:    fle.s a0, fa4, fa5
-; RV64IZFHMIN-NEXT:    beqz a0, .LBB12_2
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
+; RV64IZFHMIN-NEXT:    flt.s a0, fa4, fa5
+; RV64IZFHMIN-NEXT:    bnez a0, .LBB12_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB12_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
 ;
 ; RV32IZHINXMIN-LABEL: br_fcmp_ult:
 ; RV32IZHINXMIN:       # %bb.0:
-; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
 ; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
-; RV32IZHINXMIN-NEXT:    fle.s a0, a1, a0
-; RV32IZHINXMIN-NEXT:    beqz a0, .LBB12_2
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    flt.s a0, a0, a1
+; RV32IZHINXMIN-NEXT:    bnez a0, .LBB12_2
 ; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZHINXMIN-NEXT:    ret
 ; RV32IZHINXMIN-NEXT:  .LBB12_2: # %if.then
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
 ; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    call abort@plt
 ;
 ; RV64IZHINXMIN-LABEL: br_fcmp_ult:
 ; RV64IZHINXMIN:       # %bb.0:
-; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
 ; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
-; RV64IZHINXMIN-NEXT:    fle.s a0, a1, a0
-; RV64IZHINXMIN-NEXT:    beqz a0, .LBB12_2
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    flt.s a0, a0, a1
+; RV64IZHINXMIN-NEXT:    bnez a0, .LBB12_2
 ; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZHINXMIN-NEXT:    ret
 ; RV64IZHINXMIN-NEXT:  .LBB12_2: # %if.then
 ; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
 ; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp ult half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }
 
 define void @br_fcmp_ule(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: br_fcmp_ule:
 ; RV32IZFH:       # %bb.0:
-; RV32IZFH-NEXT:    flt.h a0, fa1, fa0
-; RV32IZFH-NEXT:    beqz a0, .LBB13_2
+; RV32IZFH-NEXT:    fle.h a0, fa0, fa1
+; RV32IZFH-NEXT:    bnez a0, .LBB13_2
 ; RV32IZFH-NEXT:  # %bb.1: # %if.else
 ; RV32IZFH-NEXT:    ret
 ; RV32IZFH-NEXT:  .LBB13_2: # %if.then
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    call abort@plt
 ;
 ; RV64IZFH-LABEL: br_fcmp_ule:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    flt.h a0, fa1, fa0
-; RV64IZFH-NEXT:    beqz a0, .LBB13_2
+; RV64IZFH-NEXT:    fle.h a0, fa0, fa1
+; RV64IZFH-NEXT:    bnez a0, .LBB13_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB13_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
 ; RV32IZHINX-LABEL: br_fcmp_ule:
 ; RV32IZHINX:       # %bb.0:
-; RV32IZHINX-NEXT:    flt.h a0, a1, a0
-; RV32IZHINX-NEXT:    beqz a0, .LBB13_2
+; RV32IZHINX-NEXT:    fle.h a0, a0, a1
+; RV32IZHINX-NEXT:    bnez a0, .LBB13_2
 ; RV32IZHINX-NEXT:  # %bb.1: # %if.else
 ; RV32IZHINX-NEXT:    ret
 ; RV32IZHINX-NEXT:  .LBB13_2: # %if.then
 ; RV32IZHINX-NEXT:    addi sp, sp, -16
 ; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    call abort@plt
 ;
 ; RV64IZHINX-LABEL: br_fcmp_ule:
 ; RV64IZHINX:       # %bb.0:
-; RV64IZHINX-NEXT:    flt.h a0, a1, a0
-; RV64IZHINX-NEXT:    beqz a0, .LBB13_2
+; RV64IZHINX-NEXT:    fle.h a0, a0, a1
+; RV64IZHINX-NEXT:    bnez a0, .LBB13_2
 ; RV64IZHINX-NEXT:  # %bb.1: # %if.else
 ; RV64IZHINX-NEXT:    ret
 ; RV64IZHINX-NEXT:  .LBB13_2: # %if.then
 ; RV64IZHINX-NEXT:    addi sp, sp, -16
 ; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZHINX-NEXT:    call abort@plt
 ;
 ; RV32IZFHMIN-LABEL: br_fcmp_ule:
 ; RV32IZFHMIN:       # %bb.0:
-; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
-; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa1
-; RV32IZFHMIN-NEXT:    flt.s a0, fa4, fa5
-; RV32IZFHMIN-NEXT:    beqz a0, .LBB13_2
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
+; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
+; RV32IZFHMIN-NEXT:    fle.s a0, fa4, fa5
+; RV32IZFHMIN-NEXT:    bnez a0, .LBB13_2
 ; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZFHMIN-NEXT:    ret
 ; RV32IZFHMIN-NEXT:  .LBB13_2: # %if.then
 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    call abort@plt
 ;
 ; RV64IZFHMIN-LABEL: br_fcmp_ule:
 ; RV64IZFHMIN:       # %bb.0:
-; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
-; RV64IZFHMIN-NEXT:    fcvt.s.h fa4, fa1
-; RV64IZFHMIN-NEXT:    flt.s a0, fa4, fa5
-; RV64IZFHMIN-NEXT:    beqz a0, .LBB13_2
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
+; RV64IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
+; RV64IZFHMIN-NEXT:    fle.s a0, fa4, fa5
+; RV64IZFHMIN-NEXT:    bnez a0, .LBB13_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB13_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
 ;
 ; RV32IZHINXMIN-LABEL: br_fcmp_ule:
 ; RV32IZHINXMIN:       # %bb.0:
-; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
 ; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
-; RV32IZHINXMIN-NEXT:    flt.s a0, a1, a0
-; RV32IZHINXMIN-NEXT:    beqz a0, .LBB13_2
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fle.s a0, a0, a1
+; RV32IZHINXMIN-NEXT:    bnez a0, .LBB13_2
 ; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZHINXMIN-NEXT:    ret
 ; RV32IZHINXMIN-NEXT:  .LBB13_2: # %if.then
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
 ; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    call abort@plt
 ;
 ; RV64IZHINXMIN-LABEL: br_fcmp_ule:
 ; RV64IZHINXMIN:       # %bb.0:
-; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
 ; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
-; RV64IZHINXMIN-NEXT:    flt.s a0, a1, a0
-; RV64IZHINXMIN-NEXT:    beqz a0, .LBB13_2
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fle.s a0, a0, a1
+; RV64IZHINXMIN-NEXT:    bnez a0, .LBB13_2
 ; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZHINXMIN-NEXT:    ret
 ; RV64IZHINXMIN-NEXT:  .LBB13_2: # %if.then
 ; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
 ; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp ule half %a, %b
   br i1 %1, label %if.then, label %if.else

llvm/test/CodeGen/RISCV/half-convert.ll

 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, fa0
 ; RV32IZFH-NEXT:    lui a0, 913408
 ; RV32IZFH-NEXT:    fmv.w.x fa5, a0
-; RV32IZFH-NEXT:    fle.s s0, fa5, fs0
+; RV32IZFH-NEXT:    flt.s s0, fs0, fa5
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixsfdi@plt
 ; RV32IZFH-NEXT:    lui a4, 524288
 ; RV32IZFH-NEXT:    lui a2, 524288
-; RV32IZFH-NEXT:    beqz s0, .LBB10_2
+; RV32IZFH-NEXT:    bnez s0, .LBB10_2
 ; RV32IZFH-NEXT:  # %bb.1: # %start
 ; RV32IZFH-NEXT:    mv a2, a1
 ; RV32IZFH-NEXT:  .LBB10_2: # %start
 ; RV32IZFH-NEXT:    lui a1, %hi(.LCPI10_0)
 ; RV32IZFH-NEXT:    flw fa5, %lo(.LCPI10_0)(a1)
 ; RV32IZFH-NEXT:    flt.s a3, fa5, fs0
 ; RV32IZFH-NEXT:    beqz a3, .LBB10_4
 ; RV32IZFH-NEXT:  # %bb.3:
 ; RV32IZFH-NEXT:    addi a2, a4, -1
 ; RV32IZFH-NEXT:  .LBB10_4: # %start
 ; RV32IZFH-NEXT:    feq.s a1, fs0, fs0
 ; RV32IZFH-NEXT:    neg a4, a1
 ; RV32IZFH-NEXT:    and a1, a4, a2
 ; RV32IZFH-NEXT:    neg a2, a3
-; RV32IZFH-NEXT:    neg a3, s0
-; RV32IZFH-NEXT:    and a0, a3, a0
+; RV32IZFH-NEXT:    addi s0, s0, -1
+; RV32IZFH-NEXT:    and a0, s0, a0
 ; RV32IZFH-NEXT:    or a0, a2, a0
 ; RV32IZFH-NEXT:    and a0, a4, a0
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;

 ; RV32IDZFH:       # %bb.0: # %start
 ; RV32IDZFH-NEXT:    addi sp, sp, -16
 ; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IDZFH-NEXT:    fcvt.s.h fs0, fa0
 ; RV32IDZFH-NEXT:    lui a0, 913408
 ; RV32IDZFH-NEXT:    fmv.w.x fa5, a0
-; RV32IDZFH-NEXT:    fle.s s0, fa5, fs0
+; RV32IDZFH-NEXT:    flt.s s0, fs0, fa5
 ; RV32IDZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IDZFH-NEXT:    call __fixsfdi@plt
 ; RV32IDZFH-NEXT:    lui a4, 524288
 ; RV32IDZFH-NEXT:    lui a2, 524288
-; RV32IDZFH-NEXT:    beqz s0, .LBB10_2
+; RV32IDZFH-NEXT:    bnez s0, .LBB10_2
 ; RV32IDZFH-NEXT:  # %bb.1: # %start
 ; RV32IDZFH-NEXT:    mv a2, a1
 ; RV32IDZFH-NEXT:  .LBB10_2: # %start
 ; RV32IDZFH-NEXT:    lui a1, %hi(.LCPI10_0)
 ; RV32IDZFH-NEXT:    flw fa5, %lo(.LCPI10_0)(a1)
 ; RV32IDZFH-NEXT:    flt.s a3, fa5, fs0
 ; RV32IDZFH-NEXT:    beqz a3, .LBB10_4
 ; RV32IDZFH-NEXT:  # %bb.3:
 ; RV32IDZFH-NEXT:    addi a2, a4, -1
 ; RV32IDZFH-NEXT:  .LBB10_4: # %start
 ; RV32IDZFH-NEXT:    feq.s a1, fs0, fs0
 ; RV32IDZFH-NEXT:    neg a4, a1
 ; RV32IDZFH-NEXT:    and a1, a4, a2
 ; RV32IDZFH-NEXT:    neg a2, a3
-; RV32IDZFH-NEXT:    neg a3, s0
-; RV32IDZFH-NEXT:    and a0, a3, a0
+; RV32IDZFH-NEXT:    addi s0, s0, -1
+; RV32IDZFH-NEXT:    and a0, s0, a0
 ; RV32IDZFH-NEXT:    or a0, a2, a0
 ; RV32IDZFH-NEXT:    and a0, a4, a0
 ; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
 ;

 ; RV32IZHINX-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI10_0)
 ; RV32IZHINX-NEXT:    lw a1, %lo(.LCPI10_0)(a1)
 ; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
 ; RV32IZHINX-NEXT:    flt.s s1, a1, s0
 ; RV32IZHINX-NEXT:    neg s2, s1
 ; RV32IZHINX-NEXT:    lui a0, 913408
-; RV32IZHINX-NEXT:    fle.s s3, a0, s0
-; RV32IZHINX-NEXT:    neg s4, s3
+; RV32IZHINX-NEXT:    flt.s s3, s0, a0
+; RV32IZHINX-NEXT:    addi s4, s3, -1
 ; RV32IZHINX-NEXT:    mv a0, s0
 ; RV32IZHINX-NEXT:    call __fixsfdi@plt
 ; RV32IZHINX-NEXT:    and a0, s4, a0
 ; RV32IZHINX-NEXT:    or a0, s2, a0
 ; RV32IZHINX-NEXT:    feq.s a2, s0, s0
 ; RV32IZHINX-NEXT:    neg a2, a2
 ; RV32IZHINX-NEXT:    lui a4, 524288
 ; RV32IZHINX-NEXT:    lui a3, 524288
-; RV32IZHINX-NEXT:    beqz s3, .LBB10_2
+; RV32IZHINX-NEXT:    bnez s3, .LBB10_2
 ; RV32IZHINX-NEXT:  # %bb.1: # %start
 ; RV32IZHINX-NEXT:    mv a3, a1
 ; RV32IZHINX-NEXT:  .LBB10_2: # %start
 ; RV32IZHINX-NEXT:    and a0, a2, a0
 ; RV32IZHINX-NEXT:    beqz s1, .LBB10_4
 ; RV32IZHINX-NEXT:  # %bb.3:
 ; RV32IZHINX-NEXT:    addi a3, a4, -1
 ; RV32IZHINX-NEXT:  .LBB10_4: # %start

 ; RV32IZDINXZHINX-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; RV32IZDINXZHINX-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
 ; RV32IZDINXZHINX-NEXT:    lui a1, %hi(.LCPI10_0)
 ; RV32IZDINXZHINX-NEXT:    lw a1, %lo(.LCPI10_0)(a1)
 ; RV32IZDINXZHINX-NEXT:    fcvt.s.h s0, a0
 ; RV32IZDINXZHINX-NEXT:    flt.s s1, a1, s0
 ; RV32IZDINXZHINX-NEXT:    neg s2, s1
 ; RV32IZDINXZHINX-NEXT:    lui a0, 913408
-; RV32IZDINXZHINX-NEXT:    fle.s s3, a0, s0
-; RV32IZDINXZHINX-NEXT:    neg s4, s3
+; RV32IZDINXZHINX-NEXT:    flt.s s3, s0, a0
+; RV32IZDINXZHINX-NEXT:    addi s4, s3, -1
 ; RV32IZDINXZHINX-NEXT:    mv a0, s0
 ; RV32IZDINXZHINX-NEXT:    call __fixsfdi@plt
 ; RV32IZDINXZHINX-NEXT:    and a0, s4, a0
 ; RV32IZDINXZHINX-NEXT:    or a0, s2, a0
 ; RV32IZDINXZHINX-NEXT:    feq.s a2, s0, s0
 ; RV32IZDINXZHINX-NEXT:    neg a2, a2
 ; RV32IZDINXZHINX-NEXT:    lui a4, 524288
 ; RV32IZDINXZHINX-NEXT:    lui a3, 524288
-; RV32IZDINXZHINX-NEXT:    beqz s3, .LBB10_2
+; RV32IZDINXZHINX-NEXT:    bnez s3, .LBB10_2
 ; RV32IZDINXZHINX-NEXT:  # %bb.1: # %start
 ; RV32IZDINXZHINX-NEXT:    mv a3, a1
 ; RV32IZDINXZHINX-NEXT:  .LBB10_2: # %start
 ; RV32IZDINXZHINX-NEXT:    and a0, a2, a0
 ; RV32IZDINXZHINX-NEXT:    beqz s1, .LBB10_4
 ; RV32IZDINXZHINX-NEXT:  # %bb.3:
 ; RV32IZDINXZHINX-NEXT:    addi a3, a4, -1
 ; RV32IZDINXZHINX-NEXT:  .LBB10_4: # %start

 ; RV32IFZFHMIN:       # %bb.0: # %start
 ; RV32IFZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IFZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IFZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IFZFHMIN-NEXT:    fcvt.s.h fs0, fa0
 ; RV32IFZFHMIN-NEXT:    lui a0, 913408
 ; RV32IFZFHMIN-NEXT:    fmv.w.x fa5, a0
-; RV32IFZFHMIN-NEXT:    fle.s s0, fa5, fs0
+; RV32IFZFHMIN-NEXT:    flt.s s0, fs0, fa5
 ; RV32IFZFHMIN-NEXT:    fmv.s fa0, fs0
 ; RV32IFZFHMIN-NEXT:    call __fixsfdi@plt
 ; RV32IFZFHMIN-NEXT:    lui a4, 524288
 ; RV32IFZFHMIN-NEXT:    lui a2, 524288
-; RV32IFZFHMIN-NEXT:    beqz s0, .LBB10_2
+; RV32IFZFHMIN-NEXT:    bnez s0, .LBB10_2
 ; RV32IFZFHMIN-NEXT:  # %bb.1: # %start
 ; RV32IFZFHMIN-NEXT:    mv a2, a1
 ; RV32IFZFHMIN-NEXT:  .LBB10_2: # %start
 ; RV32IFZFHMIN-NEXT:    lui a1, %hi(.LCPI10_0)
 ; RV32IFZFHMIN-NEXT:    flw fa5, %lo(.LCPI10_0)(a1)
 ; RV32IFZFHMIN-NEXT:    flt.s a3, fa5, fs0
 ; RV32IFZFHMIN-NEXT:    beqz a3, .LBB10_4
 ; RV32IFZFHMIN-NEXT:  # %bb.3:
 ; RV32IFZFHMIN-NEXT:    addi a2, a4, -1
 ; RV32IFZFHMIN-NEXT:  .LBB10_4: # %start
 ; RV32IFZFHMIN-NEXT:    feq.s a1, fs0, fs0
 ; RV32IFZFHMIN-NEXT:    neg a4, a1
 ; RV32IFZFHMIN-NEXT:    and a1, a4, a2
 ; RV32IFZFHMIN-NEXT:    neg a2, a3
-; RV32IFZFHMIN-NEXT:    neg a3, s0
-; RV32IFZFHMIN-NEXT:    and a0, a3, a0
+; RV32IFZFHMIN-NEXT:    addi s0, s0, -1
+; RV32IFZFHMIN-NEXT:    and a0, s0, a0
 ; RV32IFZFHMIN-NEXT:    or a0, a2, a0
 ; RV32IFZFHMIN-NEXT:    and a0, a4, a0
 ; RV32IFZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IFZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IFZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32IFZFHMIN-NEXT:    ret
 ;

 ; RV32IDZFHMIN:       # %bb.0: # %start
 ; RV32IDZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IDZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IDZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IDZFHMIN-NEXT:    fsd fs0, 0(sp) # 8-byte Folded Spill
 ; RV32IDZFHMIN-NEXT:    fcvt.s.h fs0, fa0
 ; RV32IDZFHMIN-NEXT:    lui a0, 913408
 ; RV32IDZFHMIN-NEXT:    fmv.w.x fa5, a0
-; RV32IDZFHMIN-NEXT:    fle.s s0, fa5, fs0
+; RV32IDZFHMIN-NEXT:    flt.s s0, fs0, fa5
 ; RV32IDZFHMIN-NEXT:    fmv.s fa0, fs0
 ; RV32IDZFHMIN-NEXT:    call __fixsfdi@plt
 ; RV32IDZFHMIN-NEXT:    lui a4, 524288
 ; RV32IDZFHMIN-NEXT:    lui a2, 524288
-; RV32IDZFHMIN-NEXT:    beqz s0, .LBB10_2
+; RV32IDZFHMIN-NEXT:    bnez s0, .LBB10_2
 ; RV32IDZFHMIN-NEXT:  # %bb.1: # %start
 ; RV32IDZFHMIN-NEXT:    mv a2, a1
 ; RV32IDZFHMIN-NEXT:  .LBB10_2: # %start
 ; RV32IDZFHMIN-NEXT:    lui a1, %hi(.LCPI10_0)
 ; RV32IDZFHMIN-NEXT:    flw fa5, %lo(.LCPI10_0)(a1)
 ; RV32IDZFHMIN-NEXT:    flt.s a3, fa5, fs0
 ; RV32IDZFHMIN-NEXT:    beqz a3, .LBB10_4
 ; RV32IDZFHMIN-NEXT:  # %bb.3:
 ; RV32IDZFHMIN-NEXT:    addi a2, a4, -1
 ; RV32IDZFHMIN-NEXT:  .LBB10_4: # %start
 ; RV32IDZFHMIN-NEXT:    feq.s a1, fs0, fs0
 ; RV32IDZFHMIN-NEXT:    neg a4, a1
 ; RV32IDZFHMIN-NEXT:    and a1, a4, a2
 ; RV32IDZFHMIN-NEXT:    neg a2, a3
-; RV32IDZFHMIN-NEXT:    neg a3, s0
-; RV32IDZFHMIN-NEXT:    and a0, a3, a0
+; RV32IDZFHMIN-NEXT:    addi s0, s0, -1
+; RV32IDZFHMIN-NEXT:    and a0, s0, a0
 ; RV32IDZFHMIN-NEXT:    or a0, a2, a0
 ; RV32IDZFHMIN-NEXT:    and a0, a4, a0
 ; RV32IDZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IDZFHMIN-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IDZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32IDZFHMIN-NEXT:    ret
 ;
 ; CHECK32-IZHINXMIN-LABEL: fcvt_l_h_sat:
 ; CHECK32-IZHINXMIN:       # %bb.0: # %start
 ; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, -32
 ; CHECK32-IZHINXMIN-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; CHECK32-IZHINXMIN-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; CHECK32-IZHINXMIN-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; CHECK32-IZHINXMIN-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; CHECK32-IZHINXMIN-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; CHECK32-IZHINXMIN-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
 ; CHECK32-IZHINXMIN-NEXT:    lui a1, %hi(.LCPI10_0)
 ; CHECK32-IZHINXMIN-NEXT:    lw a1, %lo(.LCPI10_0)(a1)
 ; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h s0, a0
 ; CHECK32-IZHINXMIN-NEXT:    flt.s s1, a1, s0
 ; CHECK32-IZHINXMIN-NEXT:    neg s2, s1
 ; CHECK32-IZHINXMIN-NEXT:    lui a0, 913408
-; CHECK32-IZHINXMIN-NEXT:    fle.s s3, a0, s0
-; CHECK32-IZHINXMIN-NEXT:    neg s4, s3
+; CHECK32-IZHINXMIN-NEXT:    flt.s s3, s0, a0
+; CHECK32-IZHINXMIN-NEXT:    addi s4, s3, -1
 ; CHECK32-IZHINXMIN-NEXT:    mv a0, s0
 ; CHECK32-IZHINXMIN-NEXT:    call __fixsfdi@plt
 ; CHECK32-IZHINXMIN-NEXT:    and a0, s4, a0
 ; CHECK32-IZHINXMIN-NEXT:    or a0, s2, a0
 ; CHECK32-IZHINXMIN-NEXT:    feq.s a2, s0, s0
 ; CHECK32-IZHINXMIN-NEXT:    neg a2, a2
 ; CHECK32-IZHINXMIN-NEXT:    lui a4, 524288
 ; CHECK32-IZHINXMIN-NEXT:    lui a3, 524288
-; CHECK32-IZHINXMIN-NEXT:    beqz s3, .LBB10_2
+; CHECK32-IZHINXMIN-NEXT:    bnez s3, .LBB10_2
 ; CHECK32-IZHINXMIN-NEXT:  # %bb.1: # %start
 ; CHECK32-IZHINXMIN-NEXT:    mv a3, a1
 ; CHECK32-IZHINXMIN-NEXT:  .LBB10_2: # %start
 ; CHECK32-IZHINXMIN-NEXT:    and a0, a2, a0
 ; CHECK32-IZHINXMIN-NEXT:    beqz s1, .LBB10_4
 ; CHECK32-IZHINXMIN-NEXT:  # %bb.3:
 ; CHECK32-IZHINXMIN-NEXT:    addi a3, a4, -1
 ; CHECK32-IZHINXMIN-NEXT:  .LBB10_4: # %start

 ; CHECK32-IZDINXZHINXMIN-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
 ; CHECK32-IZDINXZHINXMIN-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
 ; CHECK32-IZDINXZHINXMIN-NEXT:    lui a1, %hi(.LCPI10_0)
 ; CHECK32-IZDINXZHINXMIN-NEXT:    lw a1, %lo(.LCPI10_0)(a1)
 ; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h s0, a0
 ; CHECK32-IZDINXZHINXMIN-NEXT:    flt.s s1, a1, s0
 ; CHECK32-IZDINXZHINXMIN-NEXT:    neg s2, s1
 ; CHECK32-IZDINXZHINXMIN-NEXT:    lui a0, 913408
-; CHECK32-IZDINXZHINXMIN-NEXT:    fle.s s3, a0, s0
-; CHECK32-IZDINXZHINXMIN-NEXT:    neg s4, s3
+; CHECK32-IZDINXZHINXMIN-NEXT:    flt.s s3, s0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi s4, s3, -1
 ; CHECK32-IZDINXZHINXMIN-NEXT:    mv a0, s0
 ; CHECK32-IZDINXZHINXMIN-NEXT:    call __fixsfdi@plt
 ; CHECK32-IZDINXZHINXMIN-NEXT:    and a0, s4, a0
 ; CHECK32-IZDINXZHINXMIN-NEXT:    or a0, s2, a0
 ; CHECK32-IZDINXZHINXMIN-NEXT:    feq.s a2, s0, s0
 ; CHECK32-IZDINXZHINXMIN-NEXT:    neg a2, a2
 ; CHECK32-IZDINXZHINXMIN-NEXT:    lui a4, 524288
 ; CHECK32-IZDINXZHINXMIN-NEXT:    lui a3, 524288
-; CHECK32-IZDINXZHINXMIN-NEXT:    beqz s3, .LBB10_2
+; CHECK32-IZDINXZHINXMIN-NEXT:    bnez s3, .LBB10_2
 ; CHECK32-IZDINXZHINXMIN-NEXT:  # %bb.1: # %start
 ; CHECK32-IZDINXZHINXMIN-NEXT:    mv a3, a1
 ; CHECK32-IZDINXZHINXMIN-NEXT:  .LBB10_2: # %start
 ; CHECK32-IZDINXZHINXMIN-NEXT:    and a0, a2, a0
 ; CHECK32-IZDINXZHINXMIN-NEXT:    beqz s1, .LBB10_4
 ; CHECK32-IZDINXZHINXMIN-NEXT:  # %bb.3:
 ; CHECK32-IZDINXZHINXMIN-NEXT:    addi a3, a4, -1
 ; CHECK32-IZDINXZHINXMIN-NEXT:  .LBB10_4: # %start

 ; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI12_0)
 ; RV32IZFH-NEXT:    flw fa5, %lo(.LCPI12_0)(a0)
 ; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IZFH-NEXT:    flt.s a0, fa5, fa0
 ; RV32IZFH-NEXT:    neg s0, a0
 ; RV32IZFH-NEXT:    fmv.w.x fa5, zero
-; RV32IZFH-NEXT:    fle.s a0, fa5, fa0
-; RV32IZFH-NEXT:    neg s1, a0
+; RV32IZFH-NEXT:    flt.s a0, fa0, fa5
+; RV32IZFH-NEXT:    addi s1, a0, -1
 ; RV32IZFH-NEXT:    call __fixunssfdi@plt
 ; RV32IZFH-NEXT:    and a0, s1, a0
 ; RV32IZFH-NEXT:    or a0, s0, a0
 ; RV32IZFH-NEXT:    and a1, s1, a1
 ; RV32IZFH-NEXT:    or a1, s0, a1
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload

 ; RV32IDZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    lui a0, %hi(.LCPI12_0)
 ; RV32IDZFH-NEXT:    flw fa5, %lo(.LCPI12_0)(a0)
 ; RV32IDZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IDZFH-NEXT:    flt.s a0, fa5, fa0
 ; RV32IDZFH-NEXT:    neg s0, a0
 ; RV32IDZFH-NEXT:    fmv.w.x fa5, zero
-; RV32IDZFH-NEXT:    fle.s a0, fa5, fa0
-; RV32IDZFH-NEXT:    neg s1, a0
+; RV32IDZFH-NEXT:    flt.s a0, fa0, fa5
+; RV32IDZFH-NEXT:    addi s1, a0, -1
 ; RV32IDZFH-NEXT:    call __fixunssfdi@plt
 ; RV32IDZFH-NEXT:    and a0, s1, a0
 ; RV32IDZFH-NEXT:    or a0, s0, a0
 ; RV32IDZFH-NEXT:    and a1, s1, a1
 ; RV32IDZFH-NEXT:    or a1, s0, a1
 ; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload

 ; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI12_0)
 ; RV32IZHINX-NEXT:    lw a1, %lo(.LCPI12_0)(a1)
 ; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
 ; RV32IZHINX-NEXT:    flt.s a1, a1, a0
 ; RV32IZHINX-NEXT:    neg s0, a1
-; RV32IZHINX-NEXT:    fle.s a1, zero, a0
-; RV32IZHINX-NEXT:    neg s1, a1
+; RV32IZHINX-NEXT:    flt.s a1, a0, zero
+; RV32IZHINX-NEXT:    addi s1, a1, -1
 ; RV32IZHINX-NEXT:    call __fixunssfdi@plt
 ; RV32IZHINX-NEXT:    and a0, s1, a0
 ; RV32IZHINX-NEXT:    or a0, s0, a0
 ; RV32IZHINX-NEXT:    and a1, s1, a1
 ; RV32IZHINX-NEXT:    or a1, s0, a1
 ; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload

 ; RV32IZDINXZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZDINXZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZDINXZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZDINXZHINX-NEXT:    lui a1, %hi(.LCPI12_0)
 ; RV32IZDINXZHINX-NEXT:    lw a1, %lo(.LCPI12_0)(a1)
 ; RV32IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
 ; RV32IZDINXZHINX-NEXT:    flt.s a1, a1, a0
 ; RV32IZDINXZHINX-NEXT:    neg s0, a1
-; RV32IZDINXZHINX-NEXT:    fle.s a1, zero, a0
-; RV32IZDINXZHINX-NEXT:    neg s1, a1
+; RV32IZDINXZHINX-NEXT:    flt.s a1, a0, zero
+; RV32IZDINXZHINX-NEXT:    addi s1, a1, -1
 ; RV32IZDINXZHINX-NEXT:    call __fixunssfdi@plt
 ; RV32IZDINXZHINX-NEXT:    and a0, s1, a0
 ; RV32IZDINXZHINX-NEXT:    or a0, s0, a0
 ; RV32IZDINXZHINX-NEXT:    and a1, s1, a1
 ; RV32IZDINXZHINX-NEXT:    or a1, s0, a1
 ; RV32IZDINXZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZDINXZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZDINXZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload

 ; CHECK32-IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; CHECK32-IZFHMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; CHECK32-IZFHMIN-NEXT:    lui a0, %hi(.LCPI12_0)
 ; CHECK32-IZFHMIN-NEXT:    flw fa5, %lo(.LCPI12_0)(a0)
 ; CHECK32-IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; CHECK32-IZFHMIN-NEXT:    flt.s a0, fa5, fa0
 ; CHECK32-IZFHMIN-NEXT:    neg s0, a0
 ; CHECK32-IZFHMIN-NEXT:    fmv.w.x fa5, zero
-; CHECK32-IZFHMIN-NEXT:    fle.s a0, fa5, fa0
-; CHECK32-IZFHMIN-NEXT:    neg s1, a0
+; CHECK32-IZFHMIN-NEXT:    flt.s a0, fa0, fa5
+; CHECK32-IZFHMIN-NEXT:    addi s1, a0, -1
 ; CHECK32-IZFHMIN-NEXT:    call __fixunssfdi@plt
 ; CHECK32-IZFHMIN-NEXT:    and a0, s1, a0
 ; CHECK32-IZFHMIN-NEXT:    or a0, s0, a0
 ; CHECK32-IZFHMIN-NEXT:    and a1, s1, a1
 ; CHECK32-IZFHMIN-NEXT:    or a1, s0, a1
 ; CHECK32-IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; CHECK32-IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; CHECK32-IZFHMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload

 ; CHECK32-IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; CHECK32-IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; CHECK32-IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; CHECK32-IZHINXMIN-NEXT:    lui a1, %hi(.LCPI12_0)
 ; CHECK32-IZHINXMIN-NEXT:    lw a1, %lo(.LCPI12_0)(a1)
 ; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
 ; CHECK32-IZHINXMIN-NEXT:    flt.s a1, a1, a0
 ; CHECK32-IZHINXMIN-NEXT:    neg s0, a1
-; CHECK32-IZHINXMIN-NEXT:    fle.s a1, zero, a0
-; CHECK32-IZHINXMIN-NEXT:    neg s1, a1
+; CHECK32-IZHINXMIN-NEXT:    flt.s a1, a0, zero
+; CHECK32-IZHINXMIN-NEXT:    addi s1, a1, -1
 ; CHECK32-IZHINXMIN-NEXT:    call __fixunssfdi@plt
 ; CHECK32-IZHINXMIN-NEXT:    and a0, s1, a0
 ; CHECK32-IZHINXMIN-NEXT:    or a0, s0, a0
 ; CHECK32-IZHINXMIN-NEXT:    and a1, s1, a1
 ; CHECK32-IZHINXMIN-NEXT:    or a1, s0, a1
 ; CHECK32-IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; CHECK32-IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; CHECK32-IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload

 ; CHECK32-IZDINXZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; CHECK32-IZDINXZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; CHECK32-IZDINXZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; CHECK32-IZDINXZHINXMIN-NEXT:    lui a1, %hi(.LCPI12_0)
 ; CHECK32-IZDINXZHINXMIN-NEXT:    lw a1, %lo(.LCPI12_0)(a1)
 ; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
 ; CHECK32-IZDINXZHINXMIN-NEXT:    flt.s a1, a1, a0
 ; CHECK32-IZDINXZHINXMIN-NEXT:    neg s0, a1
-; CHECK32-IZDINXZHINXMIN-NEXT:    fle.s a1, zero, a0
-; CHECK32-IZDINXZHINXMIN-NEXT:    neg s1, a1
+; CHECK32-IZDINXZHINXMIN-NEXT:    flt.s a1, a0, zero
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi s1, a1, -1
 ; CHECK32-IZDINXZHINXMIN-NEXT:    call __fixunssfdi@plt
 ; CHECK32-IZDINXZHINXMIN-NEXT:    and a0, s1, a0
 ; CHECK32-IZDINXZHINXMIN-NEXT:    or a0, s0, a0
 ; CHECK32-IZDINXZHINXMIN-NEXT:    and a1, s1, a1
 ; CHECK32-IZDINXZHINXMIN-NEXT:    or a1, s0, a1
 ; CHECK32-IZDINXZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; CHECK32-IZDINXZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; CHECK32-IZDINXZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload

llvm/test/CodeGen/RISCV/half-fcmp.ll

; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp ueq half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ugt(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_ugt:
 ; CHECKIZFH:       # %bb.0:
-; CHECKIZFH-NEXT:    fle.h a0, fa0, fa1
-; CHECKIZFH-NEXT:    xori a0, a0, 1
+; CHECKIZFH-NEXT:    flt.h a0, fa1, fa0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; CHECKIZHINX-LABEL: fcmp_ugt:
 ; CHECKIZHINX:       # %bb.0:
-; CHECKIZHINX-NEXT:    fle.h a0, a0, a1
-; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    flt.h a0, a1, a0
 ; CHECKIZHINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    fmv.h.x fa5, a1
-; RV32I-NEXT:    fmv.h.x fa4, a0
-; RV32I-NEXT:    fle.h a0, fa4, fa5
-; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    fmv.h.x fa5, a0
+; RV32I-NEXT:    fmv.h.x fa4, a1
+; RV32I-NEXT:    flt.h a0, fa4, fa5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ugt:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    fmv.h.x fa5, a1
-; RV64I-NEXT:    fmv.h.x fa4, a0
-; RV64I-NEXT:    fle.h a0, fa4, fa5
-; RV64I-NEXT:    xori a0, a0, 1
+; RV64I-NEXT:    fmv.h.x fa5, a0
+; RV64I-NEXT:    fmv.h.x fa4, a1
+; RV64I-NEXT:    flt.h a0, fa4, fa5
 ; RV64I-NEXT:    ret
 ;
 ; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ugt:
 ; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
-; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h fa4, fa0
-; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fle.s a0, fa4, fa5
-; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h fa5, fa0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h fa4, fa1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    flt.s a0, fa4, fa5
 ; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
 ;
 ; CHECKIZFHMIN-LABEL: fcmp_ugt:
 ; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a0
-; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a1
+; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a1
+; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
-; CHECKIZFHMIN-NEXT:    fle.s a0, fa5, fa4
-; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    flt.s a0, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    ret
 ;
 ; CHECKIZHINXMIN-LABEL: fcmp_ugt:
 ; CHECKIZHINXMIN:       # %bb.0:
-; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
 ; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
-; CHECKIZHINXMIN-NEXT:    fle.s a0, a0, a1
-; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    flt.s a0, a1, a0
 ; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp ugt half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uge(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_uge:
 ; CHECKIZFH:       # %bb.0:
-; CHECKIZFH-NEXT:    flt.h a0, fa0, fa1
-; CHECKIZFH-NEXT:    xori a0, a0, 1
+; CHECKIZFH-NEXT:    fle.h a0, fa1, fa0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; CHECKIZHINX-LABEL: fcmp_uge:
 ; CHECKIZHINX:       # %bb.0:
-; CHECKIZHINX-NEXT:    flt.h a0, a0, a1
-; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    fle.h a0, a1, a0
 ; CHECKIZHINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    fmv.h.x fa5, a1
-; RV32I-NEXT:    fmv.h.x fa4, a0
-; RV32I-NEXT:    flt.h a0, fa4, fa5
-; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    fmv.h.x fa5, a0
+; RV32I-NEXT:    fmv.h.x fa4, a1
+; RV32I-NEXT:    fle.h a0, fa4, fa5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_uge:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    fmv.h.x fa5, a1
-; RV64I-NEXT:    fmv.h.x fa4, a0
-; RV64I-NEXT:    flt.h a0, fa4, fa5
-; RV64I-NEXT:    xori a0, a0, 1
+; RV64I-NEXT:    fmv.h.x fa5, a0
+; RV64I-NEXT:    fmv.h.x fa4, a1
+; RV64I-NEXT:    fle.h a0, fa4, fa5
 ; RV64I-NEXT:    ret
 ;
 ; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_uge:
 ; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
-; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h fa4, fa0
-; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    flt.s a0, fa4, fa5
-; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h fa5, fa0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h fa4, fa1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fle.s a0, fa4, fa5
 ; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
 ;
 ; CHECKIZFHMIN-LABEL: fcmp_uge:
 ; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a0
-; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a1
+; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a1
+; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
-; CHECKIZFHMIN-NEXT:    flt.s a0, fa5, fa4
-; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    fle.s a0, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    ret
 ;
 ; CHECKIZHINXMIN-LABEL: fcmp_uge:
 ; CHECKIZHINXMIN:       # %bb.0:
-; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
 ; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
-; CHECKIZHINXMIN-NEXT:    flt.s a0, a0, a1
-; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fle.s a0, a1, a0
 ; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp uge half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ult(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_ult:
 ; CHECKIZFH:       # %bb.0:
-; CHECKIZFH-NEXT:    fle.h a0, fa1, fa0
-; CHECKIZFH-NEXT:    xori a0, a0, 1
+; CHECKIZFH-NEXT:    flt.h a0, fa0, fa1
 ; CHECKIZFH-NEXT:    ret
 ;
 ; CHECKIZHINX-LABEL: fcmp_ult:
 ; CHECKIZHINX:       # %bb.0:
-; CHECKIZHINX-NEXT:    fle.h a0, a1, a0
-; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    flt.h a0, a0, a1
 ; CHECKIZHINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ult:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    fmv.h.x fa5, a0
-; RV32I-NEXT:    fmv.h.x fa4, a1
-; RV32I-NEXT:    fle.h a0, fa4, fa5
-; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    fmv.h.x fa5, a1
+; RV32I-NEXT:    fmv.h.x fa4, a0
+; RV32I-NEXT:    flt.h a0, fa4, fa5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ult:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    fmv.h.x fa5, a0
-; RV64I-NEXT:    fmv.h.x fa4, a1
-; RV64I-NEXT:    fle.h a0, fa4, fa5
-; RV64I-NEXT:    xori a0, a0, 1
+; RV64I-NEXT:    fmv.h.x fa5, a1
+; RV64I-NEXT:    fmv.h.x fa4, a0
+; RV64I-NEXT:    flt.h a0, fa4, fa5
 ; RV64I-NEXT:    ret
 ;
 ; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ult:
 ; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
-; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fle.s a0, fa4, fa5
-; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h fa5, fa1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h fa4, fa0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    flt.s a0, fa4, fa5
 ; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
 ;
 ; CHECKIZFHMIN-LABEL: fcmp_ult:
 ; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a1
-; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a0
+; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a0
+; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
-; CHECKIZFHMIN-NEXT:    fle.s a0, fa5, fa4
-; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    flt.s a0, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    ret
 ;
 ; CHECKIZHINXMIN-LABEL: fcmp_ult:
 ; CHECKIZHINXMIN:       # %bb.0:
-; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
 ; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT:    fle.s a0, a1, a0
-; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a0, a0, a1
 ; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp ult half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ule(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_ule:
 ; CHECKIZFH:       # %bb.0:
-; CHECKIZFH-NEXT:    flt.h a0, fa1, fa0
-; CHECKIZFH-NEXT:    xori a0, a0, 1
+; CHECKIZFH-NEXT:    fle.h a0, fa0, fa1
 ; CHECKIZFH-NEXT:    ret
 ;
 ; CHECKIZHINX-LABEL: fcmp_ule:
 ; CHECKIZHINX:       # %bb.0:
-; CHECKIZHINX-NEXT:    flt.h a0, a1, a0
-; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    fle.h a0, a0, a1
 ; CHECKIZHINX-NEXT:    ret
 ;
 ; RV32I-LABEL: fcmp_ule:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    fmv.h.x fa5, a0
-; RV32I-NEXT:    fmv.h.x fa4, a1
-; RV32I-NEXT:    flt.h a0, fa4, fa5
-; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    fmv.h.x fa5, a1
+; RV32I-NEXT:    fmv.h.x fa4, a0
+; RV32I-NEXT:    fle.h a0, fa4, fa5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ule:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    fmv.h.x fa5, a0
-; RV64I-NEXT:    fmv.h.x fa4, a1
-; RV64I-NEXT:    flt.h a0, fa4, fa5
-; RV64I-NEXT:    xori a0, a0, 1
+; RV64I-NEXT:    fmv.h.x fa5, a1
+; RV64I-NEXT:    fmv.h.x fa4, a0
+; RV64I-NEXT:    fle.h a0, fa4, fa5
 ; RV64I-NEXT:    ret
 ;
 ; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_ule:
 ; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
-; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    flt.s a0, fa4, fa5
-; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h fa5, fa1
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fcvt.s.h fa4, fa0
+; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    fle.s a0, fa4, fa5
 ; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
 ;
 ; CHECKIZFHMIN-LABEL: fcmp_ule:
 ; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a1
-; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a0
+; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a0
+; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
-; CHECKIZFHMIN-NEXT:    flt.s a0, fa5, fa4
-; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    fle.s a0, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    ret
 ;
 ; CHECKIZHINXMIN-LABEL: fcmp_ule:
 ; CHECKIZHINXMIN:       # %bb.0:
-; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
 ; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT:    flt.s a0, a1, a0
-; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fle.s a0, a0, a1
 ; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp ule half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_une(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_une:

llvm/test/CodeGen/RISCV/half-round-conv-sat.ll

 ; RV32IZFH-NEXT:  # %bb.1:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rdn
 ; RV32IZFH-NEXT:    fcvt.h.w fa5, a0, rdn
 ; RV32IZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; RV32IZFH-NEXT:  .LBB1_2:
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, fa0
 ; RV32IZFH-NEXT:    lui a0, 913408
 ; RV32IZFH-NEXT:    fmv.w.x fa5, a0
-; RV32IZFH-NEXT:    fle.s s0, fa5, fs0
+; RV32IZFH-NEXT:    flt.s s0, fs0, fa5
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixsfdi@plt
 ; RV32IZFH-NEXT:    lui a4, 524288
 ; RV32IZFH-NEXT:    lui a2, 524288
-; RV32IZFH-NEXT:    beqz s0, .LBB1_4
+; RV32IZFH-NEXT:    bnez s0, .LBB1_4
 ; RV32IZFH-NEXT:  # %bb.3:
 ; RV32IZFH-NEXT:    mv a2, a1
 ; RV32IZFH-NEXT:  .LBB1_4:
 ; RV32IZFH-NEXT:    lui a1, %hi(.LCPI1_1)
 ; RV32IZFH-NEXT:    flw fa5, %lo(.LCPI1_1)(a1)
 ; RV32IZFH-NEXT:    flt.s a3, fa5, fs0
 ; RV32IZFH-NEXT:    beqz a3, .LBB1_6
 ; RV32IZFH-NEXT:  # %bb.5:
 ; RV32IZFH-NEXT:    addi a2, a4, -1
 ; RV32IZFH-NEXT:  .LBB1_6:
 ; RV32IZFH-NEXT:    feq.s a1, fs0, fs0
 ; RV32IZFH-NEXT:    neg a4, a1
 ; RV32IZFH-NEXT:    and a1, a4, a2
-; RV32IZFH-NEXT:    neg a2, s0
-; RV32IZFH-NEXT:    and a0, a2, a0
+; RV32IZFH-NEXT:    addi s0, s0, -1
+; RV32IZFH-NEXT:    and a0, s0, a0
 ; RV32IZFH-NEXT:    neg a2, a3
 ; RV32IZFH-NEXT:    or a0, a2, a0
 ; RV32IZFH-NEXT:    and a0, a4, a0
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_floor_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IZHINX-LABEL: test_floor_si64:
 ; RV32IZHINX:       # %bb.0:
 ; RV32IZHINX-NEXT:    addi sp, sp, -16
 ; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI1_0)
 ; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI1_0)(a1)
 ; RV32IZHINX-NEXT:    fabs.h a2, a0
 ; RV32IZHINX-NEXT:    flt.h a1, a2, a1
 ; RV32IZHINX-NEXT:    beqz a1, .LBB1_2
 ; RV32IZHINX-NEXT:  # %bb.1:
 ; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
 ; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
 ; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
 ; RV32IZHINX-NEXT:  .LBB1_2:
 ; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINX-NEXT:    lui a0, 913408
-; RV32IZHINX-NEXT:    fle.s s1, a0, s0
-; RV32IZHINX-NEXT:    neg s2, s1
 ; RV32IZHINX-NEXT:    mv a0, s0
 ; RV32IZHINX-NEXT:    call __fixsfdi@plt
-; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI1_1)
-; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI1_1)(a2)
-; RV32IZHINX-NEXT:    and a0, s2, a0
-; RV32IZHINX-NEXT:    flt.s a4, a2, s0
+; RV32IZHINX-NEXT:    lui a2, 913408
+; RV32IZHINX-NEXT:    lui a3, %hi(.LCPI1_1)
+; RV32IZHINX-NEXT:    lw a3, %lo(.LCPI1_1)(a3)
+; RV32IZHINX-NEXT:    flt.s a6, s0, a2
+; RV32IZHINX-NEXT:    addi a2, a6, -1
+; RV32IZHINX-NEXT:    and a0, a2, a0
+; RV32IZHINX-NEXT:    flt.s a4, a3, s0
 ; RV32IZHINX-NEXT:    neg a2, a4
 ; RV32IZHINX-NEXT:    or a0, a2, a0
 ; RV32IZHINX-NEXT:    feq.s a2, s0, s0
 ; RV32IZHINX-NEXT:    neg a2, a2
 ; RV32IZHINX-NEXT:    lui a5, 524288
 ; RV32IZHINX-NEXT:    lui a3, 524288
-; RV32IZHINX-NEXT:    beqz s1, .LBB1_4
+; RV32IZHINX-NEXT:    bnez a6, .LBB1_4
 ; RV32IZHINX-NEXT:  # %bb.3:
 ; RV32IZHINX-NEXT:    mv a3, a1
 ; RV32IZHINX-NEXT:  .LBB1_4:
 ; RV32IZHINX-NEXT:    and a0, a2, a0
 ; RV32IZHINX-NEXT:    beqz a4, .LBB1_6
 ; RV32IZHINX-NEXT:  # %bb.5:
 ; RV32IZHINX-NEXT:    addi a3, a5, -1
 ; RV32IZHINX-NEXT:  .LBB1_6:
 ; RV32IZHINX-NEXT:    and a1, a2, a3
 ; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    addi sp, sp, 16
 ; RV32IZHINX-NEXT:    ret
 ;
 ; RV64IZHINX-LABEL: test_floor_si64:
 ; RV64IZHINX:       # %bb.0:
 ; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI1_0)
 ; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI1_0)(a1)
 ; RV64IZHINX-NEXT:    fabs.h a2, a0

 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, fa5
 ; RV32IZFHMIN-NEXT:    lui a0, 913408
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa5, a0
-; RV32IZFHMIN-NEXT:    fle.s s0, fa5, fs0
+; RV32IZFHMIN-NEXT:    flt.s s0, fs0, fa5
 ; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
 ; RV32IZFHMIN-NEXT:    call __fixsfdi@plt
 ; RV32IZFHMIN-NEXT:    lui a4, 524288
 ; RV32IZFHMIN-NEXT:    lui a2, 524288
-; RV32IZFHMIN-NEXT:    beqz s0, .LBB1_4
+; RV32IZFHMIN-NEXT:    bnez s0, .LBB1_4
 ; RV32IZFHMIN-NEXT:  # %bb.3:
 ; RV32IZFHMIN-NEXT:    mv a2, a1
 ; RV32IZFHMIN-NEXT:  .LBB1_4:
 ; RV32IZFHMIN-NEXT:    lui a1, %hi(.LCPI1_0)
 ; RV32IZFHMIN-NEXT:    flw fa5, %lo(.LCPI1_0)(a1)
 ; RV32IZFHMIN-NEXT:    flt.s a3, fa5, fs0
 ; RV32IZFHMIN-NEXT:    beqz a3, .LBB1_6
 ; RV32IZFHMIN-NEXT:  # %bb.5:
 ; RV32IZFHMIN-NEXT:    addi a2, a4, -1
 ; RV32IZFHMIN-NEXT:  .LBB1_6:
 ; RV32IZFHMIN-NEXT:    feq.s a1, fs0, fs0
 ; RV32IZFHMIN-NEXT:    neg a4, a1
 ; RV32IZFHMIN-NEXT:    and a1, a4, a2
-; RV32IZFHMIN-NEXT:    neg a2, s0
-; RV32IZFHMIN-NEXT:    and a0, a2, a0
+; RV32IZFHMIN-NEXT:    addi s0, s0, -1
+; RV32IZFHMIN-NEXT:    and a0, s0, a0
 ; RV32IZFHMIN-NEXT:    neg a2, a3
 ; RV32IZFHMIN-NEXT:    or a0, a2, a0
 ; RV32IZFHMIN-NEXT:    and a0, a4, a0
 ; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32IZFHMIN-NEXT:    ret

 ; RV32IZHINXMIN-NEXT:  # %bb.1:
 ; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
 ; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
 ; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
 ; RV32IZHINXMIN-NEXT:  .LBB1_2:
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
 ; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
 ; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINXMIN-NEXT:    lui a0, 913408
-; RV32IZHINXMIN-NEXT:    fle.s s1, a0, s0
-; RV32IZHINXMIN-NEXT:    neg s2, s1
 ; RV32IZHINXMIN-NEXT:    mv a0, s0
 ; RV32IZHINXMIN-NEXT:    call __fixsfdi@plt
-; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI1_0)
-; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI1_0)(a2)
-; RV32IZHINXMIN-NEXT:    and a0, s2, a0
-; RV32IZHINXMIN-NEXT:    flt.s a4, a2, s0
+; RV32IZHINXMIN-NEXT:    lui a2, 913408
+; RV32IZHINXMIN-NEXT:    lui a3, %hi(.LCPI1_0)
+; RV32IZHINXMIN-NEXT:    lw a3, %lo(.LCPI1_0)(a3)
+; RV32IZHINXMIN-NEXT:    flt.s a6, s0, a2
+; RV32IZHINXMIN-NEXT:    addi a2, a6, -1
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a4, a3, s0
 ; RV32IZHINXMIN-NEXT:    neg a2, a4
 ; RV32IZHINXMIN-NEXT:    or a0, a2, a0
 ; RV32IZHINXMIN-NEXT:    feq.s a2, s0, s0
 ; RV32IZHINXMIN-NEXT:    neg a2, a2
 ; RV32IZHINXMIN-NEXT:    lui a5, 524288
 ; RV32IZHINXMIN-NEXT:    lui a3, 524288
-; RV32IZHINXMIN-NEXT:    beqz s1, .LBB1_4
-; RV32IZHINXMIN-NEXT:  # %bb.3:
-; RV32IZHINXMIN-NEXT:    mv a3, a1
-; RV32IZHINXMIN-NEXT:  .LBB1_4:
-; RV32IZHINXMIN-NEXT:    and a0, a2, a0
 ; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
-; RV32IZHINXMIN-NEXT:    beqz a4, .LBB1_6
-; RV32IZHINXMIN-NEXT:  # %bb.5:
-; RV32IZHINXMIN-NEXT:    addi a3, a5, -1
+; RV32IZHINXMIN-NEXT:    beqz a6, .LBB1_5
+; RV32IZHINXMIN-NEXT:  # %bb.3:
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    bnez a4, .LBB1_6
+; RV32IZHINXMIN-NEXT:  .LBB1_4:
+; RV32IZHINXMIN-NEXT:    and a1, a2, a3
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB1_5:
+; RV32IZHINXMIN-NEXT:    mv a3, a1
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    beqz a4, .LBB1_4
 ; RV32IZHINXMIN-NEXT:  .LBB1_6:
+; RV32IZHINXMIN-NEXT:    addi a3, a5, -1
 ; RV32IZHINXMIN-NEXT:    and a1, a2, a3
 ; RV32IZHINXMIN-NEXT:    ret
 ;
 ; RV64IZHINXMIN-LABEL: test_floor_si64:
 ; RV64IZHINXMIN:       # %bb.0:
 ; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
 ; RV64IZHINXMIN-NEXT:    lui a1, 307200
 ; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
; RV64IZHINXMIN-NEXT:    ret
   ret i32 %b
 }
 
 define i64 @test_floor_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_floor_ui64:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI3_0)
 ; RV32IZFH-NEXT:    flh fa5, %lo(.LCPI3_0)(a0)
 ; RV32IZFH-NEXT:    fabs.h fa4, fa0
 ; RV32IZFH-NEXT:    flt.h a0, fa4, fa5
 ; RV32IZFH-NEXT:    beqz a0, .LBB3_2
 ; RV32IZFH-NEXT:  # %bb.1:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rdn
 ; RV32IZFH-NEXT:    fcvt.h.w fa5, a0, rdn
 ; RV32IZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; RV32IZFH-NEXT:  .LBB3_2:
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, fa0
-; RV32IZFH-NEXT:    fmv.w.x fa5, zero
-; RV32IZFH-NEXT:    fle.s a0, fa5, fs0
-; RV32IZFH-NEXT:    neg s0, a0
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixunssfdi@plt
+; RV32IZFH-NEXT:    fmv.w.x fa5, zero
 ; RV32IZFH-NEXT:    lui a2, %hi(.LCPI3_1)
-; RV32IZFH-NEXT:    flw fa5, %lo(.LCPI3_1)(a2)
-; RV32IZFH-NEXT:    and a0, s0, a0
-; RV32IZFH-NEXT:    flt.s a2, fa5, fs0
-; RV32IZFH-NEXT:    neg a2, a2
-; RV32IZFH-NEXT:    or a0, a2, a0
-; RV32IZFH-NEXT:    and a1, s0, a1
-; RV32IZFH-NEXT:    or a1, a2, a1
+; RV32IZFH-NEXT:    flw fa4, %lo(.LCPI3_1)(a2)
+; RV32IZFH-NEXT:    flt.s a2, fs0, fa5
+; RV32IZFH-NEXT:    addi a2, a2, -1
+; RV32IZFH-NEXT:    and a0, a2, a0
+; RV32IZFH-NEXT:    flt.s a3, fa4, fs0
+; RV32IZFH-NEXT:    neg a3, a3
+; RV32IZFH-NEXT:    or a0, a3, a0
+; RV32IZFH-NEXT:    and a1, a2, a1
+; RV32IZFH-NEXT:    or a1, a3, a1
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_floor_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IZHINX-LABEL: test_floor_ui64:
 ; RV32IZHINX:       # %bb.0:
 ; RV32IZHINX-NEXT:    addi sp, sp, -16
 ; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI3_0)
 ; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI3_0)(a1)
 ; RV32IZHINX-NEXT:    fabs.h a2, a0
 ; RV32IZHINX-NEXT:    flt.h a1, a2, a1
 ; RV32IZHINX-NEXT:    beqz a1, .LBB3_2
 ; RV32IZHINX-NEXT:  # %bb.1:
 ; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
 ; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
 ; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
 ; RV32IZHINX-NEXT:  .LBB3_2:
 ; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINX-NEXT:    fle.s a0, zero, s0
-; RV32IZHINX-NEXT:    neg s1, a0
 ; RV32IZHINX-NEXT:    mv a0, s0
 ; RV32IZHINX-NEXT:    call __fixunssfdi@plt
 ; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI3_1)
 ; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI3_1)(a2)
-; RV32IZHINX-NEXT:    and a0, s1, a0
+; RV32IZHINX-NEXT:    flt.s a3, s0, zero
+; RV32IZHINX-NEXT:    addi a3, a3, -1
+; RV32IZHINX-NEXT:    and a0, a3, a0
 ; RV32IZHINX-NEXT:    flt.s a2, a2, s0
 ; RV32IZHINX-NEXT:    neg a2, a2
 ; RV32IZHINX-NEXT:    or a0, a2, a0
-; RV32IZHINX-NEXT:    and a1, s1, a1
+; RV32IZHINX-NEXT:    and a1, a3, a1
 ; RV32IZHINX-NEXT:    or a1, a2, a1
 ; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    addi sp, sp, 16
 ; RV32IZHINX-NEXT:    ret
 ;
 ; RV64IZHINX-LABEL: test_floor_ui64:
 ; RV64IZHINX:       # %bb.0:
 ; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI3_0)
 ; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI3_0)(a1)
 ; RV64IZHINX-NEXT:    fabs.h a2, a0

 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB3_2
 ; RV32IZFHMIN-NEXT:  # %bb.1:
 ; RV32IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rdn
 ; RV32IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rdn
 ; RV32IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV32IZFHMIN-NEXT:  .LBB3_2:
 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, fa5
-; RV32IZFHMIN-NEXT:    fmv.w.x fa5, zero
-; RV32IZFHMIN-NEXT:    fle.s a0, fa5, fs0
-; RV32IZFHMIN-NEXT:    neg s0, a0
 ; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
 ; RV32IZFHMIN-NEXT:    call __fixunssfdi@plt
+; RV32IZFHMIN-NEXT:    fmv.w.x fa5, zero
 ; RV32IZFHMIN-NEXT:    lui a2, %hi(.LCPI3_0)
-; RV32IZFHMIN-NEXT:    flw fa5, %lo(.LCPI3_0)(a2)
-; RV32IZFHMIN-NEXT:    and a0, s0, a0
-; RV32IZFHMIN-NEXT:    flt.s a2, fa5, fs0
-; RV32IZFHMIN-NEXT:    neg a2, a2
-; RV32IZFHMIN-NEXT:    or a0, a2, a0
-; RV32IZFHMIN-NEXT:    and a1, s0, a1
-; RV32IZFHMIN-NEXT:    or a1, a2, a1
+; RV32IZFHMIN-NEXT:    flw fa4, %lo(.LCPI3_0)(a2)
+; RV32IZFHMIN-NEXT:    flt.s a2, fs0, fa5
+; RV32IZFHMIN-NEXT:    addi a2, a2, -1
+; RV32IZFHMIN-NEXT:    and a0, a2, a0
+; RV32IZFHMIN-NEXT:    flt.s a3, fa4, fs0
+; RV32IZFHMIN-NEXT:    neg a3, a3
+; RV32IZFHMIN-NEXT:    or a0, a3, a0
+; RV32IZFHMIN-NEXT:    and a1, a2, a1
+; RV32IZFHMIN-NEXT:    or a1, a3, a1
 ; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32IZFHMIN-NEXT:    ret
 ;
 ; RV64IZFHMIN-LABEL: test_floor_ui64:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    lui a0, 307200
 ; RV64IZFHMIN-NEXT:    fmv.w.x fa4, a0

 ; RV32IZHINXMIN-NEXT:  # %bb.1:
 ; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
 ; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
 ; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
 ; RV32IZHINXMIN-NEXT:  .LBB3_2:
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
 ; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
 ; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINXMIN-NEXT:    fle.s a0, zero, s0
-; RV32IZHINXMIN-NEXT:    neg s1, a0
 ; RV32IZHINXMIN-NEXT:    mv a0, s0
 ; RV32IZHINXMIN-NEXT:    call __fixunssfdi@plt
 ; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI3_0)
 ; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI3_0)(a2)
-; RV32IZHINXMIN-NEXT:    and a0, s1, a0
+; RV32IZHINXMIN-NEXT:    flt.s a3, s0, zero
+; RV32IZHINXMIN-NEXT:    addi a3, a3, -1
+; RV32IZHINXMIN-NEXT:    and a0, a3, a0
 ; RV32IZHINXMIN-NEXT:    flt.s a2, a2, s0
 ; RV32IZHINXMIN-NEXT:    neg a2, a2
 ; RV32IZHINXMIN-NEXT:    or a0, a2, a0
-; RV32IZHINXMIN-NEXT:    and a1, s1, a1
+; RV32IZHINXMIN-NEXT:    and a1, a3, a1
 ; RV32IZHINXMIN-NEXT:    or a1, a2, a1
 ; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
 ; RV32IZHINXMIN-NEXT:    ret
 ;
 ; RV64IZHINXMIN-LABEL: test_floor_ui64:
 ; RV64IZHINXMIN:       # %bb.0:
 ; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
 ; RV64IZHINXMIN-NEXT:    lui a1, 307200
 ; RV64IZHINXMIN-NEXT:    fabs.s a2, a0

 ; RV32IZFH-NEXT:  # %bb.1:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rup
 ; RV32IZFH-NEXT:    fcvt.h.w fa5, a0, rup
 ; RV32IZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; RV32IZFH-NEXT:  .LBB5_2:
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, fa0
 ; RV32IZFH-NEXT:    lui a0, 913408
 ; RV32IZFH-NEXT:    fmv.w.x fa5, a0
-; RV32IZFH-NEXT:    fle.s s0, fa5, fs0
+; RV32IZFH-NEXT:    flt.s s0, fs0, fa5
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixsfdi@plt
 ; RV32IZFH-NEXT:    lui a4, 524288
 ; RV32IZFH-NEXT:    lui a2, 524288
-; RV32IZFH-NEXT:    beqz s0, .LBB5_4
+; RV32IZFH-NEXT:    bnez s0, .LBB5_4
 ; RV32IZFH-NEXT:  # %bb.3:
 ; RV32IZFH-NEXT:    mv a2, a1
 ; RV32IZFH-NEXT:  .LBB5_4:
 ; RV32IZFH-NEXT:    lui a1, %hi(.LCPI5_1)
 ; RV32IZFH-NEXT:    flw fa5, %lo(.LCPI5_1)(a1)
 ; RV32IZFH-NEXT:    flt.s a3, fa5, fs0
 ; RV32IZFH-NEXT:    beqz a3, .LBB5_6
 ; RV32IZFH-NEXT:  # %bb.5:
 ; RV32IZFH-NEXT:    addi a2, a4, -1
 ; RV32IZFH-NEXT:  .LBB5_6:
 ; RV32IZFH-NEXT:    feq.s a1, fs0, fs0
 ; RV32IZFH-NEXT:    neg a4, a1
 ; RV32IZFH-NEXT:    and a1, a4, a2
-; RV32IZFH-NEXT:    neg a2, s0
-; RV32IZFH-NEXT:    and a0, a2, a0
+; RV32IZFH-NEXT:    addi s0, s0, -1
+; RV32IZFH-NEXT:    and a0, s0, a0
 ; RV32IZFH-NEXT:    neg a2, a3
 ; RV32IZFH-NEXT:    or a0, a2, a0
 ; RV32IZFH-NEXT:    and a0, a4, a0
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_ceil_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rup
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IZHINX-LABEL: test_ceil_si64:
 ; RV32IZHINX:       # %bb.0:
 ; RV32IZHINX-NEXT:    addi sp, sp, -16
 ; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI5_0)
 ; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI5_0)(a1)
 ; RV32IZHINX-NEXT:    fabs.h a2, a0
 ; RV32IZHINX-NEXT:    flt.h a1, a2, a1
 ; RV32IZHINX-NEXT:    beqz a1, .LBB5_2
 ; RV32IZHINX-NEXT:  # %bb.1:
 ; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rup
 ; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rup
 ; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
 ; RV32IZHINX-NEXT:  .LBB5_2:
 ; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINX-NEXT:    lui a0, 913408
-; RV32IZHINX-NEXT:    fle.s s1, a0, s0
-; RV32IZHINX-NEXT:    neg s2, s1
 ; RV32IZHINX-NEXT:    mv a0, s0
 ; RV32IZHINX-NEXT:    call __fixsfdi@plt
-; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI5_1)
-; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI5_1)(a2)
-; RV32IZHINX-NEXT:    and a0, s2, a0
-; RV32IZHINX-NEXT:    flt.s a4, a2, s0
+; RV32IZHINX-NEXT:    lui a2, 913408
+; RV32IZHINX-NEXT:    lui a3, %hi(.LCPI5_1)
+; RV32IZHINX-NEXT:    lw a3, %lo(.LCPI5_1)(a3)
+; RV32IZHINX-NEXT:    flt.s a6, s0, a2
+; RV32IZHINX-NEXT:    addi a2, a6, -1
+; RV32IZHINX-NEXT:    and a0, a2, a0
+; RV32IZHINX-NEXT:    flt.s a4, a3, s0
 ; RV32IZHINX-NEXT:    neg a2, a4
 ; RV32IZHINX-NEXT:    or a0, a2, a0
 ; RV32IZHINX-NEXT:    feq.s a2, s0, s0
 ; RV32IZHINX-NEXT:    neg a2, a2
 ; RV32IZHINX-NEXT:    lui a5, 524288
 ; RV32IZHINX-NEXT:    lui a3, 524288
-; RV32IZHINX-NEXT:    beqz s1, .LBB5_4
+; RV32IZHINX-NEXT:    bnez a6, .LBB5_4
 ; RV32IZHINX-NEXT:  # %bb.3:
 ; RV32IZHINX-NEXT:    mv a3, a1
 ; RV32IZHINX-NEXT:  .LBB5_4:
 ; RV32IZHINX-NEXT:    and a0, a2, a0
 ; RV32IZHINX-NEXT:    beqz a4, .LBB5_6
 ; RV32IZHINX-NEXT:  # %bb.5:
 ; RV32IZHINX-NEXT:    addi a3, a5, -1
 ; RV32IZHINX-NEXT:  .LBB5_6:
 ; RV32IZHINX-NEXT:    and a1, a2, a3
 ; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    addi sp, sp, 16
 ; RV32IZHINX-NEXT:    ret
 ;
 ; RV64IZHINX-LABEL: test_ceil_si64:
 ; RV64IZHINX:       # %bb.0:
 ; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI5_0)
 ; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI5_0)(a1)
 ; RV64IZHINX-NEXT:    fabs.h a2, a0

 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, fa5
 ; RV32IZFHMIN-NEXT:    lui a0, 913408
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa5, a0
-; RV32IZFHMIN-NEXT:    fle.s s0, fa5, fs0
+; RV32IZFHMIN-NEXT:    flt.s s0, fs0, fa5
 ; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
 ; RV32IZFHMIN-NEXT:    call __fixsfdi@plt
 ; RV32IZFHMIN-NEXT:    lui a4, 524288
 ; RV32IZFHMIN-NEXT:    lui a2, 524288
-; RV32IZFHMIN-NEXT:    beqz s0, .LBB5_4
+; RV32IZFHMIN-NEXT:    bnez s0, .LBB5_4
 ; RV32IZFHMIN-NEXT:  # %bb.3:
 ; RV32IZFHMIN-NEXT:    mv a2, a1
 ; RV32IZFHMIN-NEXT:  .LBB5_4:
 ; RV32IZFHMIN-NEXT:    lui a1, %hi(.LCPI5_0)
 ; RV32IZFHMIN-NEXT:    flw fa5, %lo(.LCPI5_0)(a1)
 ; RV32IZFHMIN-NEXT:    flt.s a3, fa5, fs0
 ; RV32IZFHMIN-NEXT:    beqz a3, .LBB5_6
 ; RV32IZFHMIN-NEXT:  # %bb.5:
 ; RV32IZFHMIN-NEXT:    addi a2, a4, -1
 ; RV32IZFHMIN-NEXT:  .LBB5_6:
 ; RV32IZFHMIN-NEXT:    feq.s a1, fs0, fs0
 ; RV32IZFHMIN-NEXT:    neg a4, a1
 ; RV32IZFHMIN-NEXT:    and a1, a4, a2
-; RV32IZFHMIN-NEXT:    neg a2, s0
-; RV32IZFHMIN-NEXT:    and a0, a2, a0
+; RV32IZFHMIN-NEXT:    addi s0, s0, -1
+; RV32IZFHMIN-NEXT:    and a0, s0, a0
 ; RV32IZFHMIN-NEXT:    neg a2, a3
 ; RV32IZFHMIN-NEXT:    or a0, a2, a0
 ; RV32IZFHMIN-NEXT:    and a0, a4, a0
 ; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32IZFHMIN-NEXT:    ret

 ; RV32IZHINXMIN-NEXT:  # %bb.1:
 ; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
 ; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
 ; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
 ; RV32IZHINXMIN-NEXT:  .LBB5_2:
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
 ; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
 ; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINXMIN-NEXT:    lui a0, 913408
-; RV32IZHINXMIN-NEXT:    fle.s s1, a0, s0
-; RV32IZHINXMIN-NEXT:    neg s2, s1
 ; RV32IZHINXMIN-NEXT:    mv a0, s0
 ; RV32IZHINXMIN-NEXT:    call __fixsfdi@plt
-; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI5_0)
-; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI5_0)(a2)
-; RV32IZHINXMIN-NEXT:    and a0, s2, a0
-; RV32IZHINXMIN-NEXT:    flt.s a4, a2, s0
+; RV32IZHINXMIN-NEXT:    lui a2, 913408
+; RV32IZHINXMIN-NEXT:    lui a3, %hi(.LCPI5_0)
+; RV32IZHINXMIN-NEXT:    lw a3, %lo(.LCPI5_0)(a3)
+; RV32IZHINXMIN-NEXT:    flt.s a6, s0, a2
+; RV32IZHINXMIN-NEXT:    addi a2, a6, -1
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a4, a3, s0
 ; RV32IZHINXMIN-NEXT:    neg a2, a4
 ; RV32IZHINXMIN-NEXT:    or a0, a2, a0
 ; RV32IZHINXMIN-NEXT:    feq.s a2, s0, s0
 ; RV32IZHINXMIN-NEXT:    neg a2, a2
 ; RV32IZHINXMIN-NEXT:    lui a5, 524288
 ; RV32IZHINXMIN-NEXT:    lui a3, 524288
-; RV32IZHINXMIN-NEXT:    beqz s1, .LBB5_4
-; RV32IZHINXMIN-NEXT:  # %bb.3:
-; RV32IZHINXMIN-NEXT:    mv a3, a1
-; RV32IZHINXMIN-NEXT:  .LBB5_4:
-; RV32IZHINXMIN-NEXT:    and a0, a2, a0
 ; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
-; RV32IZHINXMIN-NEXT:    beqz a4, .LBB5_6
-; RV32IZHINXMIN-NEXT:  # %bb.5:
-; RV32IZHINXMIN-NEXT:    addi a3, a5, -1
+; RV32IZHINXMIN-NEXT:    beqz a6, .LBB5_5
+; RV32IZHINXMIN-NEXT:  # %bb.3:
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    bnez a4, .LBB5_6
+; RV32IZHINXMIN-NEXT:  .LBB5_4:
+; RV32IZHINXMIN-NEXT:    and a1, a2, a3
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB5_5:
+; RV32IZHINXMIN-NEXT:    mv a3, a1
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    beqz a4, .LBB5_4
 ; RV32IZHINXMIN-NEXT:  .LBB5_6:
+; RV32IZHINXMIN-NEXT:    addi a3, a5, -1
 ; RV32IZHINXMIN-NEXT:    and a1, a2, a3
 ; RV32IZHINXMIN-NEXT:    ret
 ;
 ; RV64IZHINXMIN-LABEL: test_ceil_si64:
 ; RV64IZHINXMIN:       # %bb.0:
 ; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
 ; RV64IZHINXMIN-NEXT:    lui a1, 307200
 ; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
; RV64IZHINXMIN-NEXT:    ret
   ret i32 %b
 }
 
 define i64 @test_ceil_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_ceil_ui64:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI7_0)
 ; RV32IZFH-NEXT:    flh fa5, %lo(.LCPI7_0)(a0)
 ; RV32IZFH-NEXT:    fabs.h fa4, fa0
 ; RV32IZFH-NEXT:    flt.h a0, fa4, fa5
 ; RV32IZFH-NEXT:    beqz a0, .LBB7_2
 ; RV32IZFH-NEXT:  # %bb.1:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rup
 ; RV32IZFH-NEXT:    fcvt.h.w fa5, a0, rup
 ; RV32IZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; RV32IZFH-NEXT:  .LBB7_2:
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, fa0
-; RV32IZFH-NEXT:    fmv.w.x fa5, zero
-; RV32IZFH-NEXT:    fle.s a0, fa5, fs0
-; RV32IZFH-NEXT:    neg s0, a0
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixunssfdi@plt
+; RV32IZFH-NEXT:    fmv.w.x fa5, zero
 ; RV32IZFH-NEXT:    lui a2, %hi(.LCPI7_1)
-; RV32IZFH-NEXT:    flw fa5, %lo(.LCPI7_1)(a2)
-; RV32IZFH-NEXT:    and a0, s0, a0
-; RV32IZFH-NEXT:    flt.s a2, fa5, fs0
-; RV32IZFH-NEXT:    neg a2, a2
-; RV32IZFH-NEXT:    or a0, a2, a0
-; RV32IZFH-NEXT:    and a1, s0, a1
-; RV32IZFH-NEXT:    or a1, a2, a1
+; RV32IZFH-NEXT:    flw fa4, %lo(.LCPI7_1)(a2)
+; RV32IZFH-NEXT:    flt.s a2, fs0, fa5
+; RV32IZFH-NEXT:    addi a2, a2, -1
+; RV32IZFH-NEXT:    and a0, a2, a0
+; RV32IZFH-NEXT:    flt.s a3, fa4, fs0
+; RV32IZFH-NEXT:    neg a3, a3
+; RV32IZFH-NEXT:    or a0, a3, a0
+; RV32IZFH-NEXT:    and a1, a2, a1
+; RV32IZFH-NEXT:    or a1, a3, a1
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_ceil_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rup
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IZHINX-LABEL: test_ceil_ui64:
 ; RV32IZHINX:       # %bb.0:
 ; RV32IZHINX-NEXT:    addi sp, sp, -16
 ; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI7_0)
 ; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI7_0)(a1)
 ; RV32IZHINX-NEXT:    fabs.h a2, a0
 ; RV32IZHINX-NEXT:    flt.h a1, a2, a1
 ; RV32IZHINX-NEXT:    beqz a1, .LBB7_2
 ; RV32IZHINX-NEXT:  # %bb.1:
 ; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rup
 ; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rup
 ; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
 ; RV32IZHINX-NEXT:  .LBB7_2:
 ; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINX-NEXT:    fle.s a0, zero, s0
-; RV32IZHINX-NEXT:    neg s1, a0
 ; RV32IZHINX-NEXT:    mv a0, s0
 ; RV32IZHINX-NEXT:    call __fixunssfdi@plt
 ; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI7_1)
 ; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI7_1)(a2)
-; RV32IZHINX-NEXT:    and a0, s1, a0
+; RV32IZHINX-NEXT:    flt.s a3, s0, zero
+; RV32IZHINX-NEXT:    addi a3, a3, -1
+; RV32IZHINX-NEXT:    and a0, a3, a0
 ; RV32IZHINX-NEXT:    flt.s a2, a2, s0
 ; RV32IZHINX-NEXT:    neg a2, a2
 ; RV32IZHINX-NEXT:    or a0, a2, a0
-; RV32IZHINX-NEXT:    and a1, s1, a1
+; RV32IZHINX-NEXT:    and a1, a3, a1
 ; RV32IZHINX-NEXT:    or a1, a2, a1
 ; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    addi sp, sp, 16
 ; RV32IZHINX-NEXT:    ret
 ;
 ; RV64IZHINX-LABEL: test_ceil_ui64:
 ; RV64IZHINX:       # %bb.0:
 ; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI7_0)
 ; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI7_0)(a1)
 ; RV64IZHINX-NEXT:    fabs.h a2, a0

 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB7_2
 ; RV32IZFHMIN-NEXT:  # %bb.1:
 ; RV32IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rup
 ; RV32IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rup
 ; RV32IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV32IZFHMIN-NEXT:  .LBB7_2:
 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, fa5
-; RV32IZFHMIN-NEXT:    fmv.w.x fa5, zero
-; RV32IZFHMIN-NEXT:    fle.s a0, fa5, fs0
-; RV32IZFHMIN-NEXT:    neg s0, a0
 ; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
 ; RV32IZFHMIN-NEXT:    call __fixunssfdi@plt
+; RV32IZFHMIN-NEXT:    fmv.w.x fa5, zero
 ; RV32IZFHMIN-NEXT:    lui a2, %hi(.LCPI7_0)
-; RV32IZFHMIN-NEXT:    flw fa5, %lo(.LCPI7_0)(a2)
-; RV32IZFHMIN-NEXT:    and a0, s0, a0
-; RV32IZFHMIN-NEXT:    flt.s a2, fa5, fs0
-; RV32IZFHMIN-NEXT:    neg a2, a2
-; RV32IZFHMIN-NEXT:    or a0, a2, a0
-; RV32IZFHMIN-NEXT:    and a1, s0, a1
-; RV32IZFHMIN-NEXT:    or a1, a2, a1
+; RV32IZFHMIN-NEXT:    flw fa4, %lo(.LCPI7_0)(a2)
+; RV32IZFHMIN-NEXT:    flt.s a2, fs0, fa5
+; RV32IZFHMIN-NEXT:    addi a2, a2, -1
+; RV32IZFHMIN-NEXT:    and a0, a2, a0
+; RV32IZFHMIN-NEXT:    flt.s a3, fa4, fs0
+; RV32IZFHMIN-NEXT:    neg a3, a3
+; RV32IZFHMIN-NEXT:    or a0, a3, a0
+; RV32IZFHMIN-NEXT:    and a1, a2, a1
+; RV32IZFHMIN-NEXT:    or a1, a3, a1
 ; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32IZFHMIN-NEXT:    ret
 ;
 ; RV64IZFHMIN-LABEL: test_ceil_ui64:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    lui a0, 307200
 ; RV64IZFHMIN-NEXT:    fmv.w.x fa4, a0

 ; RV32IZHINXMIN-NEXT:  # %bb.1:
 ; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
 ; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
 ; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
 ; RV32IZHINXMIN-NEXT:  .LBB7_2:
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
 ; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
 ; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINXMIN-NEXT:    fle.s a0, zero, s0
-; RV32IZHINXMIN-NEXT:    neg s1, a0
 ; RV32IZHINXMIN-NEXT:    mv a0, s0
 ; RV32IZHINXMIN-NEXT:    call __fixunssfdi@plt
 ; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI7_0)
 ; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI7_0)(a2)
-; RV32IZHINXMIN-NEXT:    and a0, s1, a0
+; RV32IZHINXMIN-NEXT:    flt.s a3, s0, zero
+; RV32IZHINXMIN-NEXT:    addi a3, a3, -1
+; RV32IZHINXMIN-NEXT:    and a0, a3, a0
 ; RV32IZHINXMIN-NEXT:    flt.s a2, a2, s0
 ; RV32IZHINXMIN-NEXT:    neg a2, a2
 ; RV32IZHINXMIN-NEXT:    or a0, a2, a0
-; RV32IZHINXMIN-NEXT:    and a1, s1, a1
+; RV32IZHINXMIN-NEXT:    and a1, a3, a1
 ; RV32IZHINXMIN-NEXT:    or a1, a2, a1
 ; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
 ; RV32IZHINXMIN-NEXT:    ret
 ;
 ; RV64IZHINXMIN-LABEL: test_ceil_ui64:
 ; RV64IZHINXMIN:       # %bb.0:
 ; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
 ; RV64IZHINXMIN-NEXT:    lui a1, 307200
 ; RV64IZHINXMIN-NEXT:    fabs.s a2, a0

 ; RV32IZFH-NEXT:  # %bb.1:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IZFH-NEXT:    fcvt.h.w fa5, a0, rtz
 ; RV32IZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; RV32IZFH-NEXT:  .LBB9_2:
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, fa0
 ; RV32IZFH-NEXT:    lui a0, 913408
 ; RV32IZFH-NEXT:    fmv.w.x fa5, a0
-; RV32IZFH-NEXT:    fle.s s0, fa5, fs0
+; RV32IZFH-NEXT:    flt.s s0, fs0, fa5
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixsfdi@plt
 ; RV32IZFH-NEXT:    lui a4, 524288
 ; RV32IZFH-NEXT:    lui a2, 524288
-; RV32IZFH-NEXT:    beqz s0, .LBB9_4
+; RV32IZFH-NEXT:    bnez s0, .LBB9_4
 ; RV32IZFH-NEXT:  # %bb.3:
 ; RV32IZFH-NEXT:    mv a2, a1
 ; RV32IZFH-NEXT:  .LBB9_4:
 ; RV32IZFH-NEXT:    lui a1, %hi(.LCPI9_1)
 ; RV32IZFH-NEXT:    flw fa5, %lo(.LCPI9_1)(a1)
 ; RV32IZFH-NEXT:    flt.s a3, fa5, fs0
 ; RV32IZFH-NEXT:    beqz a3, .LBB9_6
 ; RV32IZFH-NEXT:  # %bb.5:
 ; RV32IZFH-NEXT:    addi a2, a4, -1
 ; RV32IZFH-NEXT:  .LBB9_6:
 ; RV32IZFH-NEXT:    feq.s a1, fs0, fs0
 ; RV32IZFH-NEXT:    neg a4, a1
 ; RV32IZFH-NEXT:    and a1, a4, a2
-; RV32IZFH-NEXT:    neg a2, s0
-; RV32IZFH-NEXT:    and a0, a2, a0
+; RV32IZFH-NEXT:    addi s0, s0, -1
+; RV32IZFH-NEXT:    and a0, s0, a0
 ; RV32IZFH-NEXT:    neg a2, a3
 ; RV32IZFH-NEXT:    or a0, a2, a0
 ; RV32IZFH-NEXT:    and a0, a4, a0
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_trunc_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IZHINX-LABEL: test_trunc_si64:
 ; RV32IZHINX:       # %bb.0:
 ; RV32IZHINX-NEXT:    addi sp, sp, -16
 ; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI9_0)
 ; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI9_0)(a1)
 ; RV32IZHINX-NEXT:    fabs.h a2, a0
 ; RV32IZHINX-NEXT:    flt.h a1, a2, a1
 ; RV32IZHINX-NEXT:    beqz a1, .LBB9_2
 ; RV32IZHINX-NEXT:  # %bb.1:
 ; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
 ; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
 ; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
 ; RV32IZHINX-NEXT:  .LBB9_2:
 ; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINX-NEXT:    lui a0, 913408
-; RV32IZHINX-NEXT:    fle.s s1, a0, s0
-; RV32IZHINX-NEXT:    neg s2, s1
 ; RV32IZHINX-NEXT:    mv a0, s0
 ; RV32IZHINX-NEXT:    call __fixsfdi@plt
-; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI9_1)
-; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI9_1)(a2)
-; RV32IZHINX-NEXT:    and a0, s2, a0
-; RV32IZHINX-NEXT:    flt.s a4, a2, s0
+; RV32IZHINX-NEXT:    lui a2, 913408
+; RV32IZHINX-NEXT:    lui a3, %hi(.LCPI9_1)
+; RV32IZHINX-NEXT:    lw a3, %lo(.LCPI9_1)(a3)
+; RV32IZHINX-NEXT:    flt.s a6, s0, a2
+; RV32IZHINX-NEXT:    addi a2, a6, -1
+; RV32IZHINX-NEXT:    and a0, a2, a0
+; RV32IZHINX-NEXT:    flt.s a4, a3, s0
 ; RV32IZHINX-NEXT:    neg a2, a4
 ; RV32IZHINX-NEXT:    or a0, a2, a0
 ; RV32IZHINX-NEXT:    feq.s a2, s0, s0
 ; RV32IZHINX-NEXT:    neg a2, a2
 ; RV32IZHINX-NEXT:    lui a5, 524288
 ; RV32IZHINX-NEXT:    lui a3, 524288
-; RV32IZHINX-NEXT:    beqz s1, .LBB9_4
+; RV32IZHINX-NEXT:    bnez a6, .LBB9_4
 ; RV32IZHINX-NEXT:  # %bb.3:
 ; RV32IZHINX-NEXT:    mv a3, a1
 ; RV32IZHINX-NEXT:  .LBB9_4:
 ; RV32IZHINX-NEXT:    and a0, a2, a0
 ; RV32IZHINX-NEXT:    beqz a4, .LBB9_6
 ; RV32IZHINX-NEXT:  # %bb.5:
 ; RV32IZHINX-NEXT:    addi a3, a5, -1
 ; RV32IZHINX-NEXT:  .LBB9_6:
 ; RV32IZHINX-NEXT:    and a1, a2, a3
 ; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    addi sp, sp, 16
 ; RV32IZHINX-NEXT:    ret
 ;
 ; RV64IZHINX-LABEL: test_trunc_si64:
 ; RV64IZHINX:       # %bb.0:
 ; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI9_0)
 ; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI9_0)(a1)
 ; RV64IZHINX-NEXT:    fabs.h a2, a0

 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, fa5
 ; RV32IZFHMIN-NEXT:    lui a0, 913408
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa5, a0
-; RV32IZFHMIN-NEXT:    fle.s s0, fa5, fs0
+; RV32IZFHMIN-NEXT:    flt.s s0, fs0, fa5
 ; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
 ; RV32IZFHMIN-NEXT:    call __fixsfdi@plt
 ; RV32IZFHMIN-NEXT:    lui a4, 524288
 ; RV32IZFHMIN-NEXT:    lui a2, 524288
-; RV32IZFHMIN-NEXT:    beqz s0, .LBB9_4
+; RV32IZFHMIN-NEXT:    bnez s0, .LBB9_4
 ; RV32IZFHMIN-NEXT:  # %bb.3:
 ; RV32IZFHMIN-NEXT:    mv a2, a1
 ; RV32IZFHMIN-NEXT:  .LBB9_4:
 ; RV32IZFHMIN-NEXT:    lui a1, %hi(.LCPI9_0)
 ; RV32IZFHMIN-NEXT:    flw fa5, %lo(.LCPI9_0)(a1)
 ; RV32IZFHMIN-NEXT:    flt.s a3, fa5, fs0
 ; RV32IZFHMIN-NEXT:    beqz a3, .LBB9_6
 ; RV32IZFHMIN-NEXT:  # %bb.5:
 ; RV32IZFHMIN-NEXT:    addi a2, a4, -1
 ; RV32IZFHMIN-NEXT:  .LBB9_6:
 ; RV32IZFHMIN-NEXT:    feq.s a1, fs0, fs0
 ; RV32IZFHMIN-NEXT:    neg a4, a1
 ; RV32IZFHMIN-NEXT:    and a1, a4, a2
-; RV32IZFHMIN-NEXT:    neg a2, s0
-; RV32IZFHMIN-NEXT:    and a0, a2, a0
+; RV32IZFHMIN-NEXT:    addi s0, s0, -1
+; RV32IZFHMIN-NEXT:    and a0, s0, a0
 ; RV32IZFHMIN-NEXT:    neg a2, a3
 ; RV32IZFHMIN-NEXT:    or a0, a2, a0
 ; RV32IZFHMIN-NEXT:    and a0, a4, a0
 ; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32IZFHMIN-NEXT:    ret

 ; RV32IZHINXMIN-NEXT:  # %bb.1:
 ; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
 ; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
 ; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
 ; RV32IZHINXMIN-NEXT:  .LBB9_2:
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
 ; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
 ; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINXMIN-NEXT:    lui a0, 913408
-; RV32IZHINXMIN-NEXT:    fle.s s1, a0, s0
-; RV32IZHINXMIN-NEXT:    neg s2, s1
 ; RV32IZHINXMIN-NEXT:    mv a0, s0
 ; RV32IZHINXMIN-NEXT:    call __fixsfdi@plt
-; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI9_0)
-; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI9_0)(a2)
-; RV32IZHINXMIN-NEXT:    and a0, s2, a0
-; RV32IZHINXMIN-NEXT:    flt.s a4, a2, s0
+; RV32IZHINXMIN-NEXT:    lui a2, 913408
+; RV32IZHINXMIN-NEXT:    lui a3, %hi(.LCPI9_0)
+; RV32IZHINXMIN-NEXT:    lw a3, %lo(.LCPI9_0)(a3)
+; RV32IZHINXMIN-NEXT:    flt.s a6, s0, a2
+; RV32IZHINXMIN-NEXT:    addi a2, a6, -1
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a4, a3, s0
 ; RV32IZHINXMIN-NEXT:    neg a2, a4
 ; RV32IZHINXMIN-NEXT:    or a0, a2, a0
 ; RV32IZHINXMIN-NEXT:    feq.s a2, s0, s0
 ; RV32IZHINXMIN-NEXT:    neg a2, a2
 ; RV32IZHINXMIN-NEXT:    lui a5, 524288
 ; RV32IZHINXMIN-NEXT:    lui a3, 524288
-; RV32IZHINXMIN-NEXT:    beqz s1, .LBB9_4
-; RV32IZHINXMIN-NEXT:  # %bb.3:
-; RV32IZHINXMIN-NEXT:    mv a3, a1
-; RV32IZHINXMIN-NEXT:  .LBB9_4:
-; RV32IZHINXMIN-NEXT:    and a0, a2, a0
 ; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
-; RV32IZHINXMIN-NEXT:    beqz a4, .LBB9_6
-; RV32IZHINXMIN-NEXT:  # %bb.5:
-; RV32IZHINXMIN-NEXT:    addi a3, a5, -1
+; RV32IZHINXMIN-NEXT:    beqz a6, .LBB9_5
+; RV32IZHINXMIN-NEXT:  # %bb.3:
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    bnez a4, .LBB9_6
+; RV32IZHINXMIN-NEXT:  .LBB9_4:
+; RV32IZHINXMIN-NEXT:    and a1, a2, a3
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB9_5:
+; RV32IZHINXMIN-NEXT:    mv a3, a1
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    beqz a4, .LBB9_4
 ; RV32IZHINXMIN-NEXT:  .LBB9_6:
+; RV32IZHINXMIN-NEXT:    addi a3, a5, -1
 ; RV32IZHINXMIN-NEXT:    and a1, a2, a3
 ; RV32IZHINXMIN-NEXT:    ret
 ;
 ; RV64IZHINXMIN-LABEL: test_trunc_si64:
 ; RV64IZHINXMIN:       # %bb.0:
 ; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
 ; RV64IZHINXMIN-NEXT:    lui a1, 307200
 ; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
; RV64IZHINXMIN-NEXT:    ret
   ret i32 %b
 }
 
 define i64 @test_trunc_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_trunc_ui64:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI11_0)
 ; RV32IZFH-NEXT:    flh fa5, %lo(.LCPI11_0)(a0)
 ; RV32IZFH-NEXT:    fabs.h fa4, fa0
 ; RV32IZFH-NEXT:    flt.h a0, fa4, fa5
 ; RV32IZFH-NEXT:    beqz a0, .LBB11_2
 ; RV32IZFH-NEXT:  # %bb.1:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IZFH-NEXT:    fcvt.h.w fa5, a0, rtz
 ; RV32IZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; RV32IZFH-NEXT:  .LBB11_2:
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, fa0
-; RV32IZFH-NEXT:    fmv.w.x fa5, zero
-; RV32IZFH-NEXT:    fle.s a0, fa5, fs0
-; RV32IZFH-NEXT:    neg s0, a0
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixunssfdi@plt
+; RV32IZFH-NEXT:    fmv.w.x fa5, zero
 ; RV32IZFH-NEXT:    lui a2, %hi(.LCPI11_1)
-; RV32IZFH-NEXT:    flw fa5, %lo(.LCPI11_1)(a2)
-; RV32IZFH-NEXT:    and a0, s0, a0
-; RV32IZFH-NEXT:    flt.s a2, fa5, fs0
-; RV32IZFH-NEXT:    neg a2, a2
-; RV32IZFH-NEXT:    or a0, a2, a0
-; RV32IZFH-NEXT:    and a1, s0, a1
-; RV32IZFH-NEXT:    or a1, a2, a1
+; RV32IZFH-NEXT:    flw fa4, %lo(.LCPI11_1)(a2)
+; RV32IZFH-NEXT:    flt.s a2, fs0, fa5
+; RV32IZFH-NEXT:    addi a2, a2, -1
+; RV32IZFH-NEXT:    and a0, a2, a0
+; RV32IZFH-NEXT:    flt.s a3, fa4, fs0
+; RV32IZFH-NEXT:    neg a3, a3
+; RV32IZFH-NEXT:    or a0, a3, a0
+; RV32IZFH-NEXT:    and a1, a2, a1
+; RV32IZFH-NEXT:    or a1, a3, a1
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_trunc_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IZHINX-LABEL: test_trunc_ui64:
 ; RV32IZHINX:       # %bb.0:
 ; RV32IZHINX-NEXT:    addi sp, sp, -16
 ; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI11_0)
 ; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI11_0)(a1)
 ; RV32IZHINX-NEXT:    fabs.h a2, a0
 ; RV32IZHINX-NEXT:    flt.h a1, a2, a1
 ; RV32IZHINX-NEXT:    beqz a1, .LBB11_2
 ; RV32IZHINX-NEXT:  # %bb.1:
 ; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
 ; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
 ; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
 ; RV32IZHINX-NEXT:  .LBB11_2:
 ; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINX-NEXT:    fle.s a0, zero, s0
-; RV32IZHINX-NEXT:    neg s1, a0
 ; RV32IZHINX-NEXT:    mv a0, s0
 ; RV32IZHINX-NEXT:    call __fixunssfdi@plt
 ; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI11_1)
 ; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI11_1)(a2)
-; RV32IZHINX-NEXT:    and a0, s1, a0
+; RV32IZHINX-NEXT:    flt.s a3, s0, zero
+; RV32IZHINX-NEXT:    addi a3, a3, -1
+; RV32IZHINX-NEXT:    and a0, a3, a0
 ; RV32IZHINX-NEXT:    flt.s a2, a2, s0
 ; RV32IZHINX-NEXT:    neg a2, a2
 ; RV32IZHINX-NEXT:    or a0, a2, a0
-; RV32IZHINX-NEXT:    and a1, s1, a1
+; RV32IZHINX-NEXT:    and a1, a3, a1
 ; RV32IZHINX-NEXT:    or a1, a2, a1
 ; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    addi sp, sp, 16
 ; RV32IZHINX-NEXT:    ret
 ;
 ; RV64IZHINX-LABEL: test_trunc_ui64:
 ; RV64IZHINX:       # %bb.0:
 ; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI11_0)
 ; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI11_0)(a1)
 ; RV64IZHINX-NEXT:    fabs.h a2, a0

 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB11_2
 ; RV32IZFHMIN-NEXT:  # %bb.1:
 ; RV32IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; RV32IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rtz
 ; RV32IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV32IZFHMIN-NEXT:  .LBB11_2:
 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, fa5
-; RV32IZFHMIN-NEXT:    fmv.w.x fa5, zero
-; RV32IZFHMIN-NEXT:    fle.s a0, fa5, fs0
-; RV32IZFHMIN-NEXT:    neg s0, a0
 ; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
 ; RV32IZFHMIN-NEXT:    call __fixunssfdi@plt
+; RV32IZFHMIN-NEXT:    fmv.w.x fa5, zero
 ; RV32IZFHMIN-NEXT:    lui a2, %hi(.LCPI11_0)
-; RV32IZFHMIN-NEXT:    flw fa5, %lo(.LCPI11_0)(a2)
-; RV32IZFHMIN-NEXT:    and a0, s0, a0
-; RV32IZFHMIN-NEXT:    flt.s a2, fa5, fs0
-; RV32IZFHMIN-NEXT:    neg a2, a2
-; RV32IZFHMIN-NEXT:    or a0, a2, a0
-; RV32IZFHMIN-NEXT:    and a1, s0, a1
-; RV32IZFHMIN-NEXT:    or a1, a2, a1
+; RV32IZFHMIN-NEXT:    flw fa4, %lo(.LCPI11_0)(a2)
+; RV32IZFHMIN-NEXT:    flt.s a2, fs0, fa5
+; RV32IZFHMIN-NEXT:    addi a2, a2, -1
+; RV32IZFHMIN-NEXT:    and a0, a2, a0
+; RV32IZFHMIN-NEXT:    flt.s a3, fa4, fs0
+; RV32IZFHMIN-NEXT:    neg a3, a3
+; RV32IZFHMIN-NEXT:    or a0, a3, a0
+; RV32IZFHMIN-NEXT:    and a1, a2, a1
+; RV32IZFHMIN-NEXT:    or a1, a3, a1
 ; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32IZFHMIN-NEXT:    ret
 ;
 ; RV64IZFHMIN-LABEL: test_trunc_ui64:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    lui a0, 307200
 ; RV64IZFHMIN-NEXT:    fmv.w.x fa4, a0

 ; RV32IZHINXMIN-NEXT:  # %bb.1:
 ; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
 ; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
 ; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
 ; RV32IZHINXMIN-NEXT:  .LBB11_2:
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
 ; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
 ; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINXMIN-NEXT:    fle.s a0, zero, s0
-; RV32IZHINXMIN-NEXT:    neg s1, a0
 ; RV32IZHINXMIN-NEXT:    mv a0, s0
 ; RV32IZHINXMIN-NEXT:    call __fixunssfdi@plt
 ; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI11_0)
 ; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI11_0)(a2)
-; RV32IZHINXMIN-NEXT:    and a0, s1, a0
+; RV32IZHINXMIN-NEXT:    flt.s a3, s0, zero
+; RV32IZHINXMIN-NEXT:    addi a3, a3, -1
+; RV32IZHINXMIN-NEXT:    and a0, a3, a0
 ; RV32IZHINXMIN-NEXT:    flt.s a2, a2, s0
 ; RV32IZHINXMIN-NEXT:    neg a2, a2
 ; RV32IZHINXMIN-NEXT:    or a0, a2, a0
-; RV32IZHINXMIN-NEXT:    and a1, s1, a1
+; RV32IZHINXMIN-NEXT:    and a1, a3, a1
 ; RV32IZHINXMIN-NEXT:    or a1, a2, a1
 ; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
 ; RV32IZHINXMIN-NEXT:    ret
 ;
 ; RV64IZHINXMIN-LABEL: test_trunc_ui64:
 ; RV64IZHINXMIN:       # %bb.0:
 ; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
 ; RV64IZHINXMIN-NEXT:    lui a1, 307200
 ; RV64IZHINXMIN-NEXT:    fabs.s a2, a0

 ; RV32IZFH-NEXT:  # %bb.1:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; RV32IZFH-NEXT:    fcvt.h.w fa5, a0, rmm
 ; RV32IZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; RV32IZFH-NEXT:  .LBB13_2:
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, fa0
 ; RV32IZFH-NEXT:    lui a0, 913408
 ; RV32IZFH-NEXT:    fmv.w.x fa5, a0
-; RV32IZFH-NEXT:    fle.s s0, fa5, fs0
+; RV32IZFH-NEXT:    flt.s s0, fs0, fa5
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixsfdi@plt
 ; RV32IZFH-NEXT:    lui a4, 524288
 ; RV32IZFH-NEXT:    lui a2, 524288
-; RV32IZFH-NEXT:    beqz s0, .LBB13_4
+; RV32IZFH-NEXT:    bnez s0, .LBB13_4
 ; RV32IZFH-NEXT:  # %bb.3:
 ; RV32IZFH-NEXT:    mv a2, a1
 ; RV32IZFH-NEXT:  .LBB13_4:
 ; RV32IZFH-NEXT:    lui a1, %hi(.LCPI13_1)
 ; RV32IZFH-NEXT:    flw fa5, %lo(.LCPI13_1)(a1)
 ; RV32IZFH-NEXT:    flt.s a3, fa5, fs0
 ; RV32IZFH-NEXT:    beqz a3, .LBB13_6
 ; RV32IZFH-NEXT:  # %bb.5:
 ; RV32IZFH-NEXT:    addi a2, a4, -1
 ; RV32IZFH-NEXT:  .LBB13_6:
 ; RV32IZFH-NEXT:    feq.s a1, fs0, fs0
 ; RV32IZFH-NEXT:    neg a4, a1
 ; RV32IZFH-NEXT:    and a1, a4, a2
-; RV32IZFH-NEXT:    neg a2, s0
-; RV32IZFH-NEXT:    and a0, a2, a0
+; RV32IZFH-NEXT:    addi s0, s0, -1
+; RV32IZFH-NEXT:    and a0, s0, a0
 ; RV32IZFH-NEXT:    neg a2, a3
 ; RV32IZFH-NEXT:    or a0, a2, a0
 ; RV32IZFH-NEXT:    and a0, a4, a0
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_round_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IZHINX-LABEL: test_round_si64:
 ; RV32IZHINX:       # %bb.0:
 ; RV32IZHINX-NEXT:    addi sp, sp, -16
 ; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI13_0)
 ; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI13_0)(a1)
 ; RV32IZHINX-NEXT:    fabs.h a2, a0
 ; RV32IZHINX-NEXT:    flt.h a1, a2, a1
 ; RV32IZHINX-NEXT:    beqz a1, .LBB13_2
 ; RV32IZHINX-NEXT:  # %bb.1:
 ; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
 ; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
 ; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
 ; RV32IZHINX-NEXT:  .LBB13_2:
 ; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINX-NEXT:    lui a0, 913408
-; RV32IZHINX-NEXT:    fle.s s1, a0, s0
-; RV32IZHINX-NEXT:    neg s2, s1
 ; RV32IZHINX-NEXT:    mv a0, s0
 ; RV32IZHINX-NEXT:    call __fixsfdi@plt
-; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI13_1)
-; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI13_1)(a2)
-; RV32IZHINX-NEXT:    and a0, s2, a0
-; RV32IZHINX-NEXT:    flt.s a4, a2, s0
+; RV32IZHINX-NEXT:    lui a2, 913408
+; RV32IZHINX-NEXT:    lui a3, %hi(.LCPI13_1)
+; RV32IZHINX-NEXT:    lw a3, %lo(.LCPI13_1)(a3)
+; RV32IZHINX-NEXT:    flt.s a6, s0, a2
+; RV32IZHINX-NEXT:    addi a2, a6, -1
+; RV32IZHINX-NEXT:    and a0, a2, a0
+; RV32IZHINX-NEXT:    flt.s a4, a3, s0
 ; RV32IZHINX-NEXT:    neg a2, a4
 ; RV32IZHINX-NEXT:    or a0, a2, a0
 ; RV32IZHINX-NEXT:    feq.s a2, s0, s0
 ; RV32IZHINX-NEXT:    neg a2, a2
 ; RV32IZHINX-NEXT:    lui a5, 524288
 ; RV32IZHINX-NEXT:    lui a3, 524288
-; RV32IZHINX-NEXT:    beqz s1, .LBB13_4
+; RV32IZHINX-NEXT:    bnez a6, .LBB13_4
 ; RV32IZHINX-NEXT:  # %bb.3:
 ; RV32IZHINX-NEXT:    mv a3, a1
 ; RV32IZHINX-NEXT:  .LBB13_4:
 ; RV32IZHINX-NEXT:    and a0, a2, a0
 ; RV32IZHINX-NEXT:    beqz a4, .LBB13_6
 ; RV32IZHINX-NEXT:  # %bb.5:
 ; RV32IZHINX-NEXT:    addi a3, a5, -1
 ; RV32IZHINX-NEXT:  .LBB13_6:
 ; RV32IZHINX-NEXT:    and a1, a2, a3
 ; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    addi sp, sp, 16
 ; RV32IZHINX-NEXT:    ret
 ;
 ; RV64IZHINX-LABEL: test_round_si64:
 ; RV64IZHINX:       # %bb.0:
 ; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI13_0)
 ; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI13_0)(a1)
 ; RV64IZHINX-NEXT:    fabs.h a2, a0

 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, fa5
 ; RV32IZFHMIN-NEXT:    lui a0, 913408
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa5, a0
-; RV32IZFHMIN-NEXT:    fle.s s0, fa5, fs0
+; RV32IZFHMIN-NEXT:    flt.s s0, fs0, fa5
 ; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
 ; RV32IZFHMIN-NEXT:    call __fixsfdi@plt
 ; RV32IZFHMIN-NEXT:    lui a4, 524288
 ; RV32IZFHMIN-NEXT:    lui a2, 524288
-; RV32IZFHMIN-NEXT:    beqz s0, .LBB13_4
+; RV32IZFHMIN-NEXT:    bnez s0, .LBB13_4
 ; RV32IZFHMIN-NEXT:  # %bb.3:
 ; RV32IZFHMIN-NEXT:    mv a2, a1
 ; RV32IZFHMIN-NEXT:  .LBB13_4:
 ; RV32IZFHMIN-NEXT:    lui a1, %hi(.LCPI13_0)
 ; RV32IZFHMIN-NEXT:    flw fa5, %lo(.LCPI13_0)(a1)
 ; RV32IZFHMIN-NEXT:    flt.s a3, fa5, fs0
 ; RV32IZFHMIN-NEXT:    beqz a3, .LBB13_6
 ; RV32IZFHMIN-NEXT:  # %bb.5:
 ; RV32IZFHMIN-NEXT:    addi a2, a4, -1
 ; RV32IZFHMIN-NEXT:  .LBB13_6:
 ; RV32IZFHMIN-NEXT:    feq.s a1, fs0, fs0
 ; RV32IZFHMIN-NEXT:    neg a4, a1
 ; RV32IZFHMIN-NEXT:    and a1, a4, a2
-; RV32IZFHMIN-NEXT:    neg a2, s0
-; RV32IZFHMIN-NEXT:    and a0, a2, a0
+; RV32IZFHMIN-NEXT:    addi s0, s0, -1
+; RV32IZFHMIN-NEXT:    and a0, s0, a0
 ; RV32IZFHMIN-NEXT:    neg a2, a3
 ; RV32IZFHMIN-NEXT:    or a0, a2, a0
 ; RV32IZFHMIN-NEXT:    and a0, a4, a0
 ; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32IZFHMIN-NEXT:    ret

 ; RV32IZHINXMIN-NEXT:  # %bb.1:
 ; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
 ; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
 ; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
 ; RV32IZHINXMIN-NEXT:  .LBB13_2:
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
 ; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
 ; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINXMIN-NEXT:    lui a0, 913408
-; RV32IZHINXMIN-NEXT:    fle.s s1, a0, s0
-; RV32IZHINXMIN-NEXT:    neg s2, s1
 ; RV32IZHINXMIN-NEXT:    mv a0, s0
 ; RV32IZHINXMIN-NEXT:    call __fixsfdi@plt
-; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI13_0)
-; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI13_0)(a2)
-; RV32IZHINXMIN-NEXT:    and a0, s2, a0
-; RV32IZHINXMIN-NEXT:    flt.s a4, a2, s0
+; RV32IZHINXMIN-NEXT:    lui a2, 913408
+; RV32IZHINXMIN-NEXT:    lui a3, %hi(.LCPI13_0)
+; RV32IZHINXMIN-NEXT:    lw a3, %lo(.LCPI13_0)(a3)
+; RV32IZHINXMIN-NEXT:    flt.s a6, s0, a2
+; RV32IZHINXMIN-NEXT:    addi a2, a6, -1
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a4, a3, s0
 ; RV32IZHINXMIN-NEXT:    neg a2, a4
 ; RV32IZHINXMIN-NEXT:    or a0, a2, a0
 ; RV32IZHINXMIN-NEXT:    feq.s a2, s0, s0
 ; RV32IZHINXMIN-NEXT:    neg a2, a2
 ; RV32IZHINXMIN-NEXT:    lui a5, 524288
 ; RV32IZHINXMIN-NEXT:    lui a3, 524288
-; RV32IZHINXMIN-NEXT:    beqz s1, .LBB13_4
-; RV32IZHINXMIN-NEXT:  # %bb.3:
-; RV32IZHINXMIN-NEXT:    mv a3, a1
-; RV32IZHINXMIN-NEXT:  .LBB13_4:
-; RV32IZHINXMIN-NEXT:    and a0, a2, a0
 ; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
-; RV32IZHINXMIN-NEXT:    beqz a4, .LBB13_6
-; RV32IZHINXMIN-NEXT:  # %bb.5:
-; RV32IZHINXMIN-NEXT:    addi a3, a5, -1
+; RV32IZHINXMIN-NEXT:    beqz a6, .LBB13_5
+; RV32IZHINXMIN-NEXT:  # %bb.3:
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    bnez a4, .LBB13_6
+; RV32IZHINXMIN-NEXT:  .LBB13_4:
+; RV32IZHINXMIN-NEXT:    and a1, a2, a3
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB13_5:
+; RV32IZHINXMIN-NEXT:    mv a3, a1
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    beqz a4, .LBB13_4
 ; RV32IZHINXMIN-NEXT:  .LBB13_6:
+; RV32IZHINXMIN-NEXT:    addi a3, a5, -1
 ; RV32IZHINXMIN-NEXT:    and a1, a2, a3
 ; RV32IZHINXMIN-NEXT:    ret
 ;
 ; RV64IZHINXMIN-LABEL: test_round_si64:
 ; RV64IZHINXMIN:       # %bb.0:
 ; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
 ; RV64IZHINXMIN-NEXT:    lui a1, 307200
 ; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
; RV64IZHINXMIN-NEXT:    ret
   ret i32 %b
 }
 
 define i64 @test_round_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_round_ui64:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI15_0)
 ; RV32IZFH-NEXT:    flh fa5, %lo(.LCPI15_0)(a0)
 ; RV32IZFH-NEXT:    fabs.h fa4, fa0
 ; RV32IZFH-NEXT:    flt.h a0, fa4, fa5
 ; RV32IZFH-NEXT:    beqz a0, .LBB15_2
 ; RV32IZFH-NEXT:  # %bb.1:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; RV32IZFH-NEXT:    fcvt.h.w fa5, a0, rmm
 ; RV32IZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; RV32IZFH-NEXT:  .LBB15_2:
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, fa0
-; RV32IZFH-NEXT:    fmv.w.x fa5, zero
-; RV32IZFH-NEXT:    fle.s a0, fa5, fs0
-; RV32IZFH-NEXT:    neg s0, a0
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixunssfdi@plt
+; RV32IZFH-NEXT:    fmv.w.x fa5, zero
 ; RV32IZFH-NEXT:    lui a2, %hi(.LCPI15_1)
-; RV32IZFH-NEXT:    flw fa5, %lo(.LCPI15_1)(a2)
-; RV32IZFH-NEXT:    and a0, s0, a0
-; RV32IZFH-NEXT:    flt.s a2, fa5, fs0
-; RV32IZFH-NEXT:    neg a2, a2
-; RV32IZFH-NEXT:    or a0, a2, a0
-; RV32IZFH-NEXT:    and a1, s0, a1
-; RV32IZFH-NEXT:    or a1, a2, a1
+; RV32IZFH-NEXT:    flw fa4, %lo(.LCPI15_1)(a2)
+; RV32IZFH-NEXT:    flt.s a2, fs0, fa5
+; RV32IZFH-NEXT:    addi a2, a2, -1
+; RV32IZFH-NEXT:    and a0, a2, a0
+; RV32IZFH-NEXT:    flt.s a3, fa4, fs0
+; RV32IZFH-NEXT:    neg a3, a3
+; RV32IZFH-NEXT:    or a0, a3, a0
+; RV32IZFH-NEXT:    and a1, a2, a1
+; RV32IZFH-NEXT:    or a1, a3, a1
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_round_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IZHINX-LABEL: test_round_ui64:
 ; RV32IZHINX:       # %bb.0:
 ; RV32IZHINX-NEXT:    addi sp, sp, -16
 ; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI15_0)
 ; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI15_0)(a1)
 ; RV32IZHINX-NEXT:    fabs.h a2, a0
 ; RV32IZHINX-NEXT:    flt.h a1, a2, a1
 ; RV32IZHINX-NEXT:    beqz a1, .LBB15_2
 ; RV32IZHINX-NEXT:  # %bb.1:
 ; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
 ; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
 ; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
 ; RV32IZHINX-NEXT:  .LBB15_2:
 ; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINX-NEXT:    fle.s a0, zero, s0
-; RV32IZHINX-NEXT:    neg s1, a0
 ; RV32IZHINX-NEXT:    mv a0, s0
 ; RV32IZHINX-NEXT:    call __fixunssfdi@plt
 ; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI15_1)
 ; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI15_1)(a2)
-; RV32IZHINX-NEXT:    and a0, s1, a0
+; RV32IZHINX-NEXT:    flt.s a3, s0, zero
+; RV32IZHINX-NEXT:    addi a3, a3, -1
+; RV32IZHINX-NEXT:    and a0, a3, a0
 ; RV32IZHINX-NEXT:    flt.s a2, a2, s0
 ; RV32IZHINX-NEXT:    neg a2, a2
 ; RV32IZHINX-NEXT:    or a0, a2, a0
-; RV32IZHINX-NEXT:    and a1, s1, a1
+; RV32IZHINX-NEXT:    and a1, a3, a1
 ; RV32IZHINX-NEXT:    or a1, a2, a1
 ; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    addi sp, sp, 16
 ; RV32IZHINX-NEXT:    ret
 ;
 ; RV64IZHINX-LABEL: test_round_ui64:
 ; RV64IZHINX:       # %bb.0:
 ; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI15_0)
 ; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI15_0)(a1)
 ; RV64IZHINX-NEXT:    fabs.h a2, a0

 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB15_2
 ; RV32IZFHMIN-NEXT:  # %bb.1:
 ; RV32IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rmm
 ; RV32IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rmm
 ; RV32IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV32IZFHMIN-NEXT:  .LBB15_2:
 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, fa5
-; RV32IZFHMIN-NEXT:    fmv.w.x fa5, zero
-; RV32IZFHMIN-NEXT:    fle.s a0, fa5, fs0
-; RV32IZFHMIN-NEXT:    neg s0, a0
 ; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
 ; RV32IZFHMIN-NEXT:    call __fixunssfdi@plt
+; RV32IZFHMIN-NEXT:    fmv.w.x fa5, zero
 ; RV32IZFHMIN-NEXT:    lui a2, %hi(.LCPI15_0)
-; RV32IZFHMIN-NEXT:    flw fa5, %lo(.LCPI15_0)(a2)
-; RV32IZFHMIN-NEXT:    and a0, s0, a0
-; RV32IZFHMIN-NEXT:    flt.s a2, fa5, fs0
-; RV32IZFHMIN-NEXT:    neg a2, a2
-; RV32IZFHMIN-NEXT:    or a0, a2, a0
-; RV32IZFHMIN-NEXT:    and a1, s0, a1
-; RV32IZFHMIN-NEXT:    or a1, a2, a1
+; RV32IZFHMIN-NEXT:    flw fa4, %lo(.LCPI15_0)(a2)
+; RV32IZFHMIN-NEXT:    flt.s a2, fs0, fa5
+; RV32IZFHMIN-NEXT:    addi a2, a2, -1
+; RV32IZFHMIN-NEXT:    and a0, a2, a0
+; RV32IZFHMIN-NEXT:    flt.s a3, fa4, fs0
+; RV32IZFHMIN-NEXT:    neg a3, a3
+; RV32IZFHMIN-NEXT:    or a0, a3, a0
+; RV32IZFHMIN-NEXT:    and a1, a2, a1
+; RV32IZFHMIN-NEXT:    or a1, a3, a1
 ; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32IZFHMIN-NEXT:    ret
 ;
 ; RV64IZFHMIN-LABEL: test_round_ui64:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    lui a0, 307200
 ; RV64IZFHMIN-NEXT:    fmv.w.x fa4, a0

 ; RV32IZHINXMIN-NEXT:  # %bb.1:
 ; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
 ; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
 ; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
 ; RV32IZHINXMIN-NEXT:  .LBB15_2:
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
 ; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
 ; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINXMIN-NEXT:    fle.s a0, zero, s0
-; RV32IZHINXMIN-NEXT:    neg s1, a0
 ; RV32IZHINXMIN-NEXT:    mv a0, s0
 ; RV32IZHINXMIN-NEXT:    call __fixunssfdi@plt
 ; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI15_0)
 ; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI15_0)(a2)
-; RV32IZHINXMIN-NEXT:    and a0, s1, a0
+; RV32IZHINXMIN-NEXT:    flt.s a3, s0, zero
+; RV32IZHINXMIN-NEXT:    addi a3, a3, -1
+; RV32IZHINXMIN-NEXT:    and a0, a3, a0
 ; RV32IZHINXMIN-NEXT:    flt.s a2, a2, s0
 ; RV32IZHINXMIN-NEXT:    neg a2, a2
 ; RV32IZHINXMIN-NEXT:    or a0, a2, a0
-; RV32IZHINXMIN-NEXT:    and a1, s1, a1
+; RV32IZHINXMIN-NEXT:    and a1, a3, a1
 ; RV32IZHINXMIN-NEXT:    or a1, a2, a1
 ; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
 ; RV32IZHINXMIN-NEXT:    ret
 ;
 ; RV64IZHINXMIN-LABEL: test_round_ui64:
 ; RV64IZHINXMIN:       # %bb.0:
 ; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
 ; RV64IZHINXMIN-NEXT:    lui a1, 307200
 ; RV64IZHINXMIN-NEXT:    fabs.s a2, a0

 ; RV32IZFH-NEXT:  # %bb.1:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rne
 ; RV32IZFH-NEXT:    fcvt.h.w fa5, a0, rne
 ; RV32IZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; RV32IZFH-NEXT:  .LBB17_2:
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, fa0
 ; RV32IZFH-NEXT:    lui a0, 913408
 ; RV32IZFH-NEXT:    fmv.w.x fa5, a0
-; RV32IZFH-NEXT:    fle.s s0, fa5, fs0
+; RV32IZFH-NEXT:    flt.s s0, fs0, fa5
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixsfdi@plt
 ; RV32IZFH-NEXT:    lui a4, 524288
 ; RV32IZFH-NEXT:    lui a2, 524288
-; RV32IZFH-NEXT:    beqz s0, .LBB17_4
+; RV32IZFH-NEXT:    bnez s0, .LBB17_4
 ; RV32IZFH-NEXT:  # %bb.3:
 ; RV32IZFH-NEXT:    mv a2, a1
 ; RV32IZFH-NEXT:  .LBB17_4:
 ; RV32IZFH-NEXT:    lui a1, %hi(.LCPI17_1)
 ; RV32IZFH-NEXT:    flw fa5, %lo(.LCPI17_1)(a1)
 ; RV32IZFH-NEXT:    flt.s a3, fa5, fs0
 ; RV32IZFH-NEXT:    beqz a3, .LBB17_6
 ; RV32IZFH-NEXT:  # %bb.5:
 ; RV32IZFH-NEXT:    addi a2, a4, -1
 ; RV32IZFH-NEXT:  .LBB17_6:
 ; RV32IZFH-NEXT:    feq.s a1, fs0, fs0
 ; RV32IZFH-NEXT:    neg a4, a1
 ; RV32IZFH-NEXT:    and a1, a4, a2
-; RV32IZFH-NEXT:    neg a2, s0
-; RV32IZFH-NEXT:    and a0, a2, a0
+; RV32IZFH-NEXT:    addi s0, s0, -1
+; RV32IZFH-NEXT:    and a0, s0, a0
 ; RV32IZFH-NEXT:    neg a2, a3
 ; RV32IZFH-NEXT:    or a0, a2, a0
 ; RV32IZFH-NEXT:    and a0, a4, a0
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_roundeven_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rne
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IZHINX-LABEL: test_roundeven_si64:
 ; RV32IZHINX:       # %bb.0:
 ; RV32IZHINX-NEXT:    addi sp, sp, -16
 ; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI17_0)
 ; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI17_0)(a1)
 ; RV32IZHINX-NEXT:    fabs.h a2, a0
 ; RV32IZHINX-NEXT:    flt.h a1, a2, a1
 ; RV32IZHINX-NEXT:    beqz a1, .LBB17_2
 ; RV32IZHINX-NEXT:  # %bb.1:
 ; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rne
 ; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rne
 ; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
 ; RV32IZHINX-NEXT:  .LBB17_2:
 ; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINX-NEXT:    lui a0, 913408
-; RV32IZHINX-NEXT:    fle.s s1, a0, s0
-; RV32IZHINX-NEXT:    neg s2, s1
 ; RV32IZHINX-NEXT:    mv a0, s0
 ; RV32IZHINX-NEXT:    call __fixsfdi@plt
-; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI17_1)
-; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI17_1)(a2)
-; RV32IZHINX-NEXT:    and a0, s2, a0
-; RV32IZHINX-NEXT:    flt.s a4, a2, s0
+; RV32IZHINX-NEXT:    lui a2, 913408
+; RV32IZHINX-NEXT:    lui a3, %hi(.LCPI17_1)
+; RV32IZHINX-NEXT:    lw a3, %lo(.LCPI17_1)(a3)
+; RV32IZHINX-NEXT:    flt.s a6, s0, a2
+; RV32IZHINX-NEXT:    addi a2, a6, -1
+; RV32IZHINX-NEXT:    and a0, a2, a0
+; RV32IZHINX-NEXT:    flt.s a4, a3, s0
 ; RV32IZHINX-NEXT:    neg a2, a4
 ; RV32IZHINX-NEXT:    or a0, a2, a0
 ; RV32IZHINX-NEXT:    feq.s a2, s0, s0
 ; RV32IZHINX-NEXT:    neg a2, a2
 ; RV32IZHINX-NEXT:    lui a5, 524288
 ; RV32IZHINX-NEXT:    lui a3, 524288
-; RV32IZHINX-NEXT:    beqz s1, .LBB17_4
+; RV32IZHINX-NEXT:    bnez a6, .LBB17_4
 ; RV32IZHINX-NEXT:  # %bb.3:
 ; RV32IZHINX-NEXT:    mv a3, a1
 ; RV32IZHINX-NEXT:  .LBB17_4:
 ; RV32IZHINX-NEXT:    and a0, a2, a0
 ; RV32IZHINX-NEXT:    beqz a4, .LBB17_6
 ; RV32IZHINX-NEXT:  # %bb.5:
 ; RV32IZHINX-NEXT:    addi a3, a5, -1
 ; RV32IZHINX-NEXT:  .LBB17_6:
 ; RV32IZHINX-NEXT:    and a1, a2, a3
 ; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    addi sp, sp, 16
 ; RV32IZHINX-NEXT:    ret
 ;
 ; RV64IZHINX-LABEL: test_roundeven_si64:
 ; RV64IZHINX:       # %bb.0:
 ; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI17_0)
 ; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI17_0)(a1)
 ; RV64IZHINX-NEXT:    fabs.h a2, a0

 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, fa5
 ; RV32IZFHMIN-NEXT:    lui a0, 913408
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa5, a0
-; RV32IZFHMIN-NEXT:    fle.s s0, fa5, fs0
+; RV32IZFHMIN-NEXT:    flt.s s0, fs0, fa5
 ; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
 ; RV32IZFHMIN-NEXT:    call __fixsfdi@plt
 ; RV32IZFHMIN-NEXT:    lui a4, 524288
 ; RV32IZFHMIN-NEXT:    lui a2, 524288
-; RV32IZFHMIN-NEXT:    beqz s0, .LBB17_4
+; RV32IZFHMIN-NEXT:    bnez s0, .LBB17_4
 ; RV32IZFHMIN-NEXT:  # %bb.3:
 ; RV32IZFHMIN-NEXT:    mv a2, a1
 ; RV32IZFHMIN-NEXT:  .LBB17_4:
 ; RV32IZFHMIN-NEXT:    lui a1, %hi(.LCPI17_0)
 ; RV32IZFHMIN-NEXT:    flw fa5, %lo(.LCPI17_0)(a1)
 ; RV32IZFHMIN-NEXT:    flt.s a3, fa5, fs0
 ; RV32IZFHMIN-NEXT:    beqz a3, .LBB17_6
 ; RV32IZFHMIN-NEXT:  # %bb.5:
 ; RV32IZFHMIN-NEXT:    addi a2, a4, -1
 ; RV32IZFHMIN-NEXT:  .LBB17_6:
 ; RV32IZFHMIN-NEXT:    feq.s a1, fs0, fs0
 ; RV32IZFHMIN-NEXT:    neg a4, a1
 ; RV32IZFHMIN-NEXT:    and a1, a4, a2
-; RV32IZFHMIN-NEXT:    neg a2, s0
-; RV32IZFHMIN-NEXT:    and a0, a2, a0
+; RV32IZFHMIN-NEXT:    addi s0, s0, -1
+; RV32IZFHMIN-NEXT:    and a0, s0, a0
 ; RV32IZFHMIN-NEXT:    neg a2, a3
 ; RV32IZFHMIN-NEXT:    or a0, a2, a0
 ; RV32IZFHMIN-NEXT:    and a0, a4, a0
 ; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32IZFHMIN-NEXT:    ret

 ; RV32IZHINXMIN-NEXT:  # %bb.1:
 ; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
 ; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
 ; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
 ; RV32IZHINXMIN-NEXT:  .LBB17_2:
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
 ; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
 ; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINXMIN-NEXT:    lui a0, 913408
-; RV32IZHINXMIN-NEXT:    fle.s s1, a0, s0
-; RV32IZHINXMIN-NEXT:    neg s2, s1
 ; RV32IZHINXMIN-NEXT:    mv a0, s0
 ; RV32IZHINXMIN-NEXT:    call __fixsfdi@plt
-; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI17_0)
-; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI17_0)(a2)
-; RV32IZHINXMIN-NEXT:    and a0, s2, a0
-; RV32IZHINXMIN-NEXT:    flt.s a4, a2, s0
+; RV32IZHINXMIN-NEXT:    lui a2, 913408
+; RV32IZHINXMIN-NEXT:    lui a3, %hi(.LCPI17_0)
+; RV32IZHINXMIN-NEXT:    lw a3, %lo(.LCPI17_0)(a3)
+; RV32IZHINXMIN-NEXT:    flt.s a6, s0, a2
+; RV32IZHINXMIN-NEXT:    addi a2, a6, -1
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a4, a3, s0
 ; RV32IZHINXMIN-NEXT:    neg a2, a4
 ; RV32IZHINXMIN-NEXT:    or a0, a2, a0
 ; RV32IZHINXMIN-NEXT:    feq.s a2, s0, s0
 ; RV32IZHINXMIN-NEXT:    neg a2, a2
 ; RV32IZHINXMIN-NEXT:    lui a5, 524288
 ; RV32IZHINXMIN-NEXT:    lui a3, 524288
-; RV32IZHINXMIN-NEXT:    beqz s1, .LBB17_4
-; RV32IZHINXMIN-NEXT:  # %bb.3:
-; RV32IZHINXMIN-NEXT:    mv a3, a1
-; RV32IZHINXMIN-NEXT:  .LBB17_4:
-; RV32IZHINXMIN-NEXT:    and a0, a2, a0
 ; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
-; RV32IZHINXMIN-NEXT:    beqz a4, .LBB17_6
-; RV32IZHINXMIN-NEXT:  # %bb.5:
-; RV32IZHINXMIN-NEXT:    addi a3, a5, -1
+; RV32IZHINXMIN-NEXT:    beqz a6, .LBB17_5
+; RV32IZHINXMIN-NEXT:  # %bb.3:
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    bnez a4, .LBB17_6
+; RV32IZHINXMIN-NEXT:  .LBB17_4:
+; RV32IZHINXMIN-NEXT:    and a1, a2, a3
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB17_5:
+; RV32IZHINXMIN-NEXT:    mv a3, a1
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    beqz a4, .LBB17_4
 ; RV32IZHINXMIN-NEXT:  .LBB17_6:
+; RV32IZHINXMIN-NEXT:    addi a3, a5, -1
 ; RV32IZHINXMIN-NEXT:    and a1, a2, a3
 ; RV32IZHINXMIN-NEXT:    ret
 ;
 ; RV64IZHINXMIN-LABEL: test_roundeven_si64:
 ; RV64IZHINXMIN:       # %bb.0:
 ; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
 ; RV64IZHINXMIN-NEXT:    lui a1, 307200
 ; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
; RV64IZHINXMIN-NEXT:    ret
   ret i32 %b
 }
 
 define i64 @test_roundeven_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_roundeven_ui64:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFH-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFH-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI19_0)
 ; RV32IZFH-NEXT:    flh fa5, %lo(.LCPI19_0)(a0)
 ; RV32IZFH-NEXT:    fabs.h fa4, fa0
 ; RV32IZFH-NEXT:    flt.h a0, fa4, fa5
 ; RV32IZFH-NEXT:    beqz a0, .LBB19_2
 ; RV32IZFH-NEXT:  # %bb.1:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rne
 ; RV32IZFH-NEXT:    fcvt.h.w fa5, a0, rne
 ; RV32IZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; RV32IZFH-NEXT:  .LBB19_2:
 ; RV32IZFH-NEXT:    fcvt.s.h fs0, fa0
-; RV32IZFH-NEXT:    fmv.w.x fa5, zero
-; RV32IZFH-NEXT:    fle.s a0, fa5, fs0
-; RV32IZFH-NEXT:    neg s0, a0
 ; RV32IZFH-NEXT:    fmv.s fa0, fs0
 ; RV32IZFH-NEXT:    call __fixunssfdi@plt
+; RV32IZFH-NEXT:    fmv.w.x fa5, zero
 ; RV32IZFH-NEXT:    lui a2, %hi(.LCPI19_1)
-; RV32IZFH-NEXT:    flw fa5, %lo(.LCPI19_1)(a2)
-; RV32IZFH-NEXT:    and a0, s0, a0
-; RV32IZFH-NEXT:    flt.s a2, fa5, fs0
-; RV32IZFH-NEXT:    neg a2, a2
-; RV32IZFH-NEXT:    or a0, a2, a0
-; RV32IZFH-NEXT:    and a1, s0, a1
-; RV32IZFH-NEXT:    or a1, a2, a1
+; RV32IZFH-NEXT:    flw fa4, %lo(.LCPI19_1)(a2)
+; RV32IZFH-NEXT:    flt.s a2, fs0, fa5
+; RV32IZFH-NEXT:    addi a2, a2, -1
+; RV32IZFH-NEXT:    and a0, a2, a0
+; RV32IZFH-NEXT:    flt.s a3, fa4, fs0
+; RV32IZFH-NEXT:    neg a3, a3
+; RV32IZFH-NEXT:    or a0, a3, a0
+; RV32IZFH-NEXT:    and a1, a2, a1
+; RV32IZFH-NEXT:    or a1, a3, a1
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFH-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_roundeven_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rne
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IZHINX-LABEL: test_roundeven_ui64:
 ; RV32IZHINX:       # %bb.0:
 ; RV32IZHINX-NEXT:    addi sp, sp, -16
 ; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI19_0)
 ; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI19_0)(a1)
 ; RV32IZHINX-NEXT:    fabs.h a2, a0
 ; RV32IZHINX-NEXT:    flt.h a1, a2, a1
 ; RV32IZHINX-NEXT:    beqz a1, .LBB19_2
 ; RV32IZHINX-NEXT:  # %bb.1:
 ; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rne
 ; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rne
 ; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
 ; RV32IZHINX-NEXT:  .LBB19_2:
 ; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINX-NEXT:    fle.s a0, zero, s0
-; RV32IZHINX-NEXT:    neg s1, a0
 ; RV32IZHINX-NEXT:    mv a0, s0
 ; RV32IZHINX-NEXT:    call __fixunssfdi@plt
 ; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI19_1)
 ; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI19_1)(a2)
-; RV32IZHINX-NEXT:    and a0, s1, a0
+; RV32IZHINX-NEXT:    flt.s a3, s0, zero
+; RV32IZHINX-NEXT:    addi a3, a3, -1
+; RV32IZHINX-NEXT:    and a0, a3, a0
 ; RV32IZHINX-NEXT:    flt.s a2, a2, s0
 ; RV32IZHINX-NEXT:    neg a2, a2
 ; RV32IZHINX-NEXT:    or a0, a2, a0
-; RV32IZHINX-NEXT:    and a1, s1, a1
+; RV32IZHINX-NEXT:    and a1, a3, a1
 ; RV32IZHINX-NEXT:    or a1, a2, a1
 ; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZHINX-NEXT:    addi sp, sp, 16
 ; RV32IZHINX-NEXT:    ret
 ;
 ; RV64IZHINX-LABEL: test_roundeven_ui64:
 ; RV64IZHINX:       # %bb.0:
 ; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI19_0)
 ; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI19_0)(a1)
 ; RV64IZHINX-NEXT:    fabs.h a2, a0

 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB19_2
 ; RV32IZFHMIN-NEXT:  # %bb.1:
 ; RV32IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rne
 ; RV32IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rne
 ; RV32IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV32IZFHMIN-NEXT:  .LBB19_2:
 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZFHMIN-NEXT:    fsw fs0, 4(sp) # 4-byte Folded Spill
+; RV32IZFHMIN-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fs0, fa5
-; RV32IZFHMIN-NEXT:    fmv.w.x fa5, zero
-; RV32IZFHMIN-NEXT:    fle.s a0, fa5, fs0
-; RV32IZFHMIN-NEXT:    neg s0, a0
 ; RV32IZFHMIN-NEXT:    fmv.s fa0, fs0
 ; RV32IZFHMIN-NEXT:    call __fixunssfdi@plt
+; RV32IZFHMIN-NEXT:    fmv.w.x fa5, zero
 ; RV32IZFHMIN-NEXT:    lui a2, %hi(.LCPI19_0)
-; RV32IZFHMIN-NEXT:    flw fa5, %lo(.LCPI19_0)(a2)
-; RV32IZFHMIN-NEXT:    and a0, s0, a0
-; RV32IZFHMIN-NEXT:    flt.s a2, fa5, fs0
-; RV32IZFHMIN-NEXT:    neg a2, a2
-; RV32IZFHMIN-NEXT:    or a0, a2, a0
-; RV32IZFHMIN-NEXT:    and a1, s0, a1
-; RV32IZFHMIN-NEXT:    or a1, a2, a1
+; RV32IZFHMIN-NEXT:    flw fa4, %lo(.LCPI19_0)(a2)
+; RV32IZFHMIN-NEXT:    flt.s a2, fs0, fa5
+; RV32IZFHMIN-NEXT:    addi a2, a2, -1
+; RV32IZFHMIN-NEXT:    and a0, a2, a0
+; RV32IZFHMIN-NEXT:    flt.s a3, fa4, fs0
+; RV32IZFHMIN-NEXT:    neg a3, a3
+; RV32IZFHMIN-NEXT:    or a0, a3, a0
+; RV32IZFHMIN-NEXT:    and a1, a2, a1
+; RV32IZFHMIN-NEXT:    or a1, a3, a1
 ; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
+; RV32IZFHMIN-NEXT:    flw fs0, 8(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32IZFHMIN-NEXT:    ret
 ;
 ; RV64IZFHMIN-LABEL: test_roundeven_ui64:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    lui a0, 307200
 ; RV64IZFHMIN-NEXT:    fmv.w.x fa4, a0

 ; RV32IZHINXMIN-NEXT:  # %bb.1:
 ; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
 ; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
 ; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
 ; RV32IZHINXMIN-NEXT:  .LBB19_2:
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
 ; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
-; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
 ; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
-; RV32IZHINXMIN-NEXT:    fle.s a0, zero, s0
-; RV32IZHINXMIN-NEXT:    neg s1, a0
 ; RV32IZHINXMIN-NEXT:    mv a0, s0
 ; RV32IZHINXMIN-NEXT:    call __fixunssfdi@plt
 ; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI19_0)
 ; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI19_0)(a2)
-; RV32IZHINXMIN-NEXT:    and a0, s1, a0
+; RV32IZHINXMIN-NEXT:    flt.s a3, s0, zero
+; RV32IZHINXMIN-NEXT:    addi a3, a3, -1
+; RV32IZHINXMIN-NEXT:    and a0, a3, a0
 ; RV32IZHINXMIN-NEXT:    flt.s a2, a2, s0
 ; RV32IZHINXMIN-NEXT:    neg a2, a2
 ; RV32IZHINXMIN-NEXT:    or a0, a2, a0
-; RV32IZHINXMIN-NEXT:    and a1, s1, a1
+; RV32IZHINXMIN-NEXT:    and a1, a3, a1
 ; RV32IZHINXMIN-NEXT:    or a1, a2, a1
 ; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
-; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
 ; RV32IZHINXMIN-NEXT:    ret
 ;
 ; RV64IZHINXMIN-LABEL: test_roundeven_ui64:
 ; RV64IZHINXMIN:       # %bb.0:
 ; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
 ; RV64IZHINXMIN-NEXT:    lui a1, 307200
 ; RV64IZHINXMIN-NEXT:    fabs.s a2, a0

llvm/test/CodeGen/RISCV/half-select-fcmp.ll

; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp ueq half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ugt(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ugt:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fle.h a0, fa0, fa1
-; CHECK-NEXT:    beqz a0, .LBB9_2
+; CHECK-NEXT:    flt.h a0, fa1, fa0
+; CHECK-NEXT:    bnez a0, .LBB9_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB9_2:
 ; CHECK-NEXT:    ret
 ;
 ; CHECKIZHINX-LABEL: select_fcmp_ugt:
 ; CHECKIZHINX:       # %bb.0:
-; CHECKIZHINX-NEXT:    fle.h a2, a0, a1
-; CHECKIZHINX-NEXT:    beqz a2, .LBB9_2
+; CHECKIZHINX-NEXT:    flt.h a2, a1, a0
+; CHECKIZHINX-NEXT:    bnez a2, .LBB9_2
 ; CHECKIZHINX-NEXT:  # %bb.1:
 ; CHECKIZHINX-NEXT:    mv a0, a1
 ; CHECKIZHINX-NEXT:  .LBB9_2:
 ; CHECKIZHINX-NEXT:    ret
 ;
 ; CHECKIZFHMIN-LABEL: select_fcmp_ugt:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp ugt half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_uge(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    flt.h a0, fa0, fa1
-; CHECK-NEXT:    beqz a0, .LBB10_2
+; CHECK-NEXT:    fle.h a0, fa1, fa0
+; CHECK-NEXT:    bnez a0, .LBB10_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB10_2:
 ; CHECK-NEXT:    ret
 ;
 ; CHECKIZHINX-LABEL: select_fcmp_uge:
 ; CHECKIZHINX:       # %bb.0:
-; CHECKIZHINX-NEXT:    flt.h a2, a0, a1
-; CHECKIZHINX-NEXT:    beqz a2, .LBB10_2
+; CHECKIZHINX-NEXT:    fle.h a2, a1, a0
+; CHECKIZHINX-NEXT:    bnez a2, .LBB10_2
 ; CHECKIZHINX-NEXT:  # %bb.1:
 ; CHECKIZHINX-NEXT:    mv a0, a1
 ; CHECKIZHINX-NEXT:  .LBB10_2:
 ; CHECKIZHINX-NEXT:    ret
 ;
 ; CHECKIZFHMIN-LABEL: select_fcmp_uge:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp uge half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ult(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ult:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fle.h a0, fa1, fa0
-; CHECK-NEXT:    beqz a0, .LBB11_2
+; CHECK-NEXT:    flt.h a0, fa0, fa1
+; CHECK-NEXT:    bnez a0, .LBB11_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB11_2:
 ; CHECK-NEXT:    ret
 ;
 ; CHECKIZHINX-LABEL: select_fcmp_ult:
 ; CHECKIZHINX:       # %bb.0:
-; CHECKIZHINX-NEXT:    fle.h a2, a1, a0
-; CHECKIZHINX-NEXT:    beqz a2, .LBB11_2
+; CHECKIZHINX-NEXT:    flt.h a2, a0, a1
+; CHECKIZHINX-NEXT:    bnez a2, .LBB11_2
 ; CHECKIZHINX-NEXT:  # %bb.1:
 ; CHECKIZHINX-NEXT:    mv a0, a1
 ; CHECKIZHINX-NEXT:  .LBB11_2:
 ; CHECKIZHINX-NEXT:    ret
 ;
 ; CHECKIZFHMIN-LABEL: select_fcmp_ult:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp ult half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ule(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ule:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    flt.h a0, fa1, fa0
-; CHECK-NEXT:    beqz a0, .LBB12_2
+; CHECK-NEXT:    fle.h a0, fa0, fa1
+; CHECK-NEXT:    bnez a0, .LBB12_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB12_2:
 ; CHECK-NEXT:    ret
 ;
 ; CHECKIZHINX-LABEL: select_fcmp_ule:
 ; CHECKIZHINX:       # %bb.0:
-; CHECKIZHINX-NEXT:    flt.h a2, a1, a0
-; CHECKIZHINX-NEXT:    beqz a2, .LBB12_2
+; CHECKIZHINX-NEXT:    fle.h a2, a0, a1
+; CHECKIZHINX-NEXT:    bnez a2, .LBB12_2
 ; CHECKIZHINX-NEXT:  # %bb.1:
 ; CHECKIZHINX-NEXT:    mv a0, a1
 ; CHECKIZHINX-NEXT:  .LBB12_2:
 ; CHECKIZHINX-NEXT:    ret
 ;
 ; CHECKIZFHMIN-LABEL: select_fcmp_ule:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp fast oeq half %a, %b
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }
 
 define signext i32 @select_fcmp_uge_negone_zero(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge_negone_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fle.h a0, fa0, fa1
-; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    flt.h a0, fa1, fa0
+; CHECK-NEXT:    neg a0, a0
 ; CHECK-NEXT:    ret
 ;
 ; CHECKIZHINX-LABEL: select_fcmp_uge_negone_zero:
 ; CHECKIZHINX:       # %bb.0:
-; CHECKIZHINX-NEXT:    fle.h a0, a0, a1
-; CHECKIZHINX-NEXT:    addi a0, a0, -1
+; CHECKIZHINX-NEXT:    flt.h a0, a1, a0
+; CHECKIZHINX-NEXT:    neg a0, a0
 ; CHECKIZHINX-NEXT:    ret
 ;
 ; CHECKIZFHMIN-LABEL: select_fcmp_uge_negone_zero:
 ; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
-; CHECKIZFHMIN-NEXT:    fle.s a0, fa4, fa5
-; CHECKIZFHMIN-NEXT:    addi a0, a0, -1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
+; CHECKIZFHMIN-NEXT:    flt.s a0, fa4, fa5
+; CHECKIZFHMIN-NEXT:    neg a0, a0
 ; CHECKIZFHMIN-NEXT:    ret
 ;
 ; CHECKIZHINXMIN-LABEL: select_fcmp_uge_negone_zero:
 ; CHECKIZHINXMIN:       # %bb.0:
-; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
 ; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
-; CHECKIZHINXMIN-NEXT:    fle.s a0, a0, a1
-; CHECKIZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    flt.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:    neg a0, a0
 ; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp ugt half %a, %b
   %2 = select i1 %1, i32 -1, i32 0
   ret i32 %2
 }
 
 define signext i32 @select_fcmp_uge_1_2(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge_1_2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fle.h a0, fa0, fa1
-; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    flt.h a0, fa1, fa0
+; CHECK-NEXT:    li a1, 2
+; CHECK-NEXT:    sub a0, a1, a0
 ; CHECK-NEXT:    ret
 ;
 ; CHECKIZHINX-LABEL: select_fcmp_uge_1_2:
 ; CHECKIZHINX:       # %bb.0:
-; CHECKIZHINX-NEXT:    fle.h a0, a0, a1
-; CHECKIZHINX-NEXT:    addi a0, a0, 1
+; CHECKIZHINX-NEXT:    flt.h a0, a1, a0
+; CHECKIZHINX-NEXT:    li a1, 2
+; CHECKIZHINX-NEXT:    sub a0, a1, a0
 ; CHECKIZHINX-NEXT:    ret
 ;
 ; CHECKIZFHMIN-LABEL: select_fcmp_uge_1_2:
 ; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
-; CHECKIZFHMIN-NEXT:    fle.s a0, fa4, fa5
-; CHECKIZFHMIN-NEXT:    addi a0, a0, 1
+; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
+; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
+; CHECKIZFHMIN-NEXT:    flt.s a0, fa4, fa5
+; CHECKIZFHMIN-NEXT:    li a1, 2
+; CHECKIZFHMIN-NEXT:    sub a0, a1, a0
 ; CHECKIZFHMIN-NEXT:    ret
 ;
 ; CHECKIZHINXMIN-LABEL: select_fcmp_uge_1_2:
 ; CHECKIZHINXMIN:       # %bb.0:
-; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
 ; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
-; CHECKIZHINXMIN-NEXT:    fle.s a0, a0, a1
-; CHECKIZHINXMIN-NEXT:    addi a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    flt.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:    li a1, 2
+; CHECKIZHINXMIN-NEXT:    sub a0, a1, a0
 ; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp ugt half %a, %b
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/half-select-icmp.ll

; CHECKIZHINXMIN-NEXT:    ret
   %1 = icmp slt i32 %a, 1
   %2 = select i1 %1, half 1.000000e+00, half 0.000000e+00
   ret half %2
 }
 
 define half @select_icmp_sgt_zero(i32 signext %a) {
 ; CHECK-LABEL: select_icmp_sgt_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sgtz a0, a0
-; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    slti a0, a0, 1
 ; CHECK-NEXT:    fcvt.h.w fa0, a0
 ; CHECK-NEXT:    ret
 ;
 ; CHECKIZHINX-LABEL: select_icmp_sgt_zero:
 ; CHECKIZHINX:       # %bb.0:
-; CHECKIZHINX-NEXT:    sgtz a0, a0
-; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    slti a0, a0, 1
 ; CHECKIZHINX-NEXT:    fcvt.h.w a0, a0
 ; CHECKIZHINX-NEXT:    ret
 ;
 ; CHECKIZFHMIN-LABEL: select_icmp_sgt_zero:
 ; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    sgtz a0, a0
-; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    slti a0, a0, 1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa5, a0
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
 ;
 ; CHECKIZHINXMIN-LABEL: select_icmp_sgt_zero:
 ; CHECKIZHINXMIN:       # %bb.0:
-; CHECKIZHINXMIN-NEXT:    sgtz a0, a0
-; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    slti a0, a0, 1
 ; CHECKIZHINXMIN-NEXT:    fcvt.s.w a0, a0
 ; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
 ; CHECKIZHINXMIN-NEXT:    ret
   %1 = icmp sgt i32 %a, 0
   %2 = select i1 %1, half 0.000000e+00, half 1.000000e+00
   ret half %2
 }
 

llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll

 ; CHECK-RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; CHECK-RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; CHECK-RV64I-NEXT:    ld s2, 0(sp) # 8-byte Folded Reload
 ; CHECK-RV64I-NEXT:    addi sp, sp, 32
 ; CHECK-RV64I-NEXT:    ret
 ;
 ; CHECK-RV64IF-LABEL: flo:
 ; CHECK-RV64IF:       # %bb.0:
-; CHECK-RV64IF-NEXT:    fle.s a0, fa0, fa1
-; CHECK-RV64IF-NEXT:    fle.s a1, fa0, fa2
-; CHECK-RV64IF-NEXT:    and a0, a0, a1
-; CHECK-RV64IF-NEXT:    xori a0, a0, 1
+; CHECK-RV64IF-NEXT:    flt.s a0, fa1, fa0
+; CHECK-RV64IF-NEXT:    flt.s a1, fa2, fa0
+; CHECK-RV64IF-NEXT:    or a0, a0, a1
 ; CHECK-RV64IF-NEXT:    ret
   %l0 = fcmp ult float %a, %c
   %l1 = fcmp ult float %b, %c
   %res = or i1 %l0, %l1
   ret i1 %res
 }
 
 ; Negative test