[RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)

[liaolucy]

Summary

Improve D151719.
(xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
https://alive2.llvm.org/ce/z/BZNEia

[liaolucy]

Update, add hasOneUse()

[liaolucy]

[RISCV]Fold xor(setcc x, y, cond), 1 --> setcc (x, y, inverted(cond))

[liaolucy]

revert the last commit.sorry

[liaolucy]

[RISCV]Fold xor(setcc x, y, cond), 1 --> setcc (x, y, inverted(cond))

[liaolucy]

revert the last commit.

I tried to set the related parent but it always failed, gave up for now.
I'll post next patch later. (Fold xor(setcc x, y, cond), 1 --> setcc (x, y, inverted(cond)))

I'm sorry to bother you all.

[liaolucy]

Rebase and remove two temporary variables, clearer now.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

10484

Use APInt methods here. I don't think we're protected against types being larger than i64 here. So getSExtValue() might assert.

10485

Imm+1 is undefined behavior if Imm happens to be INT64_MAX. Another reason to use APInt.

[liaolucy]

address comments, use APInt methods, thanks.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
   if (N0.getOpcode() == RISCVISD::SLLW &&
       isAllOnesConstant(N1) && isOneConstant(N0.getOperand(0)) &&
       TLI.isOperationLegal(ISD::ROTL, MVT::i64)) {
     SDLoc DL(N);
     return DAG.getNode(RISCVISD::ROLW, DL, MVT::i64,
                        DAG.getConstant(~1, DL, MVT::i64), N0.getOperand(1));
   }
 
+  // Fold (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
+  if (N0.hasOneUse() && N0.getOpcode() == ISD::SETCC && isOneConstant(N1)) {
+    auto *ConstN00 = dyn_cast<ConstantSDNode>(N0.getOperand(0));
+    ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
+    if (ConstN00 && CC == ISD::SETLT) {
+      EVT VT = N0.getValueType();
+      SDLoc DL(N0);
+      const APInt &Imm = ConstN00->getAPIntValue();
+      if ((Imm + 1).isSignedIntN(12))
+        return DAG.getSetCC(DL, VT, N0.getOperand(1),
+                            DAG.getConstant(Imm + 1, DL, VT), CC);
+    }
+  }
+
   if (SDValue V = combineBinOpToReduce(N, DAG, Subtarget))
     return V;
   // fold (xor (select cond, 0, y), x) ->
   //      (select cond, x, (xor x, y))
   return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false, Subtarget);
 }
 
 // Replace (seteq (i64 (and X, 0xffffffff)), C1) with

llvm/test/CodeGen/RISCV/double-select-icmp.ll

; RV64ZDINX-NEXT:    ret
   %1 = icmp slt i32 %a, 1
   %2 = select i1 %1, double 1.000000e+00, double 0.000000e+00
   ret double %2
 }
 
 define double @select_icmp_sgt_zero(i32 signext %a) {
 ; CHECK-LABEL: select_icmp_sgt_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sgtz a0, a0
-; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    slti a0, a0, 1
 ; CHECK-NEXT:    fcvt.d.w fa0, a0
 ; CHECK-NEXT:    ret
 ;
 ; RV32ZDINX-LABEL: select_icmp_sgt_zero:
 ; RV32ZDINX:       # %bb.0:
 ; RV32ZDINX-NEXT:    addi sp, sp, -16
 ; RV32ZDINX-NEXT:    .cfi_def_cfa_offset 16
-; RV32ZDINX-NEXT:    sgtz a0, a0
-; RV32ZDINX-NEXT:    xori a0, a0, 1
+; RV32ZDINX-NEXT:    slti a0, a0, 1
 ; RV32ZDINX-NEXT:    fcvt.d.w a0, a0
 ; RV32ZDINX-NEXT:    sw a0, 8(sp)
 ; RV32ZDINX-NEXT:    sw a1, 12(sp)
 ; RV32ZDINX-NEXT:    lw a0, 8(sp)
 ; RV32ZDINX-NEXT:    lw a1, 12(sp)
 ; RV32ZDINX-NEXT:    addi sp, sp, 16
 ; RV32ZDINX-NEXT:    ret
 ;
 ; RV64ZDINX-LABEL: select_icmp_sgt_zero:
 ; RV64ZDINX:       # %bb.0:
-; RV64ZDINX-NEXT:    sgtz a0, a0
-; RV64ZDINX-NEXT:    xori a0, a0, 1
+; RV64ZDINX-NEXT:    slti a0, a0, 1
 ; RV64ZDINX-NEXT:    fcvt.d.w a0, a0
 ; RV64ZDINX-NEXT:    ret
   %1 = icmp sgt i32 %a, 0
   %2 = select i1 %1, double 0.000000e+00, double 1.000000e+00
   ret double %2
 }
 

llvm/test/CodeGen/RISCV/float-select-icmp.ll

; CHECKZFINX-NEXT:    ret
   %1 = icmp slt i32 %a, 1
   %2 = select i1 %1, float 1.000000e+00, float 0.000000e+00
   ret float %2
 }
 
 define float @select_icmp_sgt_zero(i32 signext %a) {
 ; CHECK-LABEL: select_icmp_sgt_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sgtz a0, a0
-; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    slti a0, a0, 1
 ; CHECK-NEXT:    fcvt.s.w fa0, a0
 ; CHECK-NEXT:    ret
 ;
 ; CHECKZFINX-LABEL: select_icmp_sgt_zero:
 ; CHECKZFINX:       # %bb.0:
-; CHECKZFINX-NEXT:    sgtz a0, a0
-; CHECKZFINX-NEXT:    xori a0, a0, 1
+; CHECKZFINX-NEXT:    slti a0, a0, 1
 ; CHECKZFINX-NEXT:    fcvt.s.w a0, a0
 ; CHECKZFINX-NEXT:    ret
   %1 = icmp sgt i32 %a, 0
   %2 = select i1 %1, float 0.000000e+00, float 1.000000e+00
   ret float %2
 }

llvm/test/CodeGen/RISCV/half-select-icmp.ll

; CHECKIZHINXMIN-NEXT:    ret
   %1 = icmp slt i32 %a, 1
   %2 = select i1 %1, half 1.000000e+00, half 0.000000e+00
   ret half %2
 }
 
 define half @select_icmp_sgt_zero(i32 signext %a) {
 ; CHECK-LABEL: select_icmp_sgt_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sgtz a0, a0
-; CHECK-NEXT:    xori a0, a0, 1
+; CHECK-NEXT:    slti a0, a0, 1
 ; CHECK-NEXT:    fcvt.h.w fa0, a0
 ; CHECK-NEXT:    ret
 ;
 ; CHECKIZHINX-LABEL: select_icmp_sgt_zero:
 ; CHECKIZHINX:       # %bb.0:
-; CHECKIZHINX-NEXT:    sgtz a0, a0
-; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    slti a0, a0, 1
 ; CHECKIZHINX-NEXT:    fcvt.h.w a0, a0
 ; CHECKIZHINX-NEXT:    ret
 ;
 ; CHECKIZFHMIN-LABEL: select_icmp_sgt_zero:
 ; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    sgtz a0, a0
-; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
+; CHECKIZFHMIN-NEXT:    slti a0, a0, 1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa5, a0
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
 ;
 ; CHECKIZHINXMIN-LABEL: select_icmp_sgt_zero:
 ; CHECKIZHINXMIN:       # %bb.0:
-; CHECKIZHINXMIN-NEXT:    sgtz a0, a0
-; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    slti a0, a0, 1
 ; CHECKIZHINXMIN-NEXT:    fcvt.s.w a0, a0
 ; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
 ; CHECKIZHINXMIN-NEXT:    ret
   %1 = icmp sgt i32 %a, 0
   %2 = select i1 %1, half 0.000000e+00, half 1.000000e+00
   ret half %2
 }