[RISCV] Avoid illegal DAG combination for strict-fp nodes.

[fakepaper56]

Summary

Those combines may change the exception behavior and rounding behavior.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

static SDValue performFP_TO_INTCombine(SDNode *N,
                                        TargetLowering::DAGCombinerInfo &DCI,
                                        const RISCVSubtarget &Subtarget) {
   SelectionDAG &DAG = DCI.DAG;
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   MVT XLenVT = Subtarget.getXLenVT();
 
   SDValue Src = N->getOperand(0);
 
+  // Don't do this for strict-fp Src.
+  if (Src->isStrictFPOpcode() || Src->isTargetStrictFPOpcode())
+    return SDValue();
+
   // Ensure the FP type is legal.
   if (!TLI.isTypeLegal(Src.getValueType()))
     return SDValue();
 
   // Don't do this for f16 with Zfhmin and not Zfh.
   if (Src.getValueType() == MVT::f16 && !Subtarget.hasStdExtZfh())
     return SDValue();
 
static SDValue performFP_TO_INT_SATCombine(SDNode *N,
   // Only handle XLen types. Other types narrower than XLen will eventually be
   // legalized to XLenVT.
   EVT DstVT = N->getValueType(0);
   if (DstVT != XLenVT)
     return SDValue();
 
   SDValue Src = N->getOperand(0);
 
+  // Don't do this for strict-fp Src.
+  if (Src->isStrictFPOpcode() || Src->isTargetStrictFPOpcode())
+    return SDValue();
+
   // Ensure the FP type is also legal.
   if (!TLI.isTypeLegal(Src.getValueType()))
     return SDValue();
 
   // Don't do this for f16 with Zfhmin and not Zfh.
   if (Src.getValueType() == MVT::f16 && !Subtarget.hasStdExtZfh())
     return SDValue();