[RISCV] Add special case for (select cc, 1.0, 0.0) to lowerSELECT

[liaolucy]

Summary

Use sint_to_fp instead of select.
Reduce the number of branch instructions and
avoid generating TargetConstantPool for double.

(select cc, 1.0, 0.0) -> (sint_to_fp (zext cc))
https://alive2.llvm.org/ce/z/aoEcd9
https://godbolt.org/z/n543Y9v3e

(select cc, 0.0, 1.0) -> (sint_to_fp (zext (xor cc, 1)))
https://alive2.llvm.org/ce/z/zngvSB

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

5565

Why does the condition code matter? Isn't this equally valid for any condition code?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

5565

Or rather, why do the operands to the setcc matter? If you the select true/false are 1.0 and 0.0 you can replace the select with a sint_to_fp regardless of what the condition is.

[liaolucy]

If the select true/false are 1.0 and 0.0 we can replace the select with a sint_to_fp.
(select cc, 1.0, 0.0) -> (sint_to_fp (zext cc))
https://alive2.llvm.org/ce/z/aoEcd9
thanks

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

5502

This ZERO_EXTEND shoudn't be needed. The condition must be a legal integer type so it could only be XLenVT.

[liaolucy]

Deleted two ZERO_EXTEND.
The second ZERO_EXTEND should not be needed either. Setcc and zext are all XLenVT.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

5501

Drop curly braces

5566

Why not handle this like the earlier, but use an XOR with 1 to flip the condition? Wouldn't that always better than the branch?

[liaolucy]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

5566

The select true/false are 0.0 and 1.0 (not 1.0 and 0.0) we can not replace the select with a sint_to_fp.
https://alive2.llvm.org/ce/z/L32zaJ
I didn't find an easier replacement.

[liaolucy]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

5566

Maybe I can change it to perform select and reuse the above code, I'll try it, thanks.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

5566

https://alive2.llvm.org/ce/z/zngvSB

[liaolucy]

Using xor to replace setcc.
A DAGCombine patch may be needed here. I can send a new patch.

+++ b/llvm/test/CodeGen/RISCV/half-select-icmp.ll
@@ -510,26 +510,30 @@ define half @select_icmp_slt_one(i32 signext %a) {
 define half @select_icmp_sgt_zero(i32 signext %a) {
 ; CHECK-LABEL: select_icmp_sgt_zero:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    slti a0, a0, 1
+; CHECK-NEXT:    sgtz a0, a0
+; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    fcvt.h.w fa0, a0
 ; CHECK-NEXT:    ret

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

5505

No need for else after return.

llvm/test/CodeGen/RISCV/double-select-icmp.ll

510

CHECKZFINX isn't a valid prefix for this file.

llvm/test/CodeGen/RISCV/half-select-icmp.ll

540

CHECKZFINX isn't a valid prefix for this file

[liaolucy]

Address comments. Thanks.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
   }
 
   if (SDValue V = combineSelectToBinOp(Op.getNode(), DAG, Subtarget))
     return V;
 
   // If the condition is not an integer SETCC which operates on XLenVT, we need
   // to emit a RISCVISD::SELECT_CC comparing the condition to zero. i.e.:
   // (select condv, truev, falsev)
   // -> (riscvisd::select_cc condv, zero, setne, truev, falsev)
   if (CondV.getOpcode() != ISD::SETCC ||
       CondV.getOperand(0).getSimpleValueType() != XLenVT) {
     SDValue Zero = DAG.getConstant(0, DL, XLenVT);
     SDValue SetNE = DAG.getCondCode(ISD::SETNE);
 
     SDValue Ops[] = {CondV, Zero, SetNE, TrueV, FalseV};
 
     return DAG.getNode(RISCVISD::SELECT_CC, DL, VT, Ops);
   }
 
   // If the CondV is the output of a SETCC node which operates on XLenVT inputs,
   // then merge the SETCC node into the lowered RISCVISD::SELECT_CC to take
SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
 
   if (isa<ConstantSDNode>(TrueV) && !isa<ConstantSDNode>(FalseV)) {
     // (select (setcc lhs, rhs, CC), constant, falsev)
     // -> (select (setcc lhs, rhs, InverseCC), falsev, constant)
     std::swap(TrueV, FalseV);
     TargetCC = DAG.getCondCode(ISD::getSetCCInverse(CCVal, LHS.getValueType()));
   }
 
+  // (select_cc 0, x, setge, 1.0, 0.0)
+  // -> (sint_to_fp (zext (setcc x, 1, setlt)))
+  // (select_cc 0, x, setlt, 0.0, 1.0)
+  // -> (sint_to_fp (zext (setcc x, 1, setlt)))
+  if (isa<ConstantFPSDNode>(TrueV) && isa<ConstantFPSDNode>(FalseV) &&
+      isNullConstant(LHS) &&
+      (CCVal == ISD::CondCode::SETLT || CCVal == ISD::CondCode::SETGE)) {
+    if (CCVal == ISD::CondCode::SETGE)
+      std::swap(TrueV, FalseV);
+
+    const ConstantFPSDNode *TV = cast<ConstantFPSDNode>(TrueV);
+    const ConstantFPSDNode *FV = cast<ConstantFPSDNode>(FalseV);
+    if (TV->isExactlyValue(0.0) && FV->isExactlyValue(1.0)) {
+      SDValue SETCC =
+          DAG.getSetCC(DL, XLenVT, RHS, DAG.getConstant(1, DL, XLenVT),
+                       ISD::CondCode::SETLT);
+      SDValue ZEXT = DAG.getNode(ISD::ZERO_EXTEND, DL, XLenVT, SETCC);
+      return DAG.getNode(ISD::SINT_TO_FP, DL, VT, ZEXT);
+    }
+
+    if (CCVal == ISD::CondCode::SETGE)
+      std::swap(TrueV, FalseV);
+  }
+
   SDValue Ops[] = {LHS, RHS, TargetCC, TrueV, FalseV};
   return DAG.getNode(RISCVISD::SELECT_CC, DL, VT, Ops);
 }
 
 SDValue RISCVTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
   SDValue CondV = Op.getOperand(1);
   SDLoc DL(Op);
   MVT XLenVT = Subtarget.getXLenVT();

llvm/test/CodeGen/RISCV/double-select-icmp.ll

 ; RV64ZDINX-NEXT:    mv a2, a3
 ; RV64ZDINX-NEXT:  .LBB9_2:
 ; RV64ZDINX-NEXT:    mv a0, a2
 ; RV64ZDINX-NEXT:    ret
   %1 = icmp sle i32 %a, %b
   %2 = select i1 %1, double %c, double %d
   ret double %2
 }
+
+define double @select_icmp_slt_one(i32 signext %a) {
+; CHECK-LABEL: select_icmp_slt_one:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slti a0, a0, 1
+; CHECK-NEXT:    fcvt.d.w fa0, a0
+; CHECK-NEXT:    ret
+;
+; RV32ZDINX-LABEL: select_icmp_slt_one:
+; RV32ZDINX:       # %bb.0:
+; RV32ZDINX-NEXT:    addi sp, sp, -16
+; RV32ZDINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32ZDINX-NEXT:    slti a0, a0, 1
+; RV32ZDINX-NEXT:    fcvt.d.w a0, a0
+; RV32ZDINX-NEXT:    sw a0, 8(sp)
+; RV32ZDINX-NEXT:    sw a1, 12(sp)
+; RV32ZDINX-NEXT:    lw a0, 8(sp)
+; RV32ZDINX-NEXT:    lw a1, 12(sp)
+; RV32ZDINX-NEXT:    addi sp, sp, 16
+; RV32ZDINX-NEXT:    ret
+;
+; RV64ZDINX-LABEL: select_icmp_slt_one:
+; RV64ZDINX:       # %bb.0:
+; RV64ZDINX-NEXT:    slti a0, a0, 1
+; RV64ZDINX-NEXT:    fcvt.d.w a0, a0
+; RV64ZDINX-NEXT:    ret
+  %1 = icmp slt i32 %a, 1
+  %2 = select i1 %1, double 1.000000e+00, double 0.000000e+00
+  ret double %2
+}
+
+define double @select_icmp_sgt_zero(i32 signext %a) {
+; CHECK-LABEL: select_icmp_sgt_zero:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slti a0, a0, 1
+; CHECK-NEXT:    fcvt.d.w fa0, a0
+; CHECK-NEXT:    ret
+;
+; RV32ZDINX-LABEL: select_icmp_sgt_zero:
+; RV32ZDINX:       # %bb.0:
+; RV32ZDINX-NEXT:    addi sp, sp, -16
+; RV32ZDINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32ZDINX-NEXT:    slti a0, a0, 1
+; RV32ZDINX-NEXT:    fcvt.d.w a0, a0
+; RV32ZDINX-NEXT:    sw a0, 8(sp)
+; RV32ZDINX-NEXT:    sw a1, 12(sp)
+; RV32ZDINX-NEXT:    lw a0, 8(sp)
+; RV32ZDINX-NEXT:    lw a1, 12(sp)
+; RV32ZDINX-NEXT:    addi sp, sp, 16
+; RV32ZDINX-NEXT:    ret
+;
+; RV64ZDINX-LABEL: select_icmp_sgt_zero:
+; RV64ZDINX:       # %bb.0:
+; RV64ZDINX-NEXT:    slti a0, a0, 1
+; RV64ZDINX-NEXT:    fcvt.d.w a0, a0
+; RV64ZDINX-NEXT:    ret
+; CHECKZFINX-LABEL: select_icmp_sgt_zero:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    slti a0, a0, 1
+; CHECKZFINX-NEXT:    fcvt.s.w a0, a0
+; CHECKZFINX-NEXT:    ret
+  %1 = icmp sgt i32 %a, 0
+  %2 = select i1 %1, double 0.000000e+00, double 1.000000e+00
+  ret double %2
+}
+

llvm/test/CodeGen/RISCV/float-select-icmp.ll

 ; CHECKZFINX-NEXT:    mv a2, a3
 ; CHECKZFINX-NEXT:  .LBB9_2:
 ; CHECKZFINX-NEXT:    mv a0, a2
 ; CHECKZFINX-NEXT:    ret
   %1 = icmp sle i32 %a, %b
   %2 = select i1 %1, float %c, float %d
   ret float %2
 }
+
+define float @select_icmp_slt_one(i32 signext %a) {
+; CHECK-LABEL: select_icmp_slt_one:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slti a0, a0, 1
+; CHECK-NEXT:    fcvt.s.w fa0, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: select_icmp_slt_one:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    slti a0, a0, 1
+; CHECKZFINX-NEXT:    fcvt.s.w a0, a0
+; CHECKZFINX-NEXT:    ret
+  %1 = icmp slt i32 %a, 1
+  %2 = select i1 %1, float 1.000000e+00, float 0.000000e+00
+  ret float %2
+}
+
+define float @select_icmp_sgt_zero(i32 signext %a) {
+; CHECK-LABEL: select_icmp_sgt_zero:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slti a0, a0, 1
+; CHECK-NEXT:    fcvt.s.w fa0, a0
+; CHECK-NEXT:    ret
+;
+; CHECKZFINX-LABEL: select_icmp_sgt_zero:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    slti a0, a0, 1
+; CHECKZFINX-NEXT:    fcvt.s.w a0, a0
+; CHECKZFINX-NEXT:    ret
+  %1 = icmp sgt i32 %a, 0
+  %2 = select i1 %1, float 0.000000e+00, float 1.000000e+00
+  ret float %2
+}

llvm/test/CodeGen/RISCV/half-select-icmp.ll

 ; CHECKIZHINXMIN-NEXT:  .LBB9_2:
 ; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a2
 ; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
 ; CHECKIZHINXMIN-NEXT:    ret
   %1 = icmp sle i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }
+
+define half @select_icmp_slt_one(i32 signext %a) {
+; CHECK-LABEL: select_icmp_slt_one:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slti a0, a0, 1
+; CHECK-NEXT:    fcvt.h.w fa0, a0
+; CHECK-NEXT:    ret
+;
+; CHECKIZHINX-LABEL: select_icmp_slt_one:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    slti a0, a0, 1
+; CHECKIZHINX-NEXT:    fcvt.h.w a0, a0
+; CHECKIZHINX-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_icmp_slt_one:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    slti a0, a0, 1
+; CHECKIZFHMIN-NEXT:    fcvt.s.w fa5, a0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
+; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: select_icmp_slt_one:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    slti a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
+  %1 = icmp slt i32 %a, 1
+  %2 = select i1 %1, half 1.000000e+00, half 0.000000e+00
+  ret half %2
+}
+
+define half @select_icmp_sgt_zero(i32 signext %a) {
+; CHECK-LABEL: select_icmp_sgt_zero:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slti a0, a0, 1
+; CHECK-NEXT:    fcvt.h.w fa0, a0
+; CHECK-NEXT:    ret
+;
+; CHECKIZHINX-LABEL: select_icmp_sgt_zero:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    slti a0, a0, 1
+; CHECKIZHINX-NEXT:    fcvt.h.w a0, a0
+; CHECKIZHINX-NEXT:    ret
+;
+; CHECKIZFHMIN-LABEL: select_icmp_sgt_zero:
+; CHECKIZFHMIN:       # %bb.0:
+; CHECKIZFHMIN-NEXT:    slti a0, a0, 1
+; CHECKIZFHMIN-NEXT:    fcvt.s.w fa5, a0
+; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
+; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: select_icmp_sgt_zero:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    slti a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
+; CHECKZFINX-LABEL: select_icmp_sgt_zero:
+; CHECKZFINX:       # %bb.0:
+; CHECKZFINX-NEXT:    slti a0, a0, 1
+; CHECKZFINX-NEXT:    fcvt.s.w a0, a0
+; CHECKZFINX-NEXT:    ret
+  %1 = icmp sgt i32 %a, 0
+  %2 = select i1 %1, half 0.000000e+00, half 1.000000e+00
+  ret half %2
+}
+