The RISC-V psABI recently added __bf16 in https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/367.
Now we can enable this new type in clang.
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This test seems to crash in the backend with -march=rv64gc -mabi=lp64d
__bf16 h1(__bf16 a) { return a; }
clang/docs/LanguageExtensions.rst | ||
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807 | RISC-V |
I haven't done any backend support fo bf16 yet. What I want to do in this patch is only to enable __bf16 for clang.
That doesn’t matter. The test I sent crashes, thats not acceptable.
Probably also means the ABI is not being implemented correctly.
That doesn’t matter. The test I sent crashes, thats not acceptable.
Probably also means the ABI is not being implemented correctly.
I have checked the log where it crashes. That's just because there are no corresponding instructions to address bf16 type in instruction selection. Everything is correct before instruction selection.
It created an extending load from bfloat because it tried to return as an f32. That’s not the ABI. It should be in the lower 16 bits of an FP register.
Just like AArch64 and X86, I have updated my implementation by limiting bfloat16 only when Zfbfmin/Zvfbfmin/Zvfbfwma are enabled. Now the compiler can work for bfloat16 programs without crashing.
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | ||
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435 | This needs an llvm/test/CodeGen/RISCV test. |
I feel (IMHO) this is jumping to the endpoint a bit - the usual route for something like this is:
- MC layer support
- LLVM codegen support (and tests!)
- Any needed Clang support
I was hoping to push out some patches related to zfbfmin tests+codegen today but might time-out (if so, I'll return to it tomorrow).
I think the tentative conclusion of https://discourse.llvm.org/t/rfc-c-23-p1467r9-extended-floating-point-types-and-standard-names/70033 is to make __bf16_t an arithmetic type on all targets - I'd recommend keeping an eye on https://reviews.llvm.org/D150913 (and ideally helping to review it), as that's bound to interact with this patch.
clang/test/Sema/vector-decl-crash.c | ||
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0 | Actually, I didn't want to change riscv64 into another target. However, I see someone directly changed x86 into riscv64 when he supported __bf16. |
Have you started the codegen part yet? I have basically tried but it may be a little troublesome since we use FPR16 for both fp16 and bf16. During instruction selection, it will be difficult to match those instructions fp16 and bf16 share.
The ABI information for __bf16 has been approved in RISCV psABI and is to be merged. Now we can enable this new type in clang.
See https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/367
The description seems verbose and inaccurate now. You can say:
The RISC-V psABI recently added __bf16 in https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/367
Since bf16 has been supported in backend, we can now come back to this clang patch. @craig.topper
This test crashes
float foo(__bf16 a, __bf16 b) { return a + b; }
error in backend: Cannot select: t35: f32,ch = load<(dereferenceable load (s16) from %ir.b.addr), anyext from bf16> t49, FrameIndex:i32<1>, undef:i32
clang/docs/LanguageExtensions.rst | ||
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801 | Put this above X86 so that the other X86 comment below stays together. |
RISC-V