[RISCV] MC layer support for SiFive VCIX vendor extension.

[4vtomat]

Summary

Spec: https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf

[4vtomat]

Modify commit message.

[craig.topper]

Please put SiFive in title since that’s the vendor

[craig.topper]

Also needs RISCV

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrFormatsV.td

127 ↗

(On Diff #499348)

Move this to RISCVInstrInfoXsf.td

llvm/lib/Target/RISCV/RISCVInstrInfoXsf.td

102

We need to use DecoderNamespace on these and update RISCVDisassembler to lookup the VCIX table when the extension is enabled. See the other vendor instruction for examples.

[craig.topper]

Please update docs/ReleaseNotes.rst and docs/RISCVUsage.rst

[4vtomat]

Resolve comments by Craig.

[jrtc27]

Normally we use the less cumbersome “MC layer” rather than “assembler and dis-assembler” (which also shouldn’t be hyphenated)

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

123

Please alphabetize above xthead

[4vtomat]

Resolved the comment.

[craig.topper]

@reames @asb can you help review this?

[asb]

I haven't looked through the .td description yet, but left some first comments (all pretty easily addressable and minor).

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2721

The usual LLVM style is to use early returns to reduce indentation. see https://llvm.org/docs/CodingStandards.html#use-early-exits-and-continue-to-simplify-code

Also, we already have unsigned Opcode = Inst.getOpcode(); above, so you can just use that rather than introducing VCIXOpcode.

llvm/lib/Target/RISCV/RISCVFeatures.td

536

Nit: We're not very consistent, but I think overall it's more common we use title case for the description in parentheses.

llvm/lib/Target/RISCV/RISCVInstrInfo.td

1903

Nit: Shouldn't this be RISCVInstrInfoXSf to match the capitalisation you use in the RISCVUsage addition?

llvm/test/MC/RISCV/rvv/xsfvcp-invalid.s

3

We typically have rv32 CHECK lines as well as rv64

llvm/test/MC/RISCV/rvv/xsfvcp.s

10

We typically have rv32 CHECK lines as well as rv64

[4vtomat]

Resolved Alex's comments.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td

117 ↗

(On Diff #506292)

What is the difference between this and CustomSiFiveVCIX?

[4vtomat]

llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td

117 ↗

(On Diff #506292)

CustomSiFiveVCIF inherits RVInstVCFCustom2 and CustomSiFiveVCIX inherits RVInstVCCustom2.

[craig.topper]

LGTM

[asb]

LGTM too.

llvm/docs/RISCVUsage.rst

``XTHeadMemPair``
   LLVM implements `the THeadMemPair (two-GPR memory operations) vendor-defined instructions specified in <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf>`_  by T-HEAD of Alibaba.  Instructions are prefixed with `th.` as described in the specification.
 
 ``XTHeadVdot``
   LLVM implements `version 1.0.0 of the THeadV-family custom instructions specification <https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.0/xthead-2022-12-04-2.2.0.pdf>`_ by T-HEAD of Alibaba.  All instructions are prefixed with `th.` as described in the specification, and the riscv-toolchain-convention document linked above.
 
 ``XVentanaCondOps``
   LLVM implements `version 1.0.0 of the VTx-family custom instructions specification <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf>`_ by Ventana Micro Systems.  All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above.  These instructions are only available for riscv64 at this time.
 
+``XSfvcp``
+  LLVM implements `version 1.0.0 of the SiFive Vector Coprocessor Interface (VCIX) Software Specification <https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf>`_ by SiFive.  All instructions are prefixed with `sf.vc.` as described in the specification, and the riscv-toolchain-convention document linked above.
+
 Specification Documents
 =======================
 For ratified specifications, please refer to the `official RISC-V International
 page <https://riscv.org/technical/specifications/>`_.  Make sure to check the
 `wiki for not yet integrated extensions
 <https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions>`_.
 

llvm/docs/ReleaseNotes.rst

 * vsetvli intrinsics no longer have side effects. They may now be combined,
   moved, deleted, etc. by optimizations.
 * Adds support for the vendor-defined XTHeadBa (address-generation) extension.
 * Adds support for the vendor-defined XTHeadBb (basic bit-manipulation) extension.
 * Adds support for the vendor-defined XTHeadBs (single-bit) extension.
 * Adds support for the vendor-defined XTHeadMac (multiply-accumulate instructions) extension.
 * Added support for the vendor-defined XTHeadMemPair (two-GPR memory operations)
   extension disassembler/assembler.
+* Added support for the vendor-defined Xsfvcp (SiFive VCIX) extension
+  disassembler/assembler.
 * Support for the now-ratified Zawrs extension is no longer experimental.
 
 Changes to the WebAssembly Backend
 ----------------------------------
 
 * ...
 
 Changes to the Windows Target

llvm/lib/Support/RISCVISAInfo.cpp

 //===-- RISCVISAInfo.cpp - RISCV Arch String Parser -------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
static const RISCVSupportedExtension SupportedExtensions[] = {
     // vendor-defined ('X') extensions
     {"xtheadba", RISCVExtensionVersion{1, 0}},
     {"xtheadbb", RISCVExtensionVersion{1, 0}},
     {"xtheadbs", RISCVExtensionVersion{1, 0}},
     {"xtheadmac", RISCVExtensionVersion{1, 0}},
     {"xtheadmempair", RISCVExtensionVersion{1, 0}},
     {"xtheadvdot", RISCVExtensionVersion{1, 0}},
     {"xventanacondops", RISCVExtensionVersion{1, 0}},
+    {"xsfvcp", RISCVExtensionVersion{1, 0}},
 };
 
 static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
     {"zihintntl", RISCVExtensionVersion{0, 2}},
 
     {"zca", RISCVExtensionVersion{1, 0}},
     {"zcb", RISCVExtensionVersion{1, 0}},
     {"zcd", RISCVExtensionVersion{1, 0}},

 static const char *ImpliedExtsZvl256b[] = {"zvl128b"};
 static const char *ImpliedExtsZvl128b[] = {"zvl64b"};
 static const char *ImpliedExtsZvl64b[] = {"zvl32b"};
 static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"};
 static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx",
                                        "zkne", "zknd", "zknh"};
 static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
 static const char *ImpliedExtsZvfh[] = {"zve32f"};
+static const char *ImpliedExtsXsfvcp[] = {"zve32x"};
 static const char *ImpliedExtsXTHeadVdot[] = {"v"};
 static const char *ImpliedExtsZcb[] = {"zca"};
 static const char *ImpliedExtsZfa[] = {"f"};
 
 struct ImpliedExtsEntry {
   StringLiteral Name;
   ArrayRef<const char *> Exts;
 
   bool operator<(const ImpliedExtsEntry &Other) const {
     return Name < Other.Name;
   }
 
   bool operator<(StringRef Other) const { return Name < Other; }
 };
 
 // Note: The table needs to be sorted by name.
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
     {{"v"}, {ImpliedExtsV}},
+    {{"xsfvcp"}, {ImpliedExtsXsfvcp}},
     {{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}},
     {{"zcb"}, {ImpliedExtsZcb}},
     {{"zdinx"}, {ImpliedExtsZdinx}},
     {{"zfa"}, {ImpliedExtsZfa}},
     {{"zfh"}, {ImpliedExtsZfh}},
     {{"zfhmin"}, {ImpliedExtsZfhmin}},
     {{"zhinx"}, {ImpliedExtsZhinx}},
     {{"zhinxmin"}, {ImpliedExtsZhinxmin}},

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

 //===-- RISCVAsmParser.cpp - Parse RISCV assembly to MCInst instructions --===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
template <unsigned N> bool IsUImm() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
     if (!isImm())
       return false;
     bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
     return IsConstantImm && isUInt<N>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isUImm1() { return IsUImm<1>(); }
   bool isUImm2() { return IsUImm<2>(); }
   bool isUImm3() { return IsUImm<3>(); }
   bool isUImm5() { return IsUImm<5>(); }
   bool isUImm7() { return IsUImm<7>(); }
 
   bool isRnumArg() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidUImmLog2XLenNonZero:
     if (isRV64())
       return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 6) - 1);
     return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 5) - 1);
   case Match_InvalidUImmLog2XLenHalf:
     if (isRV64())
       return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1);
+  case Match_InvalidUImm1:
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 1) - 1);
   case Match_InvalidUImm2:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 2) - 1);
   case Match_InvalidUImm2Lsb0:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 2,
                                       "immediate must be one of");
   case Match_InvalidUImm3:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 3) - 1);
   case Match_InvalidUImm5:
if (IsTHeadMemPair32 && Inst.getOperand(4).getImm() != 3) {
     return Error(Loc, "Operand must be constant 4.");
   }
 
   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
   RISCVII::VConstraintType Constraints = RISCVII::getConstraint(MCID.TSFlags);
   if (Constraints == RISCVII::NoConstraint)
     return false;
 
+  unsigned VCIXOpcode = Inst.getOpcode();
+  if (VCIXOpcode == RISCV::VC_V_XVW || VCIXOpcode == RISCV::VC_V_IVW ||
+      VCIXOpcode == RISCV::VC_V_FVW || VCIXOpcode == RISCV::VC_V_VVW) {
+    // Operands Opcode, Dst, uimm, Dst, Rs2, Rs1 for VC_V_XVW.
+    unsigned VCIXDst = Inst.getOperand(0).getReg();
+    SMLoc VCIXDstLoc = Operands[2]->getStartLoc();
+    if (Constraints & RISCVII::VS1Constraint) {
+      unsigned VCIXRs1 = Inst.getOperand(Inst.getNumOperands() - 1).getReg();
+      if (VCIXDst == VCIXRs1)
+        return Error(VCIXDstLoc, "The destination vector register group cannot"
+                                 " overlap the source vector register group.");
+    }
+    if (Constraints & RISCVII::VS2Constraint) {
+      unsigned VCIXRs2 = Inst.getOperand(Inst.getNumOperands() - 2).getReg();
+      if (VCIXDst == VCIXRs2)
+        return Error(VCIXDstLoc, "The destination vector register group cannot"
+                                 " overlap the source vector register group.");
+    }
+  } else {
     unsigned DestReg = Inst.getOperand(0).getReg();
     // Operands[1] will be the first operand, DestReg.
     SMLoc Loc = Operands[1]->getStartLoc();
     if (Constraints & RISCVII::VS2Constraint) {
       unsigned CheckReg = Inst.getOperand(1).getReg();
       if (DestReg == CheckReg)
         return Error(Loc, "The destination vector register group cannot overlap"
                           " the source vector register group.");
     }
     if ((Constraints & RISCVII::VS1Constraint) && (Inst.getOperand(2).isReg())) {
       unsigned CheckReg = Inst.getOperand(2).getReg();
       if (DestReg == CheckReg)
         return Error(Loc, "The destination vector register group cannot overlap"
                           " the source vector register group.");
     }
     if ((Constraints & RISCVII::VMConstraint) && (DestReg == RISCV::V0)) {
       // vadc, vsbc are special cases. These instructions have no mask register.
       // The destination register could not be V0.
       if (Opcode == RISCV::VADC_VVM || Opcode == RISCV::VADC_VXM ||
           Opcode == RISCV::VADC_VIM || Opcode == RISCV::VSBC_VVM ||
           Opcode == RISCV::VSBC_VXM || Opcode == RISCV::VFMERGE_VFM ||
           Opcode == RISCV::VMERGE_VIM || Opcode == RISCV::VMERGE_VVM ||
           Opcode == RISCV::VMERGE_VXM)
         return Error(Loc, "The destination vector register group cannot be V0.");
 
       // Regardless masked or unmasked version, the number of operands is the
       // same. For example, "viota.m v0, v2" is "viota.m v0, v2, NoRegister"
       // actually. We need to check the last operand to ensure whether it is
       // masked or not.
       unsigned CheckReg = Inst.getOperand(Inst.getNumOperands() - 1).getReg();
       assert((CheckReg == RISCV::V0 || CheckReg == RISCV::NoRegister) &&
              "Unexpected register for mask operand");
 
       if (DestReg == CheckReg)
         return Error(Loc, "The destination vector register group cannot overlap"
                           " the mask register.");
     }
+  }
+
   return false;
 }
 
 bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
                                         OperandVector &Operands,
                                         MCStreamer &Out) {
   Inst.setLoc(IDLoc);
 

llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

 //===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if ((Bytes[0] & 0x3) == 0x3) {
     }
     if (STI.hasFeature(RISCV::FeatureVendorXTHeadVdot)) {
       LLVM_DEBUG(dbgs() << "Trying XTHeadVdot custom opcode table:\n");
       Result =
           decodeInstruction(DecoderTableTHeadV32, MI, Insn, Address, this, STI);
       if (Result != MCDisassembler::Fail)
         return Result;
     }
+    if (STI.hasFeature(RISCV::FeatureVendorXSfvcp)) {
+      LLVM_DEBUG(dbgs() << "Trying SiFive VCIX custom opcode table:\n");
+      Result = decodeInstruction(DecoderTableXSfvcp32, MI, Insn, Address, this,
+                                 STI);
+      if (Result != MCDisassembler::Fail)
+        return Result;
+    }
 
     LLVM_DEBUG(dbgs() << "Trying RISCV32 table :\n");
     return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
   }
 
   if (Bytes.size() < 2) {
     Size = 0;
     return MCDisassembler::Fail;

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

 //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
enum {
   // multiple "bitmask" flags.
   MO_DIRECT_FLAG_MASK = 15
 };
 } // namespace RISCVII
 
 namespace RISCVOp {
 enum OperandType : unsigned {
   OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
-  OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM,
+  OPERAND_UIMM1 = OPERAND_FIRST_RISCV_IMM,
+  OPERAND_UIMM2,
   OPERAND_UIMM2_LSB0,
   OPERAND_UIMM3,
   OPERAND_UIMM4,
   OPERAND_UIMM5,
   OPERAND_UIMM7,
   OPERAND_UIMM7_LSB00,
   OPERAND_UIMM8_LSB00,
   OPERAND_UIMM8_LSB000,

llvm/lib/Target/RISCV/RISCVFeatures.td

 def FeatureVendorXTHeadVdot
     : SubtargetFeature<"xtheadvdot", "HasVendorXTHeadVdot", "true",
                        "'xtheadvdot' (T-Head Vector Extensions for Dot)",
                        [FeatureStdExtV]>;
 def HasVendorXTHeadVdot : Predicate<"Subtarget->hasVendorXTHeadVdot()">,
                                     AssemblerPredicate<(all_of FeatureVendorXTHeadVdot),
                                     "'xtheadvdot' (T-Head Vector Extensions for Dot)">;
 
+def FeatureVendorXSfvcp
+    : SubtargetFeature<"xsfvcp", "HasVendorXSfvcp", "true",
+                       "XSfvcp (SiFive custom vector coprocessor interface instructions)",
+                       [FeatureStdExtZve32x]>;
+def HasVendorXSfvcp : Predicate<"Subtarget->hasVendorXSfvcp()">,
+                                AssemblerPredicate<(all_of FeatureVendorXSfvcp),
+                                "'XSfvcp' (SiFive custom vector coprocessor interface instructions)">;
+
 //===----------------------------------------------------------------------===//
 // LLVM specific features and extensions
 //===----------------------------------------------------------------------===//
 
 // Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
 // tuning CPU names.
 def Feature32Bit
     : SubtargetFeature<"32bit", "HasRV32", "true", "Implements RV32">;

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

 //===-- RISCVInstrInfo.cpp - RISCV Instruction Information ------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (OpType >= RISCVOp::OPERAND_FIRST_RISCV_IMM &&
         default:
           llvm_unreachable("Unexpected operand type");
 
           // clang-format off
 #define CASE_OPERAND_UIMM(NUM)                                                 \
   case RISCVOp::OPERAND_UIMM##NUM:                                             \
     Ok = isUInt<NUM>(Imm);                                                     \
     break;
+        CASE_OPERAND_UIMM(1)
         CASE_OPERAND_UIMM(2)
         CASE_OPERAND_UIMM(3)
         CASE_OPERAND_UIMM(4)
         CASE_OPERAND_UIMM(5)
         CASE_OPERAND_UIMM(7)
         CASE_OPERAND_UIMM(12)
         CASE_OPERAND_UIMM(20)
           // clang-format on

llvm/lib/Target/RISCV/RISCVInstrInfo.td

let MCOperandPredicate = [{
     if (STI.getTargetTriple().isArch64Bit())
       return isUInt<6>(Imm);
     return isUInt<5>(Imm);
   }];
   let OperandType = "OPERAND_UIMMLOG2XLEN";
   let OperandNamespace = "RISCVOp";
 }
 
+def uimm1 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<1>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<1>;
+  let DecoderMethod = "decodeUImmOperand<1>";
+  let OperandType = "OPERAND_UIMM1";
+  let OperandNamespace = "RISCVOp";
+}
+
 def uimm2 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<2>;
   let DecoderMethod = "decodeUImmOperand<2>";
   let OperandType = "OPERAND_UIMM2";
   let OperandNamespace = "RISCVOp";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (!MCOp.evaluateAsConstantImm(Imm))

 include "RISCVInstrInfoZicbo.td"
 
 //===----------------------------------------------------------------------===//
 // Vendor extensions
 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrInfoXVentana.td"
 include "RISCVInstrInfoXTHead.td"
+include "RISCVInstrInfoXsf.td"

llvm/lib/Target/RISCV/RISCVInstrInfoXsf.td

+//===-- RISCVInstrInfoXsf.td - SiFive custom instructions --*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the vendor extensions defined by SiFive.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// XSFVCP extension instructions.
+//===----------------------------------------------------------------------===//
+
+def VCIXVS2    : RISCVVConstraint<VS2Constraint.Value>;
+def VCIXVS2VS1 : RISCVVConstraint<!or(VS2Constraint.Value,
+                                      VS1Constraint.Value)>;
+
+class VCIXType<bits<4> val> {
+  bits<4> Val = val;
+}
+
+def VCIX_X   : VCIXType<0b0000>;
+def VCIX_XV  : VCIXType<0b0010>;
+def VCIX_XVV : VCIXType<0b1010>;
+def VCIX_XVW : VCIXType<0b1111>;
+
+class SwapVCIXIns<dag funct6, dag rd, dag rs2, dag rs1, bit swap> {
+  dag Ins = !con(funct6, !if(swap, rs2, rd), !if(swap, rd, rs2), rs1);
+}
+
+class RVInstVCCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins,
+                      string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> rs2;
+  bits<5> rs1;
+  bits<5> rd;
+  bits<2> funct6_lo2;
+  bit vm;
+
+  let Inst{31-28} = funct6_hi4;
+  let Inst{27-26} = funct6_lo2;
+  let Inst{25} = vm;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = OPC_CUSTOM_2.Value;
+
+  let Uses = [VTYPE, VL];
+  let RVVConstraint = NoConstraint;
+}
+
+class RVInstVCFCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins,
+                       string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> rs2;
+  bits<5> rs1;
+  bits<5> rd;
+  bit funct6_lo1;
+  bit vm;
+
+  let Inst{31-28} = funct6_hi4;
+  let Inst{27} = 1;
+  let Inst{26} = funct6_lo1;
+  let Inst{25} = vm;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = OPC_CUSTOM_2.Value;
+
+  let Uses = [VTYPE, VL];
+  let RVVConstraint = NoConstraint;
+}
+
+class VCIXInfo<string suffix, VCIXType type, DAGOperand TyRd,
+               DAGOperand TyRs2, DAGOperand TyRs1, bit HaveOutputDst> {
+  string OpcodeStr = !if(HaveOutputDst, "sf.vc.v." # suffix,
+                                        "sf.vc." # suffix);
+  bits<4> Funct6_hi4 = type.Val;
+  bits<3> Funct3 = !cond(!eq(TyRs1, VR):    0b000,
+                         !eq(TyRs1, GPR):   0b100,
+                         !eq(TyRs1, FPR32): 0b101,
+                         !eq(TyRs1, simm5): 0b011);
+  dag Outs = !if(!not(HaveOutputDst), (outs),
+                 !if(!or(!eq(type, VCIX_XVV), !eq(type, VCIX_XVW)),
+                     (outs TyRd:$rd_wb), (outs TyRd:$rd)));
+  dag Ins = SwapVCIXIns<!if(!ne(TyRs1, FPR32), (ins uimm2:$funct6_lo2),
+                                               (ins uimm1:$funct6_lo1)),
+                        !if(!and(HaveOutputDst, !or(!eq(type, VCIX_X),
+                                                    !eq(type, VCIX_XV))),
+                            (ins), (ins TyRd:$rd)),
+                        (ins TyRs2:$rs2),
+                        (ins TyRs1:$rs1),
+                        !if(!eq(type, VCIX_X), 1, 0)>.Ins;
+  string Prototype = !if(!eq(type, VCIX_X), "$funct6_lo2, $rs2, $rd, $rs1",
+                         !if(!ne(TyRs1, FPR32), "$funct6_lo2, $rd, $rs2, $rs1",
+                                                "$funct6_lo1, $rd, $rs2, $rs1"));
+  string Constraints = !if(!not(HaveOutputDst), "",
+                           !if(!or(!eq(type, VCIX_XVV),
+                                   !eq(type, VCIX_XVW)), "$rd = $rd_wb", ""));
+  RISCVVConstraint RVVConstraint = !if(!or(!not(HaveOutputDst),
+                                           !ne(type, VCIX_XVW)), NoConstraint,
+                                       !if(!eq(TyRs1, VR), VCIXVS2VS1, VCIXVS2));
+}
+
+class CustomSiFiveVCIX<VCIXInfo info>
+  : RVInstVCCustom2<info.Funct6_hi4, info.Funct3, info.Outs,
+                    info.Ins, info.OpcodeStr, info.Prototype> {
+  let Constraints = info.Constraints;
+  let RVVConstraint = info.RVVConstraint;
+}
+
+class CustomSiFiveVCIF<VCIXInfo info>
+  : RVInstVCFCustom2<info.Funct6_hi4, info.Funct3, info.Outs,
+                     info.Ins, info.OpcodeStr, info.Prototype> {
+  let Constraints = info.Constraints;
+  let RVVConstraint = info.RVVConstraint;
+}
+
+multiclass CustomSiFiveVCIXorVCIF<string suffix, VCIXType type,
+                                  DAGOperand TyRd, DAGOperand TyRs2,
+                                  DAGOperand TyRs1, bit HaveOutputDst> {
+  defvar info = VCIXInfo<suffix, type, TyRd, TyRs2, TyRs1, HaveOutputDst>;
+  if !eq(TyRs1, FPR32) then {
+    def NAME : CustomSiFiveVCIF<info>;
+  } else {
+    def NAME : CustomSiFiveVCIX<info>;
+  }
+}
+
+multiclass CustomSiFiveVCIX<string suffix, VCIXType type,
+                            DAGOperand InTyRd, DAGOperand InTyRs2,
+                            DAGOperand InTyRs1> {
+  let vm = 1 in
+  defm VC_ # NAME   : CustomSiFiveVCIXorVCIF<suffix, type, InTyRd, InTyRs2,
+                                             InTyRs1, 0>;
+  let vm = 0 in
+  defm VC_V_ # NAME : CustomSiFiveVCIXorVCIF<suffix, type, VR, InTyRs2,
+                                             InTyRs1, 1>;
+}
+
+let Predicates = [HasVendorXSfvcp], mayLoad = 0, mayStore = 0,
+    hasSideEffects = 1, hasNoSchedulingInfo = 1, DecoderNamespace = "XSfvcp" in {
+  defm X   : CustomSiFiveVCIX<"x",   VCIX_X,   uimm5, uimm5, GPR>,   Sched<[]>;
+  defm I   : CustomSiFiveVCIX<"i",   VCIX_X,   uimm5, uimm5, simm5>, Sched<[]>;
+  defm XV  : CustomSiFiveVCIX<"xv",  VCIX_XV,  uimm5, VR,    GPR>,   Sched<[]>;
+  defm IV  : CustomSiFiveVCIX<"iv",  VCIX_XV,  uimm5, VR,    simm5>, Sched<[]>;
+  defm VV  : CustomSiFiveVCIX<"vv",  VCIX_XV,  uimm5, VR,    VR>,    Sched<[]>;
+  defm FV  : CustomSiFiveVCIX<"fv",  VCIX_XV,  uimm5, VR,    FPR32>, Sched<[]>;
+  defm XVV : CustomSiFiveVCIX<"xvv", VCIX_XVV, VR,    VR,    GPR>,   Sched<[]>;
+  defm IVV : CustomSiFiveVCIX<"ivv", VCIX_XVV, VR,    VR,    simm5>, Sched<[]>;
+  defm VVV : CustomSiFiveVCIX<"vvv", VCIX_XVV, VR,    VR,    VR>,    Sched<[]>;
+  defm FVV : CustomSiFiveVCIX<"fvv", VCIX_XVV, VR,    VR,    FPR32>, Sched<[]>;
+  defm XVW : CustomSiFiveVCIX<"xvw", VCIX_XVW, VR,    VR,    GPR>,   Sched<[]>;
+  defm IVW : CustomSiFiveVCIX<"ivw", VCIX_XVW, VR,    VR,    simm5>, Sched<[]>;
+  defm VVW : CustomSiFiveVCIX<"vvw", VCIX_XVW, VR,    VR,    VR>,    Sched<[]>;
+  defm FVW : CustomSiFiveVCIX<"fvw", VCIX_XVW, VR,    VR,    FPR32>, Sched<[]>;
+}

llvm/test/MC/RISCV/attribute-arch.s

 # CHECK: attribute      5, "rv32i2p0_zcd1p0"
 
 .attribute arch, "rv32izcf1p0"
 # CHECK: attribute      5, "rv32i2p0_zcf1p0"
 
 .attribute arch, "rv32izcb1p0"
 # CHECK: attribute      5, "rv32i2p0_zca1p0_zcb1p0"
 
+.attribute arch, "rv64i_xsfvcp"
+# CHECK: attribute      5, "rv64i2p0_zve32x1p0_zvl32b1p0_xsfvcp1p0"
+
 .attribute arch, "rv32izawrs1p0"
 # CHECK: attribute      5, "rv32i2p0_zawrs1p0"
 
 .attribute arch, "rv32iztso0p1"
 # CHECK: attribute      5, "rv32i2p0_ztso0p1"
 
 .attribute arch, "rv32izicsr2p0"
 # CHECK: attribute      5, "rv32i2p0_zicsr2p0"
 
 .attribute arch, "rv32izifencei2p0"
 # CHECK: attribute      5, "rv32i2p0_zifencei2p0"
 
 .attribute arch, "rv32izfa0p1"
 # CHECK: attribute      5, "rv32i2p0_f2p0_zfa0p1"

llvm/test/MC/RISCV/rvv/xsfvcp-invalid.s

+# RUN: not llvm-mc -triple=riscv64 --mattr=+v,+xsfvcp %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+
+sf.vc.v.vvw 0x3, v0, v2, v0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.{{$}}
+# CHECK-ERROR-LABEL: sf.vc.v.vvw 0x3, v0, v2, v0{{$}}
+
+sf.vc.v.xvw 0x3, v0, v0, a1
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.{{$}}
+# CHECK-ERROR-LABEL: sf.vc.v.xvw 0x3, v0, v0, a1{{$}}
+
+sf.vc.v.ivw 0x3, v0, v0, 15
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.{{$}}
+# CHECK-ERROR-LABEL: sf.vc.v.ivw 0x3, v0, v0, 15{{$}}
+
+sf.vc.v.fvw 0x1, v0, v0, fa1
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.{{$}}
+# CHECK-ERROR-LABEL: sf.vc.v.fvw 0x1, v0, v0, fa1{{$}}

llvm/test/MC/RISCV/rvv/xsfvcp.s

+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+v,+xsfvcp %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+v,+xsfvcp %s \
+# RUN:        | llvm-objdump -d --mattr=+v,+xsfvcp - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+v,+xsfvcp %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+sf.vc.x 0x3, 0xf, 0x1f, a1
+# CHECK-INST: sf.vc.x 3, 15, 31, a1
+# CHECK-ENCODING: [0xdb,0xcf,0xf5,0x0e]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: db cf f5 0e <unknown>
+
+sf.vc.i 0x3, 0xf, 0x1f, 15
+# CHECK-INST: sf.vc.i 3, 15, 31, 15
+# CHECK-ENCODING: [0xdb,0xbf,0xf7,0x0e]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: db bf f7 0e <unknown>
+
+sf.vc.vv 0x3, 0x1f, v2, v1
+# CHECK-INST: sf.vc.vv 3, 31, v2, v1
+# CHECK-ENCODING: [0xdb,0x8f,0x20,0x2e]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: db 8f 20 2e <unknown>
+
+sf.vc.xv 0x3, 0x1f, v2, a1
+# CHECK-INST: sf.vc.xv 3, 31, v2, a1
+# CHECK-ENCODING: [0xdb,0xcf,0x25,0x2e]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: db cf 25 2e <unknown>
+
+sf.vc.iv 0x3, 0x1f, v2, 15
+# CHECK-INST: sf.vc.iv 3, 31, v2, 15
+# CHECK-ENCODING: [0xdb,0xbf,0x27,0x2e]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: db bf 27 2e <unknown>
+
+sf.vc.fv 0x1, 0x1f, v2, fa1
+# CHECK-INST: sf.vc.fv 1, 31, v2, fa1
+# CHECK-ENCODING: [0xdb,0xdf,0x25,0x2e]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: db df 25 2e <unknown>
+
+sf.vc.vvv 0x3, v0, v2, v1
+# CHECK-INST: sf.vc.vvv 3, v0, v2, v1
+# CHECK-ENCODING: [0x5b,0x80,0x20,0xae]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b 80 20 ae <unknown>
+
+sf.vc.xvv 0x3, v0, v2, a1
+# CHECK-INST: sf.vc.xvv 3, v0, v2, a1
+# CHECK-ENCODING: [0x5b,0xc0,0x25,0xae]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b c0 25 ae <unknown>
+
+sf.vc.ivv 0x3, v0, v2, 15
+# CHECK-INST: sf.vc.ivv 3, v0, v2, 15
+# CHECK-ENCODING: [0x5b,0xb0,0x27,0xae]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b b0 27 ae <unknown>
+
+sf.vc.fvv 0x1, v0, v2, fa1
+# CHECK-INST: sf.vc.fvv 1, v0, v2, fa1
+# CHECK-ENCODING: [0x5b,0xd0,0x25,0xae]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b d0 25 ae <unknown>
+
+sf.vc.vvw 0x3, v0, v2, v1
+# CHECK-INST: sf.vc.vvw 3, v0, v2, v1
+# CHECK-ENCODING: [0x5b,0x80,0x20,0xfe]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b 80 20 fe <unknown>
+
+sf.vc.xvw 0x3, v0, v2, a1
+# CHECK-INST: sf.vc.xvw 3, v0, v2, a1
+# CHECK-ENCODING: [0x5b,0xc0,0x25,0xfe]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b c0 25 fe <unknown>
+
+sf.vc.ivw 0x3, v0, v2, 15
+# CHECK-INST: sf.vc.ivw 3, v0, v2, 15
+# CHECK-ENCODING: [0x5b,0xb0,0x27,0xfe]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b b0 27 fe <unknown>
+
+sf.vc.fvw 0x1, v0, v2, fa1
+# CHECK-INST: sf.vc.fvw 1, v0, v2, fa1
+# CHECK-ENCODING: [0x5b,0xd0,0x25,0xfe]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b d0 25 fe <unknown>
+
+sf.vc.v.x 0x3, 0xf, v0, a1
+# CHECK-INST: sf.vc.v.x 3, 15, v0, a1
+# CHECK-ENCODING: [0x5b,0xc0,0xf5,0x0c]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b c0 f5 0c <unknown>
+
+sf.vc.v.i 0x3, 0xf, v0, 15
+# CHECK-INST: sf.vc.v.i 3, 15, v0, 15
+# CHECK-ENCODING: [0x5b,0xb0,0xf7,0x0c]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b b0 f7 0c <unknown>
+
+sf.vc.v.vv 0x3, v0, v2, v1
+# CHECK-INST: sf.vc.v.vv 3, v0, v2, v1
+# CHECK-ENCODING: [0x5b,0x80,0x20,0x2c]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b 80 20 2c <unknown>
+
+sf.vc.v.xv 0x3, v0, v2, a1
+# CHECK-INST: sf.vc.v.xv 3, v0, v2, a1
+# CHECK-ENCODING: [0x5b,0xc0,0x25,0x2c]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b c0 25 2c <unknown>
+
+sf.vc.v.iv 0x3, v0, v2, 15
+# CHECK-INST: sf.vc.v.iv 3, v0, v2, 15
+# CHECK-ENCODING: [0x5b,0xb0,0x27,0x2c]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b b0 27 2c <unknown>
+
+sf.vc.v.fv 0x1, v0, v2, fa1
+# CHECK-INST: sf.vc.v.fv 1, v0, v2, fa1
+# CHECK-ENCODING: [0x5b,0xd0,0x25,0x2c]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b d0 25 2c <unknown>
+
+sf.vc.v.vvv 0x3, v0, v2, v1
+# CHECK-INST: sf.vc.v.vvv 3, v0, v2, v1
+# CHECK-ENCODING: [0x5b,0x80,0x20,0xac]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b 80 20 ac <unknown>
+
+sf.vc.v.xvv 0x3, v0, v2, a1
+# CHECK-INST: sf.vc.v.xvv 3, v0, v2, a1
+# CHECK-ENCODING: [0x5b,0xc0,0x25,0xac]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b c0 25 ac <unknown>
+
+sf.vc.v.ivv 0x3, v0, v2, 15
+# CHECK-INST: sf.vc.v.ivv 3, v0, v2, 15
+# CHECK-ENCODING: [0x5b,0xb0,0x27,0xac]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b b0 27 ac <unknown>
+
+sf.vc.v.fvv 0x1, v0, v2, fa1
+# CHECK-INST: sf.vc.v.fvv 1, v0, v2, fa1
+# CHECK-ENCODING: [0x5b,0xd0,0x25,0xac]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b d0 25 ac <unknown>
+
+sf.vc.v.vvw 0x3, v0, v2, v1
+# CHECK-INST: sf.vc.v.vvw 3, v0, v2, v1
+# CHECK-ENCODING: [0x5b,0x80,0x20,0xfc]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b 80 20 fc <unknown>
+
+sf.vc.v.xvw 0x3, v0, v2, a1
+# CHECK-INST: sf.vc.v.xvw 3, v0, v2, a1
+# CHECK-ENCODING: [0x5b,0xc0,0x25,0xfc]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b c0 25 fc <unknown>
+
+sf.vc.v.ivw 0x3, v0, v2, 15
+# CHECK-INST: sf.vc.v.ivw 3, v0, v2, 15
+# CHECK-ENCODING: [0x5b,0xb0,0x27,0xfc]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b b0 27 fc <unknown>
+
+sf.vc.v.fvw 0x1, v0, v2, fa1
+# CHECK-INST: sf.vc.v.fvw 1, v0, v2, fa1
+# CHECK-ENCODING: [0x5b,0xd0,0x25,0xfc]
+# CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive custom vector coprocessor interface instructions){{$}}
+# CHECK-UNKNOWN: 5b d0 25 fc <unknown>