[RISCV] Use OS-specific SafeStack ABI for Fuchsia

[mcgrathr]

Summary

Fuchsia provides a slot relative to tp for the unsafe stack pointer.

[jrtc27]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

13272

Leave unrelated functions alone

llvm/test/Transforms/SafeStack/RISCV/abi.ll

4

This is way too complicated and confusing to read. Just use --check-prefix=FUCHSIA and use update_test_checks.py to generate the CHECK lines. And probably this should have a non-Fuschia test too.

[jrtc27]

And *please* add RISCV backend maintainers and regular reviewers/committers as reviewers on such patches

[paulkirth]

Mostly this is LGTM modulo unrelated formatting. I'll let @jrtc27 decide if there's anything more required for RISCV, but the implementation and testing is consistent w/ ARM and AArch64.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

13272

nit: unrelated

13276

ditto.

[asb]

Thanks @mcgrathr - I've left an inline query.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

14249

I've not looked at the safe stack pointer code before, but I'd expect this to call TargetLowering::getSafeStackPointerLocation(IRB). Why doesn't it?

llvm/lib/Target/RISCV/RISCVISelLowering.h

bool isLegalScaleForGatherScatter(uint64_t Scale,
     // Scaled addressing not supported on indexed load/stores
     return Scale == 1;
   }
 
   /// If the target has a standard location for the stack protector cookie,
   /// returns the address of that location. Otherwise, returns nullptr.
   Value *getIRStackGuard(IRBuilderBase &IRB) const override;
 
+  /// If the target has a standard location for the unsafe stack pointer,
+  /// returns the address of that location. Otherwise, returns nullptr.
+  Value *getSafeStackPointerLocation(IRBuilderBase &IRB) const override;
+
 private:
   /// RISCVCCAssignFn - This target-specific function extends the default
   /// CCValAssign with additional information used to lower RISC-V calling
   /// conventions.
   typedef bool RISCVCCAssignFn(const DataLayout &DL, RISCVABI::ABI,
                                unsigned ValNo, MVT ValVT, MVT LocVT,
                                CCValAssign::LocInfo LocInfo,
                                ISD::ArgFlagsTy ArgFlags, CCState &State,

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 // otherwise we can't perform a tail-call.
 bool RISCVTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
   if (N->getNumValues() != 1)
     return false;
   if (!N->hasNUsesOfValue(1, 0))
     return false;
 
   SDNode *Copy = *N->use_begin();
-  
   if (Copy->getOpcode() == ISD::BITCAST) {
     return isUsedByReturnOnly(Copy, Chain);
   }
-  
   // TODO: Handle additional opcodes in order to support tail-calling libcalls
   // with soft float ABIs.
   if (Copy->getOpcode() != ISD::CopyToReg) {
     return false;
   }
 
   // If the ISD::CopyToReg has a glue operand, we conservatively assume it
   // isn't safe to perform a tail call.
Value *RISCVTargetLowering::getIRStackGuard(IRBuilderBase &IRB) const {
   // Fuchsia provides a fixed TLS slot for the stack cookie.
   // <zircon/tls.h> defines ZX_TLS_STACK_GUARD_OFFSET with this value.
   if (Subtarget.isTargetFuchsia())
     return useTpOffset(IRB, -0x10);
 
   return TargetLowering::getIRStackGuard(IRB);
 }
 
+Value *RISCVTargetLowering::getSafeStackPointerLocation(IRBuilderBase &IRB) const {
+  // Fuchsia provides a fixed TLS slot for the unsafe stack pointer.
+  // <zircon/tls.h> defines ZX_TLS_UNSAFE_SP_OFFSET with this value.
+  if (Subtarget.isTargetFuchsia())
+    return useTpOffset(IRB, -0x8);
+
+  return TargetLowering::getIRStackGuard(IRB);
+}
+
 #define GET_REGISTER_MATCHER
 #include "RISCVGenAsmMatcher.inc"
 
 Register
 RISCVTargetLowering::getRegisterByName(const char *RegName, LLT VT,
                                        const MachineFunction &MF) const {
   Register Reg = MatchRegisterAltName(RegName);
   if (Reg == RISCV::NoRegister)

llvm/test/Transforms/SafeStack/RISCV/abi.ll

+; RUN: opt -safe-stack -S -mtriple=riscv64-fuchsia < %s -o - | FileCheck --check-prefixes=TLS,FUCHSIA %s
+
+define void @unsafe_stack_escapes() nounwind safestack {
+; TLS: %[[TP:.*]] = call ptr @llvm.thread.pointer()
+;; Another platform with a different TP offset would use PLATFORM: here.
+; FUCHSIA: %[[UnsafeSpPtr:.*]] = getelementptr i8, ptr %[[TP]], i32 -8
+; TLS: %[[OldSp:.*]] = load ptr, ptr %[[UnsafeSpPtr]]
+; TLS: %[[NewSp:.*]] = getelementptr i8, ptr %[[OldSp]], i32 -16
+; TLS: store ptr %[[NewSp]], ptr %[[UnsafeSpPtr]]
+
+  %a = alloca i8, align 8
+  call void @capture(ptr %a)
+
+; CHECK: store ptr %[[OldSp]], ptr %[[UnsafeSpPtr]]
+  ret void
+}
+
+declare void @capture(ptr)

llvm/test/Transforms/SafeStack/RISCV/abi_ssp.ll

+; RUN: opt -safe-stack -S -mtriple=riscv64-fuchsia < %s -o - | FileCheck --check-prefixes=TLS,FUCHSIA %s
+
+define void @unsafe_stack_escapes() nounwind safestack sspreq {
+;; First the TP will be fetched to fetch the USP (tested in abi.ll); skip that.
+; TLS: %[[TpForUsp:.*]] = call ptr @llvm.thread.pointer()
+;; The second TP fetch will be the one to get the stack guard value.
+; TLS: %[[TpForGuard:.*]] = call ptr @llvm.thread.pointer()
+;; Another platform with a different TP offset would use PLATFORM: here.
+; FUCHSIA: %[[GuardPtr:.*]] = getelementptr i8, ptr %[[TpForGuard]], i32 -16
+; TLS: %[[GuardValue:.*]] = load ptr, ptr %[[GuardPtr]]
+; TLS: store ptr %[[GuardValue]], ptr %[[CanarySlot:.*]]
+
+  %a = alloca i8, align 8
+  call void @capture(ptr %a)
+
+; TLS: %[[CanaryValue:.*]] = load ptr, ptr %[[CanarySlot]]
+; TLS: icmp ne ptr %[[GuardValue]], %[[CanaryValue]]
+  ret void
+}
+
+declare void @capture(ptr)

llvm/test/Transforms/SafeStack/RISCV/lit.local.cfg

+if not 'RISCV' in config.root.targets:
+    config.unsupported = True